18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 28e99ea8dSJohannes Berg /* 3d9d115feSJohannes Berg * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #ifndef __iwl_trans_h__ 8e705c121SKalle Valo #define __iwl_trans_h__ 9e705c121SKalle Valo 10e705c121SKalle Valo #include <linux/ieee80211.h> 11e705c121SKalle Valo #include <linux/mm.h> /* for page_address */ 12e705c121SKalle Valo #include <linux/lockdep.h> 1339bdb17eSSharon Dvir #include <linux/kernel.h> 14e705c121SKalle Valo 15e705c121SKalle Valo #include "iwl-debug.h" 16e705c121SKalle Valo #include "iwl-config.h" 17d962f9b1SJohannes Berg #include "fw/img.h" 18e705c121SKalle Valo #include "iwl-op-mode.h" 1969725928SLuca Coelho #include <linux/firmware.h> 20d172a5efSJohannes Berg #include "fw/api/cmdhdr.h" 21d172a5efSJohannes Berg #include "fw/api/txq.h" 22f14cda6fSSara Sharon #include "fw/api/dbg-tlv.h" 23f14cda6fSSara Sharon #include "iwl-dbg-tlv.h" 24e705c121SKalle Valo 25e705c121SKalle Valo /** 26e705c121SKalle Valo * DOC: Transport layer - what is it ? 27e705c121SKalle Valo * 28e705c121SKalle Valo * The transport layer is the layer that deals with the HW directly. It provides 29e705c121SKalle Valo * an abstraction of the underlying HW to the upper layer. The transport layer 30e705c121SKalle Valo * doesn't provide any policy, algorithm or anything of this kind, but only 31e705c121SKalle Valo * mechanisms to make the HW do something. It is not completely stateless but 32e705c121SKalle Valo * close to it. 33e705c121SKalle Valo * We will have an implementation for each different supported bus. 34e705c121SKalle Valo */ 35e705c121SKalle Valo 36e705c121SKalle Valo /** 37e705c121SKalle Valo * DOC: Life cycle of the transport layer 38e705c121SKalle Valo * 39e705c121SKalle Valo * The transport layer has a very precise life cycle. 40e705c121SKalle Valo * 41e705c121SKalle Valo * 1) A helper function is called during the module initialization and 42e705c121SKalle Valo * registers the bus driver's ops with the transport's alloc function. 43e705c121SKalle Valo * 2) Bus's probe calls to the transport layer's allocation functions. 44e705c121SKalle Valo * Of course this function is bus specific. 45e705c121SKalle Valo * 3) This allocation functions will spawn the upper layer which will 46e705c121SKalle Valo * register mac80211. 47e705c121SKalle Valo * 48e705c121SKalle Valo * 4) At some point (i.e. mac80211's start call), the op_mode will call 49e705c121SKalle Valo * the following sequence: 50e705c121SKalle Valo * start_hw 51e705c121SKalle Valo * start_fw 52e705c121SKalle Valo * 53e705c121SKalle Valo * 5) Then when finished (or reset): 54e705c121SKalle Valo * stop_device 55e705c121SKalle Valo * 56e705c121SKalle Valo * 6) Eventually, the free function will be called. 57e705c121SKalle Valo */ 58e705c121SKalle Valo 59e701da0cSLuca Coelho #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 60e701da0cSLuca Coelho 61e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 62e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID 0x55550000 63e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN 0x40 64fbe41127SSara Sharon #define FH_RSCSR_RPA_EN BIT(25) 659d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN BIT(26) 66ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS 16 67ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK 0x3F0000 68e705c121SKalle Valo 69e705c121SKalle Valo struct iwl_rx_packet { 70e705c121SKalle Valo /* 71e705c121SKalle Valo * The first 4 bytes of the RX frame header contain both the RX frame 72e705c121SKalle Valo * size and some flags. 73e705c121SKalle Valo * Bit fields: 74e705c121SKalle Valo * 31: flag flush RB request 75e705c121SKalle Valo * 30: flag ignore TC (terminal counter) request 76e705c121SKalle Valo * 29: flag fast IRQ request 779d0fc5a5SDavid Spinadel * 28-27: Reserved 789d0fc5a5SDavid Spinadel * 26: RADA enabled 79fbe41127SSara Sharon * 25: Offload enabled 80ab2e696bSSara Sharon * 24: RPF enabled 81ab2e696bSSara Sharon * 23: RSS enabled 82ab2e696bSSara Sharon * 22: Checksum enabled 83ab2e696bSSara Sharon * 21-16: RX queue 84ab2e696bSSara Sharon * 15-14: Reserved 85e705c121SKalle Valo * 13-00: RX frame size 86e705c121SKalle Valo */ 87e705c121SKalle Valo __le32 len_n_flags; 88e705c121SKalle Valo struct iwl_cmd_header hdr; 89e705c121SKalle Valo u8 data[]; 90e705c121SKalle Valo } __packed; 91e705c121SKalle Valo 92e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 93e705c121SKalle Valo { 94e705c121SKalle Valo return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 95e705c121SKalle Valo } 96e705c121SKalle Valo 97e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 98e705c121SKalle Valo { 99e705c121SKalle Valo return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 100e705c121SKalle Valo } 101e705c121SKalle Valo 102e705c121SKalle Valo /** 103e705c121SKalle Valo * enum CMD_MODE - how to send the host commands ? 104e705c121SKalle Valo * 105e705c121SKalle Valo * @CMD_ASYNC: Return right away and don't wait for the response 106e705c121SKalle Valo * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 107e705c121SKalle Valo * the response. The caller needs to call iwl_free_resp when done. 108dcbb4746SEmmanuel Grumbach * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 109dcbb4746SEmmanuel Grumbach * called after this command completes. Valid only with CMD_ASYNC. 110708a39aaSHaim Dreyfuss * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to 111708a39aaSHaim Dreyfuss * SUSPEND and RESUME commands. We are in D3 mode when we set 112708a39aaSHaim Dreyfuss * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3. 113e705c121SKalle Valo */ 114e705c121SKalle Valo enum CMD_MODE { 115e705c121SKalle Valo CMD_ASYNC = BIT(0), 116e705c121SKalle Valo CMD_WANT_SKB = BIT(1), 117e705c121SKalle Valo CMD_SEND_IN_RFKILL = BIT(2), 118043fa901SEmmanuel Grumbach CMD_WANT_ASYNC_CALLBACK = BIT(3), 119708a39aaSHaim Dreyfuss CMD_SEND_IN_D3 = BIT(4), 120e705c121SKalle Valo }; 121e705c121SKalle Valo 122e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320 123e705c121SKalle Valo 124e705c121SKalle Valo /** 125e705c121SKalle Valo * struct iwl_device_cmd 126e705c121SKalle Valo * 127e705c121SKalle Valo * For allocation of the command and tx queues, this establishes the overall 128e705c121SKalle Valo * size of the largest command we send to uCode, except for commands that 129e705c121SKalle Valo * aren't fully copied and use other TFD space. 130e705c121SKalle Valo */ 131e705c121SKalle Valo struct iwl_device_cmd { 132e705c121SKalle Valo union { 133e705c121SKalle Valo struct { 134e705c121SKalle Valo struct iwl_cmd_header hdr; /* uCode API */ 135e705c121SKalle Valo u8 payload[DEF_CMD_PAYLOAD_SIZE]; 136e705c121SKalle Valo }; 137e705c121SKalle Valo struct { 138e705c121SKalle Valo struct iwl_cmd_header_wide hdr_wide; 139e705c121SKalle Valo u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 140e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide) + 141e705c121SKalle Valo sizeof(struct iwl_cmd_header)]; 142e705c121SKalle Valo }; 143e705c121SKalle Valo }; 144e705c121SKalle Valo } __packed; 145e705c121SKalle Valo 146a89c72ffSJohannes Berg /** 147a89c72ffSJohannes Berg * struct iwl_device_tx_cmd - buffer for TX command 148a89c72ffSJohannes Berg * @hdr: the header 149a89c72ffSJohannes Berg * @payload: the payload placeholder 150a89c72ffSJohannes Berg * 151a89c72ffSJohannes Berg * The actual structure is sized dynamically according to need. 152a89c72ffSJohannes Berg */ 153a89c72ffSJohannes Berg struct iwl_device_tx_cmd { 154a89c72ffSJohannes Berg struct iwl_cmd_header hdr; 155a89c72ffSJohannes Berg u8 payload[]; 156a89c72ffSJohannes Berg } __packed; 157a89c72ffSJohannes Berg 158e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 159e705c121SKalle Valo 160e705c121SKalle Valo /* 161e705c121SKalle Valo * number of transfer buffers (fragments) per transmit frame descriptor; 162e705c121SKalle Valo * this is just the driver's idea, the hardware supports 20 163e705c121SKalle Valo */ 164e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD 2 165e705c121SKalle Valo 166885375d0SMordechay Goodstein /* We need 2 entries for the TX command and header, and another one might 167885375d0SMordechay Goodstein * be needed for potential data in the SKB's head. The remaining ones can 168885375d0SMordechay Goodstein * be used for frags. 169885375d0SMordechay Goodstein */ 170885375d0SMordechay Goodstein #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 171885375d0SMordechay Goodstein 172e705c121SKalle Valo /** 173b8aed81cSJohannes Berg * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 174e705c121SKalle Valo * 175e705c121SKalle Valo * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 176e705c121SKalle Valo * ring. The transport layer doesn't map the command's buffer to DMA, but 177e705c121SKalle Valo * rather copies it to a previously allocated DMA buffer. This flag tells 178e705c121SKalle Valo * the transport layer not to copy the command, but to map the existing 179e705c121SKalle Valo * buffer (that is passed in) instead. This saves the memcpy and allows 180e705c121SKalle Valo * commands that are bigger than the fixed buffer to be submitted. 181e705c121SKalle Valo * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 182e705c121SKalle Valo * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 183e705c121SKalle Valo * chunk internally and free it again after the command completes. This 184e705c121SKalle Valo * can (currently) be used only once per command. 185e705c121SKalle Valo * Note that a TFD entry after a DUP one cannot be a normal copied one. 186e705c121SKalle Valo */ 187e705c121SKalle Valo enum iwl_hcmd_dataflag { 188e705c121SKalle Valo IWL_HCMD_DFL_NOCOPY = BIT(0), 189e705c121SKalle Valo IWL_HCMD_DFL_DUP = BIT(1), 190e705c121SKalle Valo }; 191e705c121SKalle Valo 19222463857SShahar S Matityahu enum iwl_error_event_table_status { 19322463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 19422463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 19522463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 19657417e1bSJohannes Berg IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3), 19757417e1bSJohannes Berg IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4), 1984cd177b4SJohannes Berg IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5), 1994cd177b4SJohannes Berg IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6), 20022463857SShahar S Matityahu }; 20122463857SShahar S Matityahu 202e705c121SKalle Valo /** 203e705c121SKalle Valo * struct iwl_host_cmd - Host command to the uCode 204e705c121SKalle Valo * 205e705c121SKalle Valo * @data: array of chunks that composes the data of the host command 206e705c121SKalle Valo * @resp_pkt: response packet, if %CMD_WANT_SKB was set 207e705c121SKalle Valo * @_rx_page_order: (internally used to free response packet) 208e705c121SKalle Valo * @_rx_page_addr: (internally used to free response packet) 209e705c121SKalle Valo * @flags: can be CMD_* 210e705c121SKalle Valo * @len: array of the lengths of the chunks in data 211e705c121SKalle Valo * @dataflags: IWL_HCMD_DFL_* 212e705c121SKalle Valo * @id: command id of the host command, for wide commands encoding the 213e705c121SKalle Valo * version and group as well 214e705c121SKalle Valo */ 215e705c121SKalle Valo struct iwl_host_cmd { 216e705c121SKalle Valo const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 217e705c121SKalle Valo struct iwl_rx_packet *resp_pkt; 218e705c121SKalle Valo unsigned long _rx_page_addr; 219e705c121SKalle Valo u32 _rx_page_order; 220e705c121SKalle Valo 221e705c121SKalle Valo u32 flags; 222e705c121SKalle Valo u32 id; 223e705c121SKalle Valo u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 224e705c121SKalle Valo u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 225e705c121SKalle Valo }; 226e705c121SKalle Valo 227e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 228e705c121SKalle Valo { 229e705c121SKalle Valo free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 230e705c121SKalle Valo } 231e705c121SKalle Valo 232e705c121SKalle Valo struct iwl_rx_cmd_buffer { 233e705c121SKalle Valo struct page *_page; 234e705c121SKalle Valo int _offset; 235e705c121SKalle Valo bool _page_stolen; 236e705c121SKalle Valo u32 _rx_page_order; 237e705c121SKalle Valo unsigned int truesize; 238e705c121SKalle Valo }; 239e705c121SKalle Valo 240e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 241e705c121SKalle Valo { 242e705c121SKalle Valo return (void *)((unsigned long)page_address(r->_page) + r->_offset); 243e705c121SKalle Valo } 244e705c121SKalle Valo 245e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 246e705c121SKalle Valo { 247e705c121SKalle Valo return r->_offset; 248e705c121SKalle Valo } 249e705c121SKalle Valo 250e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 251e705c121SKalle Valo { 252e705c121SKalle Valo r->_page_stolen = true; 253e705c121SKalle Valo get_page(r->_page); 254e705c121SKalle Valo return r->_page; 255e705c121SKalle Valo } 256e705c121SKalle Valo 257e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 258e705c121SKalle Valo { 259e705c121SKalle Valo __free_pages(r->_page, r->_rx_page_order); 260e705c121SKalle Valo } 261e705c121SKalle Valo 262e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS 6 263e705c121SKalle Valo 264e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 265e705c121SKalle Valo 266e705c121SKalle Valo /* 267e705c121SKalle Valo * Maximum number of HW queues the transport layer 268e705c121SKalle Valo * currently supports 269e705c121SKalle Valo */ 270e705c121SKalle Valo #define IWL_MAX_HW_QUEUES 32 271e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES 512 272e982bc2cSSara Sharon 273e705c121SKalle Valo #define IWL_MAX_TID_COUNT 8 274c65f4e03SSara Sharon #define IWL_MGMT_TID 15 275e705c121SKalle Valo #define IWL_FRAME_LIMIT 64 276e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES 16 2770cd38f4dSMordechay Goodstein #define IWL_9000_MAX_RX_HW_QUEUES 6 278e705c121SKalle Valo 279e705c121SKalle Valo /** 280e705c121SKalle Valo * enum iwl_wowlan_status - WoWLAN image/device status 281e705c121SKalle Valo * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 282e705c121SKalle Valo * @IWL_D3_STATUS_RESET: device was reset while suspended 283e705c121SKalle Valo */ 284e705c121SKalle Valo enum iwl_d3_status { 285e705c121SKalle Valo IWL_D3_STATUS_ALIVE, 286e705c121SKalle Valo IWL_D3_STATUS_RESET, 287e705c121SKalle Valo }; 288e705c121SKalle Valo 289e705c121SKalle Valo /** 290e705c121SKalle Valo * enum iwl_trans_status: transport status flags 291e705c121SKalle Valo * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 292e705c121SKalle Valo * @STATUS_DEVICE_ENABLED: APM is enabled 293e705c121SKalle Valo * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 294e705c121SKalle Valo * @STATUS_INT_ENABLED: interrupts are enabled 295326477e4SJohannes Berg * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 296326477e4SJohannes Berg * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 297e705c121SKalle Valo * @STATUS_FW_ERROR: the fw is in error state 298e705c121SKalle Valo * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 299e705c121SKalle Valo * are sent 300e705c121SKalle Valo * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 301e705c121SKalle Valo * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 3024b992db6SJohannes Berg * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once, 3034b992db6SJohannes Berg * e.g. for testing 304e705c121SKalle Valo */ 305e705c121SKalle Valo enum iwl_trans_status { 306e705c121SKalle Valo STATUS_SYNC_HCMD_ACTIVE, 307e705c121SKalle Valo STATUS_DEVICE_ENABLED, 308e705c121SKalle Valo STATUS_TPOWER_PMI, 309e705c121SKalle Valo STATUS_INT_ENABLED, 310326477e4SJohannes Berg STATUS_RFKILL_HW, 311326477e4SJohannes Berg STATUS_RFKILL_OPMODE, 312e705c121SKalle Valo STATUS_FW_ERROR, 313e705c121SKalle Valo STATUS_TRANS_GOING_IDLE, 314e705c121SKalle Valo STATUS_TRANS_IDLE, 315e705c121SKalle Valo STATUS_TRANS_DEAD, 3164b992db6SJohannes Berg STATUS_SUPPRESS_CMD_ERROR_ONCE, 317e705c121SKalle Valo }; 318e705c121SKalle Valo 3196c4fbcbcSEmmanuel Grumbach static inline int 3206c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 3216c4fbcbcSEmmanuel Grumbach { 3226c4fbcbcSEmmanuel Grumbach switch (rb_size) { 3231a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 3241a4968d1SGolan Ben Ami return get_order(2 * 1024); 3256c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 3266c4fbcbcSEmmanuel Grumbach return get_order(4 * 1024); 3276c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 3286c4fbcbcSEmmanuel Grumbach return get_order(8 * 1024); 3296c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 3303fa965c2SJohannes Berg return get_order(16 * 1024); 3316c4fbcbcSEmmanuel Grumbach default: 3326c4fbcbcSEmmanuel Grumbach WARN_ON(1); 3336c4fbcbcSEmmanuel Grumbach return -1; 3346c4fbcbcSEmmanuel Grumbach } 3356c4fbcbcSEmmanuel Grumbach } 3366c4fbcbcSEmmanuel Grumbach 33780084e35SJohannes Berg static inline int 33880084e35SJohannes Berg iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 33980084e35SJohannes Berg { 34080084e35SJohannes Berg switch (rb_size) { 34180084e35SJohannes Berg case IWL_AMSDU_2K: 34280084e35SJohannes Berg return 2 * 1024; 34380084e35SJohannes Berg case IWL_AMSDU_4K: 34480084e35SJohannes Berg return 4 * 1024; 34580084e35SJohannes Berg case IWL_AMSDU_8K: 34680084e35SJohannes Berg return 8 * 1024; 34780084e35SJohannes Berg case IWL_AMSDU_12K: 3483fa965c2SJohannes Berg return 16 * 1024; 34980084e35SJohannes Berg default: 35080084e35SJohannes Berg WARN_ON(1); 35180084e35SJohannes Berg return 0; 35280084e35SJohannes Berg } 35380084e35SJohannes Berg } 35480084e35SJohannes Berg 35539bdb17eSSharon Dvir struct iwl_hcmd_names { 35639bdb17eSSharon Dvir u8 cmd_id; 35739bdb17eSSharon Dvir const char *const cmd_name; 35839bdb17eSSharon Dvir }; 35939bdb17eSSharon Dvir 36039bdb17eSSharon Dvir #define HCMD_NAME(x) \ 36139bdb17eSSharon Dvir { .cmd_id = x, .cmd_name = #x } 36239bdb17eSSharon Dvir 36339bdb17eSSharon Dvir struct iwl_hcmd_arr { 36439bdb17eSSharon Dvir const struct iwl_hcmd_names *arr; 36539bdb17eSSharon Dvir int size; 36639bdb17eSSharon Dvir }; 36739bdb17eSSharon Dvir 36839bdb17eSSharon Dvir #define HCMD_ARR(x) \ 36939bdb17eSSharon Dvir { .arr = x, .size = ARRAY_SIZE(x) } 37039bdb17eSSharon Dvir 371e705c121SKalle Valo /** 372fdb70083SJohannes Berg * struct iwl_dump_sanitize_ops - dump sanitization operations 373fdb70083SJohannes Berg * @frob_txf: Scrub the TX FIFO data 374fdb70083SJohannes Berg * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header 375fdb70083SJohannes Berg * but that might be short or long (&struct iwl_cmd_header or 376fdb70083SJohannes Berg * &struct iwl_cmd_header_wide) 377fdb70083SJohannes Berg * @frob_mem: Scrub memory data 378fdb70083SJohannes Berg */ 379fdb70083SJohannes Berg struct iwl_dump_sanitize_ops { 380fdb70083SJohannes Berg void (*frob_txf)(void *ctx, void *buf, size_t buflen); 381fdb70083SJohannes Berg void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen); 382fdb70083SJohannes Berg void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen); 383fdb70083SJohannes Berg }; 384fdb70083SJohannes Berg 385fdb70083SJohannes Berg /** 386e705c121SKalle Valo * struct iwl_trans_config - transport configuration 387e705c121SKalle Valo * 388e705c121SKalle Valo * @op_mode: pointer to the upper layer. 389e705c121SKalle Valo * @cmd_queue: the index of the command queue. 390e705c121SKalle Valo * Must be set before start_fw. 391e705c121SKalle Valo * @cmd_fifo: the fifo for host commands 392e705c121SKalle Valo * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 393e705c121SKalle Valo * @no_reclaim_cmds: Some devices erroneously don't set the 394e705c121SKalle Valo * SEQ_RX_FRAME bit on some notifications, this is the 395e705c121SKalle Valo * list of such notifications to filter. Max length is 396e705c121SKalle Valo * %MAX_NO_RECLAIM_CMDS. 397e705c121SKalle Valo * @n_no_reclaim_cmds: # of commands in list 3986c4fbcbcSEmmanuel Grumbach * @rx_buf_size: RX buffer size needed for A-MSDUs 399e705c121SKalle Valo * if unset 4k will be the RX buffer size 400e705c121SKalle Valo * @bc_table_dword: set to true if the BC table expects the byte count to be 401e705c121SKalle Valo * in DWORD (as opposed to bytes) 402e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 40339bdb17eSSharon Dvir * @command_groups: array of command groups, each member is an array of the 40439bdb17eSSharon Dvir * commands in the group; for debugging only 40539bdb17eSSharon Dvir * @command_groups_size: number of command groups, to avoid illegal access 40621cb3222SJohannes Berg * @cb_data_offs: offset inside skb->cb to store transport data at, must have 40721cb3222SJohannes Berg * space for at least two pointers 408906d4eb8SJohannes Berg * @fw_reset_handshake: firmware supports reset flow handshake 409227f2597SJohannes Berg * @queue_alloc_cmd_ver: queue allocation command version, set to 0 410227f2597SJohannes Berg * for using the older SCD_QUEUE_CFG, set to the version of 411227f2597SJohannes Berg * SCD_QUEUE_CONFIG_CMD otherwise. 412e705c121SKalle Valo */ 413e705c121SKalle Valo struct iwl_trans_config { 414e705c121SKalle Valo struct iwl_op_mode *op_mode; 415e705c121SKalle Valo 416e705c121SKalle Valo u8 cmd_queue; 417e705c121SKalle Valo u8 cmd_fifo; 418e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 419e705c121SKalle Valo const u8 *no_reclaim_cmds; 420e705c121SKalle Valo unsigned int n_no_reclaim_cmds; 421e705c121SKalle Valo 4226c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 423e705c121SKalle Valo bool bc_table_dword; 424e705c121SKalle Valo bool scd_set_active; 42539bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 42639bdb17eSSharon Dvir int command_groups_size; 427e705c121SKalle Valo 42821cb3222SJohannes Berg u8 cb_data_offs; 429906d4eb8SJohannes Berg bool fw_reset_handshake; 430227f2597SJohannes Berg u8 queue_alloc_cmd_ver; 431e705c121SKalle Valo }; 432e705c121SKalle Valo 433e705c121SKalle Valo struct iwl_trans_dump_data { 434e705c121SKalle Valo u32 len; 435e705c121SKalle Valo u8 data[]; 436e705c121SKalle Valo }; 437e705c121SKalle Valo 438e705c121SKalle Valo struct iwl_trans; 439e705c121SKalle Valo 440e705c121SKalle Valo struct iwl_trans_txq_scd_cfg { 441e705c121SKalle Valo u8 fifo; 4422a2e9d10SLiad Kaufman u8 sta_id; 443e705c121SKalle Valo u8 tid; 444e705c121SKalle Valo bool aggregate; 445e705c121SKalle Valo int frame_limit; 446e705c121SKalle Valo }; 447e705c121SKalle Valo 4486b35ff91SSara Sharon /** 44992536c96SSara Sharon * struct iwl_trans_rxq_dma_data - RX queue DMA data 45092536c96SSara Sharon * @fr_bd_cb: DMA address of free BD cyclic buffer 45192536c96SSara Sharon * @fr_bd_wid: Initial write index of the free BD cyclic buffer 45292536c96SSara Sharon * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 45392536c96SSara Sharon * @ur_bd_cb: DMA address of used BD cyclic buffer 45492536c96SSara Sharon */ 45592536c96SSara Sharon struct iwl_trans_rxq_dma_data { 45692536c96SSara Sharon u64 fr_bd_cb; 45792536c96SSara Sharon u32 fr_bd_wid; 45892536c96SSara Sharon u64 urbd_stts_wrptr; 45992536c96SSara Sharon u64 ur_bd_cb; 46092536c96SSara Sharon }; 46192536c96SSara Sharon 4625f408503SAlon Giladi /* maximal number of DRAM MAP entries supported by FW */ 4635f408503SAlon Giladi #define IPC_DRAM_MAP_ENTRY_NUM_MAX 64 4645f408503SAlon Giladi 4655f408503SAlon Giladi /** 4665f408503SAlon Giladi * struct iwl_pnvm_image - contains info about the parsed pnvm image 4675f408503SAlon Giladi * @chunks: array of pointers to pnvm payloads and their sizes 4685f408503SAlon Giladi * @n_chunks: the number of the pnvm payloads. 469b99e32cbSAlon Giladi * @version: the version of the loaded PNVM image 4705f408503SAlon Giladi */ 4715f408503SAlon Giladi struct iwl_pnvm_image { 4725f408503SAlon Giladi struct { 4735f408503SAlon Giladi const void *data; 4745f408503SAlon Giladi u32 len; 4755f408503SAlon Giladi } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 4765f408503SAlon Giladi u32 n_chunks; 477b99e32cbSAlon Giladi u32 version; 4785f408503SAlon Giladi }; 4795f408503SAlon Giladi 48092536c96SSara Sharon /** 481e705c121SKalle Valo * struct iwl_trans_ops - transport specific operations 482e705c121SKalle Valo * 483e705c121SKalle Valo * All the handlers MUST be implemented 484e705c121SKalle Valo * 485bab3cb92SEmmanuel Grumbach * @start_hw: starts the HW. From that point on, the HW can send interrupts. 486bab3cb92SEmmanuel Grumbach * May sleep. 487e705c121SKalle Valo * @op_mode_leave: Turn off the HW RF kill indication if on 488e705c121SKalle Valo * May sleep 489e705c121SKalle Valo * @start_fw: allocates and inits all the resources for the transport 490e705c121SKalle Valo * layer. Also kick a fw image. 491e705c121SKalle Valo * May sleep 492e705c121SKalle Valo * @fw_alive: called when the fw sends alive notification. If the fw provides 493e705c121SKalle Valo * the SCD base address in SRAM, then provide it here, or 0 otherwise. 494e705c121SKalle Valo * May sleep 495e705c121SKalle Valo * @stop_device: stops the whole device (embedded CPU put to reset) and stops 496bab3cb92SEmmanuel Grumbach * the HW. From that point on, the HW will be stopped but will still issue 497bab3cb92SEmmanuel Grumbach * an interrupt if the HW RF kill switch is triggered. 498e705c121SKalle Valo * This callback must do the right thing and not crash even if %start_hw() 499e705c121SKalle Valo * was called but not &start_fw(). May sleep. 500e705c121SKalle Valo * @d3_suspend: put the device into the correct mode for WoWLAN during 501e705c121SKalle Valo * suspend. This is optional, if not implemented WoWLAN will not be 502e705c121SKalle Valo * supported. This callback may sleep. 503e705c121SKalle Valo * @d3_resume: resume the device after WoWLAN, enabling the opmode to 504e705c121SKalle Valo * talk to the WoWLAN image to get its status. This is optional, if not 505e705c121SKalle Valo * implemented WoWLAN will not be supported. This callback may sleep. 506e705c121SKalle Valo * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 507e705c121SKalle Valo * If RFkill is asserted in the middle of a SYNC host command, it must 508e705c121SKalle Valo * return -ERFKILL straight away. 509e705c121SKalle Valo * May sleep only if CMD_ASYNC is not set 5103f73b8caSEmmanuel Grumbach * @tx: send an skb. The transport relies on the op_mode to zero the 5116eb5e529SEmmanuel Grumbach * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 5126eb5e529SEmmanuel Grumbach * the CSUM will be taken care of (TCP CSUM and IP header in case of 5136eb5e529SEmmanuel Grumbach * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 5146eb5e529SEmmanuel Grumbach * header if it is IPv4. 515e705c121SKalle Valo * Must be atomic 516e705c121SKalle Valo * @reclaim: free packet until ssn. Returns a list of freed packets. 517e705c121SKalle Valo * Must be atomic 518e705c121SKalle Valo * @txq_enable: setup a queue. To setup an AC queue, use the 519e705c121SKalle Valo * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 520e705c121SKalle Valo * this one. The op_mode must not configure the HCMD queue. The scheduler 521e705c121SKalle Valo * configuration may be %NULL, in which case the hardware will not be 522dcfbd67bSEmmanuel Grumbach * configured. If true is returned, the operation mode needs to increment 523dcfbd67bSEmmanuel Grumbach * the sequence number of the packets routed to this queue because of a 524dcfbd67bSEmmanuel Grumbach * hardware scheduler bug. May sleep. 525e705c121SKalle Valo * @txq_disable: de-configure a Tx queue to send AMPDUs 526e705c121SKalle Valo * Must be atomic 52742db09c1SLiad Kaufman * @txq_set_shared_mode: change Tx queue shared/unshared marking 528d6d517b7SSara Sharon * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 529d6d517b7SSara Sharon * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 530e705c121SKalle Valo * @freeze_txq_timer: prevents the timer of the queue from firing until the 531e705c121SKalle Valo * queue is set to awake. Must be atomic. 5320cd58eaaSEmmanuel Grumbach * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 5330cd58eaaSEmmanuel Grumbach * that the transport needs to refcount the calls since this function 5340cd58eaaSEmmanuel Grumbach * will be called several times with block = true, and then the queues 5350cd58eaaSEmmanuel Grumbach * need to be unblocked only after the same number of calls with 5360cd58eaaSEmmanuel Grumbach * block = false. 537e705c121SKalle Valo * @write8: write a u8 to a register at offset ofs from the BAR 538e705c121SKalle Valo * @write32: write a u32 to a register at offset ofs from the BAR 539e705c121SKalle Valo * @read32: read a u32 register at offset ofs from the BAR 540e705c121SKalle Valo * @read_prph: read a DWORD from a periphery register 541e705c121SKalle Valo * @write_prph: write a DWORD to a periphery register 542e705c121SKalle Valo * @read_mem: read device's SRAM in DWORD 543e705c121SKalle Valo * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 544e705c121SKalle Valo * will be zeroed. 545f696a7eeSLuca Coelho * @read_config32: read a u32 value from the device's config space at 546f696a7eeSLuca Coelho * the given offset. 547e705c121SKalle Valo * @configure: configure parameters required by the transport layer from 548e705c121SKalle Valo * the op_mode. May be called several times before start_fw, can't be 549e705c121SKalle Valo * called after that. 550e705c121SKalle Valo * @set_pmi: set the power pmi state 551e705c121SKalle Valo * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 552e705c121SKalle Valo * Sleeping is not allowed between grab_nic_access and 553e705c121SKalle Valo * release_nic_access. 554e705c121SKalle Valo * @release_nic_access: let the NIC go to sleep. The "flags" parameter 555e705c121SKalle Valo * must be the same one that was sent before to the grab_nic_access. 556e705c121SKalle Valo * @set_bits_mask - set SRAM register according to value and mask. 557e705c121SKalle Valo * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 558e705c121SKalle Valo * TX'ed commands and similar. The buffer will be vfree'd by the caller. 559e705c121SKalle Valo * Note that the transport must fill in the proper file headers. 560f7805b33SLior Cohen * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 561f7805b33SLior Cohen * of the trans debugfs 562194d1f84SAlon Giladi * @load_pnvm: save the pnvm data in DRAM 563a182dfabSLuca Coelho * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the 564a182dfabSLuca Coelho * context info. 565c738fb61SAlon Giladi * @load_reduce_power: copy reduce power table to the corresponding DRAM memory 566c738fb61SAlon Giladi * @set_reduce_power: set reduce power table addresses in the sratch buffer 5673161a34dSMordechay Goodstein * @interrupts: disable/enable interrupts to transport 568e705c121SKalle Valo */ 569e705c121SKalle Valo struct iwl_trans_ops { 570e705c121SKalle Valo 571bab3cb92SEmmanuel Grumbach int (*start_hw)(struct iwl_trans *iwl_trans); 572e705c121SKalle Valo void (*op_mode_leave)(struct iwl_trans *iwl_trans); 573e705c121SKalle Valo int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 574e705c121SKalle Valo bool run_in_rfkill); 575e705c121SKalle Valo void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 576bab3cb92SEmmanuel Grumbach void (*stop_device)(struct iwl_trans *trans); 577e705c121SKalle Valo 578e5f3f215SHaim Dreyfuss int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 579e705c121SKalle Valo int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 58023ae6128SMatti Gottlieb bool test, bool reset); 581e705c121SKalle Valo 582e705c121SKalle Valo int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 583e705c121SKalle Valo 584e705c121SKalle Valo int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 585a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue); 586e705c121SKalle Valo void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 587e705c121SKalle Valo struct sk_buff_head *skbs); 588e705c121SKalle Valo 589ba7136f3SAlex Malamud void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 590ba7136f3SAlex Malamud 591dcfbd67bSEmmanuel Grumbach bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 592e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 593e705c121SKalle Valo unsigned int queue_wdg_timeout); 594e705c121SKalle Valo void (*txq_disable)(struct iwl_trans *trans, int queue, 595e705c121SKalle Valo bool configure_scd); 5962f7a3863SLuca Coelho /* 22000 functions */ 597227f2597SJohannes Berg int (*txq_alloc)(struct iwl_trans *trans, u32 flags, 598227f2597SJohannes Berg u32 sta_mask, u8 tid, 59985b17a33SJohannes Berg int size, unsigned int queue_wdg_timeout); 6006b35ff91SSara Sharon void (*txq_free)(struct iwl_trans *trans, int queue); 60192536c96SSara Sharon int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 60292536c96SSara Sharon struct iwl_trans_rxq_dma_data *data); 603e705c121SKalle Valo 60442db09c1SLiad Kaufman void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 60542db09c1SLiad Kaufman bool shared); 60642db09c1SLiad Kaufman 607a1a57877SSara Sharon int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 608d6d517b7SSara Sharon int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 609e705c121SKalle Valo void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 610e705c121SKalle Valo bool freeze); 6110cd58eaaSEmmanuel Grumbach void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 612e705c121SKalle Valo 613e705c121SKalle Valo void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 614e705c121SKalle Valo void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 615e705c121SKalle Valo u32 (*read32)(struct iwl_trans *trans, u32 ofs); 616e705c121SKalle Valo u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 617e705c121SKalle Valo void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 618e705c121SKalle Valo int (*read_mem)(struct iwl_trans *trans, u32 addr, 619e705c121SKalle Valo void *buf, int dwords); 620e705c121SKalle Valo int (*write_mem)(struct iwl_trans *trans, u32 addr, 621e705c121SKalle Valo const void *buf, int dwords); 622f696a7eeSLuca Coelho int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 623e705c121SKalle Valo void (*configure)(struct iwl_trans *trans, 624e705c121SKalle Valo const struct iwl_trans_config *trans_cfg); 625e705c121SKalle Valo void (*set_pmi)(struct iwl_trans *trans, bool state); 62615bf5ac6SJohannes Berg int (*sw_reset)(struct iwl_trans *trans, bool retake_ownership); 6271ed08f6fSJohannes Berg bool (*grab_nic_access)(struct iwl_trans *trans); 6281ed08f6fSJohannes Berg void (*release_nic_access)(struct iwl_trans *trans); 629e705c121SKalle Valo void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 630e705c121SKalle Valo u32 value); 631e705c121SKalle Valo 632e705c121SKalle Valo struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 633fdb70083SJohannes Berg u32 dump_mask, 634fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 635fdb70083SJohannes Berg void *sanitize_ctx); 636f7805b33SLior Cohen void (*debugfs_cleanup)(struct iwl_trans *trans); 637d1967ce6SShahar S Matityahu void (*sync_nmi)(struct iwl_trans *trans); 638194d1f84SAlon Giladi int (*load_pnvm)(struct iwl_trans *trans, 63933182810SAlon Giladi const struct iwl_pnvm_image *pnvm_payloads, 64033182810SAlon Giladi const struct iwl_ucode_capabilities *capa); 64133182810SAlon Giladi void (*set_pnvm)(struct iwl_trans *trans, 64233182810SAlon Giladi const struct iwl_ucode_capabilities *capa); 643c738fb61SAlon Giladi int (*load_reduce_power)(struct iwl_trans *trans, 6447c9c8477SAlon Giladi const struct iwl_pnvm_image *payloads, 6457c9c8477SAlon Giladi const struct iwl_ucode_capabilities *capa); 6467c9c8477SAlon Giladi void (*set_reduce_power)(struct iwl_trans *trans, 6477c9c8477SAlon Giladi const struct iwl_ucode_capabilities *capa); 648c738fb61SAlon Giladi 6493161a34dSMordechay Goodstein void (*interrupts)(struct iwl_trans *trans, bool enable); 650c0941aceSMukesh Sisodiya int (*imr_dma_data)(struct iwl_trans *trans, 651c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, 652c0941aceSMukesh Sisodiya u32 byte_cnt); 653c0941aceSMukesh Sisodiya 654e705c121SKalle Valo }; 655e705c121SKalle Valo 656e705c121SKalle Valo /** 657e705c121SKalle Valo * enum iwl_trans_state - state of the transport layer 658e705c121SKalle Valo * 659b2ed841eSJohannes Berg * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 660b2ed841eSJohannes Berg * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 661b2ed841eSJohannes Berg * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 662e705c121SKalle Valo */ 663e705c121SKalle Valo enum iwl_trans_state { 664b2ed841eSJohannes Berg IWL_TRANS_NO_FW, 665b2ed841eSJohannes Berg IWL_TRANS_FW_STARTED, 666b2ed841eSJohannes Berg IWL_TRANS_FW_ALIVE, 667e705c121SKalle Valo }; 668e705c121SKalle Valo 669e705c121SKalle Valo /** 670b7282643SLuca Coelho * DOC: Platform power management 671e705c121SKalle Valo * 672b7282643SLuca Coelho * In system-wide power management the entire platform goes into a low 673b7282643SLuca Coelho * power state (e.g. idle or suspend to RAM) at the same time and the 674b7282643SLuca Coelho * device is configured as a wakeup source for the entire platform. 675b7282643SLuca Coelho * This is usually triggered by userspace activity (e.g. the user 676b7282643SLuca Coelho * presses the suspend button or a power management daemon decides to 677b7282643SLuca Coelho * put the platform in low power mode). The device's behavior in this 678b7282643SLuca Coelho * mode is dictated by the wake-on-WLAN configuration. 679b7282643SLuca Coelho * 680b7282643SLuca Coelho * The terms used for the device's behavior are as follows: 681b7282643SLuca Coelho * 682b7282643SLuca Coelho * - D0: the device is fully powered and the host is awake; 683b7282643SLuca Coelho * - D3: the device is in low power mode and only reacts to 684b7282643SLuca Coelho * specific events (e.g. magic-packet received or scan 685b7282643SLuca Coelho * results found); 686b7282643SLuca Coelho * 687b7282643SLuca Coelho * These terms reflect the power modes in the firmware and are not to 688f60e2750SEmmanuel Grumbach * be confused with the physical device power state. 689e705c121SKalle Valo */ 690b7282643SLuca Coelho 691b7282643SLuca Coelho /** 692b7282643SLuca Coelho * enum iwl_plat_pm_mode - platform power management mode 693b7282643SLuca Coelho * 694b7282643SLuca Coelho * This enumeration describes the device's platform power management 695f60e2750SEmmanuel Grumbach * behavior when in system-wide suspend (i.e WoWLAN). 696b7282643SLuca Coelho * 697b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 698f60e2750SEmmanuel Grumbach * device. In system-wide suspend mode, it means that the all 699f60e2750SEmmanuel Grumbach * connections will be closed automatically by mac80211 before 700f60e2750SEmmanuel Grumbach * the platform is suspended. 701b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 702b7282643SLuca Coelho */ 703b7282643SLuca Coelho enum iwl_plat_pm_mode { 704b7282643SLuca Coelho IWL_PLAT_PM_MODE_DISABLED, 705b7282643SLuca Coelho IWL_PLAT_PM_MODE_D3, 706e705c121SKalle Valo }; 707e705c121SKalle Valo 708341bd290SShahar S Matityahu /** 709341bd290SShahar S Matityahu * enum iwl_ini_cfg_state 710341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 711341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 712341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 713341bd290SShahar S Matityahu * are corrupted. The rest of the debug TLVs will still be used 714341bd290SShahar S Matityahu */ 715341bd290SShahar S Matityahu enum iwl_ini_cfg_state { 716341bd290SShahar S Matityahu IWL_INI_CFG_STATE_NOT_LOADED, 717341bd290SShahar S Matityahu IWL_INI_CFG_STATE_LOADED, 718341bd290SShahar S Matityahu IWL_INI_CFG_STATE_CORRUPTED, 719341bd290SShahar S Matityahu }; 720341bd290SShahar S Matityahu 721b8a7547dSShahar S Matityahu /* Max time to wait for nmi interrupt */ 722b8a7547dSShahar S Matityahu #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 723b8a7547dSShahar S Matityahu 72488964b2eSSara Sharon /** 72588964b2eSSara Sharon * struct iwl_dram_data 72688964b2eSSara Sharon * @physical: page phy pointer 72788964b2eSSara Sharon * @block: pointer to the allocated block/page 72888964b2eSSara Sharon * @size: size of the block/page 72988964b2eSSara Sharon */ 73088964b2eSSara Sharon struct iwl_dram_data { 73188964b2eSSara Sharon dma_addr_t physical; 73288964b2eSSara Sharon void *block; 73388964b2eSSara Sharon int size; 73488964b2eSSara Sharon }; 7354cbb8e50SLuciano Coelho 736e705c121SKalle Valo /** 7377c9c8477SAlon Giladi * @drams: array of several DRAM areas that contains the pnvm and power 7387c9c8477SAlon Giladi * reduction table payloads. 7397c9c8477SAlon Giladi * @n_regions: number of DRAM regions that were allocated 7407c9c8477SAlon Giladi * @prph_scratch_mem_desc: points to a structure allocated in dram, 7417c9c8477SAlon Giladi * designed to show FW where all the payloads are. 7427c9c8477SAlon Giladi */ 7437c9c8477SAlon Giladi struct iwl_dram_regions { 7447c9c8477SAlon Giladi struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 7457c9c8477SAlon Giladi struct iwl_dram_data prph_scratch_mem_desc; 7467c9c8477SAlon Giladi u8 n_regions; 7477c9c8477SAlon Giladi }; 7487c9c8477SAlon Giladi 7497c9c8477SAlon Giladi /** 750593fae3eSShahar S Matityahu * struct iwl_fw_mon - fw monitor per allocation id 751593fae3eSShahar S Matityahu * @num_frags: number of fragments 752593fae3eSShahar S Matityahu * @frags: an array of DRAM buffer fragments 753593fae3eSShahar S Matityahu */ 754593fae3eSShahar S Matityahu struct iwl_fw_mon { 755593fae3eSShahar S Matityahu u32 num_frags; 756593fae3eSShahar S Matityahu struct iwl_dram_data *frags; 757593fae3eSShahar S Matityahu }; 758593fae3eSShahar S Matityahu 759593fae3eSShahar S Matityahu /** 760505a00c0SShahar S Matityahu * struct iwl_self_init_dram - dram data used by self init process 761505a00c0SShahar S Matityahu * @fw: lmac and umac dram data 762505a00c0SShahar S Matityahu * @fw_cnt: total number of items in array 763505a00c0SShahar S Matityahu * @paging: paging dram data 764505a00c0SShahar S Matityahu * @paging_cnt: total number of items in array 765505a00c0SShahar S Matityahu */ 766505a00c0SShahar S Matityahu struct iwl_self_init_dram { 767505a00c0SShahar S Matityahu struct iwl_dram_data *fw; 768505a00c0SShahar S Matityahu int fw_cnt; 769505a00c0SShahar S Matityahu struct iwl_dram_data *paging; 770505a00c0SShahar S Matityahu int paging_cnt; 771505a00c0SShahar S Matityahu }; 772505a00c0SShahar S Matityahu 773505a00c0SShahar S Matityahu /** 774c0941aceSMukesh Sisodiya * struct iwl_imr_data - imr dram data used during debug process 775c0941aceSMukesh Sisodiya * @imr_enable: imr enable status received from fw 776c0941aceSMukesh Sisodiya * @imr_size: imr dram size received from fw 777c0941aceSMukesh Sisodiya * @sram_addr: sram address from debug tlv 778c0941aceSMukesh Sisodiya * @sram_size: sram size from debug tlv 779c0941aceSMukesh Sisodiya * @imr2sram_remainbyte`: size remained after each dma transfer 780c0941aceSMukesh Sisodiya * @imr_curr_addr: current dst address used during dma transfer 781c0941aceSMukesh Sisodiya * @imr_base_addr: imr address received from fw 782c0941aceSMukesh Sisodiya */ 783c0941aceSMukesh Sisodiya struct iwl_imr_data { 784c0941aceSMukesh Sisodiya u32 imr_enable; 785c0941aceSMukesh Sisodiya u32 imr_size; 786c0941aceSMukesh Sisodiya u32 sram_addr; 787c0941aceSMukesh Sisodiya u32 sram_size; 788c0941aceSMukesh Sisodiya u32 imr2sram_remainbyte; 789c0941aceSMukesh Sisodiya u64 imr_curr_addr; 790c0941aceSMukesh Sisodiya __le64 imr_base_addr; 791c0941aceSMukesh Sisodiya }; 792c0941aceSMukesh Sisodiya 7935e31b3dfSMukesh Sisodiya #define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32 7945e31b3dfSMukesh Sisodiya 7955e31b3dfSMukesh Sisodiya /** 7965e31b3dfSMukesh Sisodiya * struct iwl_pc_data - program counter details 7975e31b3dfSMukesh Sisodiya * @pc_name: cpu name 7985e31b3dfSMukesh Sisodiya * @pc_address: cpu program counter 7995e31b3dfSMukesh Sisodiya */ 8005e31b3dfSMukesh Sisodiya struct iwl_pc_data { 8015e31b3dfSMukesh Sisodiya u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES]; 8025e31b3dfSMukesh Sisodiya u32 pc_address; 8035e31b3dfSMukesh Sisodiya }; 8045e31b3dfSMukesh Sisodiya 805c0941aceSMukesh Sisodiya /** 80691c28b83SShahar S Matityahu * struct iwl_trans_debug - transport debug related data 80791c28b83SShahar S Matityahu * 80891c28b83SShahar S Matityahu * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 80991c28b83SShahar S Matityahu * @rec_on: true iff there is a fw debug recording currently active 81091c28b83SShahar S Matityahu * @dest_tlv: points to the destination TLV for debug 81191c28b83SShahar S Matityahu * @conf_tlv: array of pointers to configuration TLVs for debug 81291c28b83SShahar S Matityahu * @trigger_tlv: array of pointers to triggers TLVs for debug 81391c28b83SShahar S Matityahu * @lmac_error_event_table: addrs of lmacs error tables 81491c28b83SShahar S Matityahu * @umac_error_event_table: addr of umac error table 81557417e1bSJohannes Berg * @tcm_error_event_table: address(es) of TCM error table(s) 8164cd177b4SJohannes Berg * @rcm_error_event_table: address(es) of RCM error table(s) 81791c28b83SShahar S Matityahu * @error_event_table_tlv_status: bitmap that indicates what error table 81891c28b83SShahar S Matityahu * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 819341bd290SShahar S Matityahu * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 820341bd290SShahar S Matityahu * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 821593fae3eSShahar S Matityahu * @fw_mon_cfg: debug buffer allocation configuration 822593fae3eSShahar S Matityahu * @fw_mon_ini: DRAM buffer fragments per allocation id 82369f0e505SShahar S Matityahu * @fw_mon: DRAM buffer for firmware monitor 82491c28b83SShahar S Matityahu * @hw_error: equals true if hw error interrupt was received from the FW 825029c25f3SShahar S Matityahu * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 8263b589d56SShahar S Matityahu * @active_regions: active regions 827677d25b2SShahar S Matityahu * @debug_info_tlv_list: list of debug info TLVs 828a9248de4SShahar S Matityahu * @time_point: array of debug time points 82960e8abd9SShahar S Matityahu * @periodic_trig_list: periodic triggers list 830f21baf24SMukesh Sisodiya * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON 831f21baf24SMukesh Sisodiya * @ucode_preset: preset based on ucode 83251fa8c02SMukesh Sisodiya * @dump_file_name_ext: dump file name extension 83351fa8c02SMukesh Sisodiya * @dump_file_name_ext_valid: dump file name extension if valid or not 8345e31b3dfSMukesh Sisodiya * @num_pc: number of program counter for cpu 8355e31b3dfSMukesh Sisodiya * @pc_data: details of the program counter 83691c28b83SShahar S Matityahu */ 83791c28b83SShahar S Matityahu struct iwl_trans_debug { 83891c28b83SShahar S Matityahu u8 n_dest_reg; 83991c28b83SShahar S Matityahu bool rec_on; 84091c28b83SShahar S Matityahu 84191c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 84291c28b83SShahar S Matityahu const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 84391c28b83SShahar S Matityahu struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 84491c28b83SShahar S Matityahu 84591c28b83SShahar S Matityahu u32 lmac_error_event_table[2]; 84691c28b83SShahar S Matityahu u32 umac_error_event_table; 84757417e1bSJohannes Berg u32 tcm_error_event_table[2]; 8484cd177b4SJohannes Berg u32 rcm_error_event_table[2]; 84991c28b83SShahar S Matityahu unsigned int error_event_table_tlv_status; 85091c28b83SShahar S Matityahu 851341bd290SShahar S Matityahu enum iwl_ini_cfg_state internal_ini_cfg; 852341bd290SShahar S Matityahu enum iwl_ini_cfg_state external_ini_cfg; 85391c28b83SShahar S Matityahu 854593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 855593fae3eSShahar S Matityahu struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 856593fae3eSShahar S Matityahu 85769f0e505SShahar S Matityahu struct iwl_dram_data fw_mon; 85891c28b83SShahar S Matityahu 85991c28b83SShahar S Matityahu bool hw_error; 860029c25f3SShahar S Matityahu enum iwl_fw_ini_buffer_location ini_dest; 8613b589d56SShahar S Matityahu 862beb44c0cSMordechay Goodstein u64 unsupported_region_msk; 8633b589d56SShahar S Matityahu struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 864677d25b2SShahar S Matityahu struct list_head debug_info_tlv_list; 865a9248de4SShahar S Matityahu struct iwl_dbg_tlv_time_point_data 866a9248de4SShahar S Matityahu time_point[IWL_FW_INI_TIME_POINT_NUM]; 86760e8abd9SShahar S Matityahu struct list_head periodic_trig_list; 868cf29c5b6SShahar S Matityahu 869cf29c5b6SShahar S Matityahu u32 domains_bitmap; 870f21baf24SMukesh Sisodiya u32 ucode_preset; 871ddb6b76bSMukesh Sisodiya bool restart_required; 872ddb6b76bSMukesh Sisodiya u32 last_tp_resetfw; 873c0941aceSMukesh Sisodiya struct iwl_imr_data imr_data; 87451fa8c02SMukesh Sisodiya u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME]; 87551fa8c02SMukesh Sisodiya bool dump_file_name_ext_valid; 8765e31b3dfSMukesh Sisodiya u32 num_pc; 8775e31b3dfSMukesh Sisodiya struct iwl_pc_data *pc_data; 87891c28b83SShahar S Matityahu }; 87991c28b83SShahar S Matityahu 8804807e736SMordechay Goodstein struct iwl_dma_ptr { 8814807e736SMordechay Goodstein dma_addr_t dma; 8824807e736SMordechay Goodstein void *addr; 8834807e736SMordechay Goodstein size_t size; 8844807e736SMordechay Goodstein }; 8854807e736SMordechay Goodstein 8864807e736SMordechay Goodstein struct iwl_cmd_meta { 8874807e736SMordechay Goodstein /* only for SYNC commands, iff the reply skb is wanted */ 8884807e736SMordechay Goodstein struct iwl_host_cmd *source; 8894807e736SMordechay Goodstein u32 flags; 8904807e736SMordechay Goodstein u32 tbs; 8914807e736SMordechay Goodstein }; 8924807e736SMordechay Goodstein 8934807e736SMordechay Goodstein /* 8944807e736SMordechay Goodstein * The FH will write back to the first TB only, so we need to copy some data 8954807e736SMordechay Goodstein * into the buffer regardless of whether it should be mapped or not. 8964807e736SMordechay Goodstein * This indicates how big the first TB must be to include the scratch buffer 8974807e736SMordechay Goodstein * and the assigned PN. 8984807e736SMordechay Goodstein * Since PN location is 8 bytes at offset 12, it's 20 now. 8994807e736SMordechay Goodstein * If we make it bigger then allocations will be bigger and copy slower, so 9004807e736SMordechay Goodstein * that's probably not useful. 9014807e736SMordechay Goodstein */ 9024807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE 20 9034807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 9044807e736SMordechay Goodstein 9054807e736SMordechay Goodstein struct iwl_pcie_txq_entry { 9064807e736SMordechay Goodstein void *cmd; 9074807e736SMordechay Goodstein struct sk_buff *skb; 9084807e736SMordechay Goodstein /* buffer to free after command completes */ 9094807e736SMordechay Goodstein const void *free_buf; 9104807e736SMordechay Goodstein struct iwl_cmd_meta meta; 9114807e736SMordechay Goodstein }; 9124807e736SMordechay Goodstein 9134807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf { 9144807e736SMordechay Goodstein u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 9154807e736SMordechay Goodstein }; 9164807e736SMordechay Goodstein 9174807e736SMordechay Goodstein /** 9184807e736SMordechay Goodstein * struct iwl_txq - Tx Queue for DMA 9194807e736SMordechay Goodstein * @q: generic Rx/Tx queue descriptor 9204807e736SMordechay Goodstein * @tfds: transmit frame descriptors (DMA memory) 9214807e736SMordechay Goodstein * @first_tb_bufs: start of command headers, including scratch buffers, for 9224807e736SMordechay Goodstein * the writeback -- this is DMA memory and an array holding one buffer 9234807e736SMordechay Goodstein * for each command on the queue 9244807e736SMordechay Goodstein * @first_tb_dma: DMA address for the first_tb_bufs start 9254807e736SMordechay Goodstein * @entries: transmit entries (driver state) 9264807e736SMordechay Goodstein * @lock: queue lock 9274807e736SMordechay Goodstein * @stuck_timer: timer that fires if queue gets stuck 9284807e736SMordechay Goodstein * @trans: pointer back to transport (for timer) 9294807e736SMordechay Goodstein * @need_update: indicates need to update read/write index 9304807e736SMordechay Goodstein * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 9314807e736SMordechay Goodstein * @wd_timeout: queue watchdog timeout (jiffies) - per queue 9324807e736SMordechay Goodstein * @frozen: tx stuck queue timer is frozen 9334807e736SMordechay Goodstein * @frozen_expiry_remainder: remember how long until the timer fires 9344807e736SMordechay Goodstein * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 9354807e736SMordechay Goodstein * @write_ptr: 1-st empty entry (index) host_w 9364807e736SMordechay Goodstein * @read_ptr: last used entry (index) host_r 9374807e736SMordechay Goodstein * @dma_addr: physical addr for BD's 9384807e736SMordechay Goodstein * @n_window: safe queue window 9394807e736SMordechay Goodstein * @id: queue id 9404807e736SMordechay Goodstein * @low_mark: low watermark, resume queue if free space more than this 9414807e736SMordechay Goodstein * @high_mark: high watermark, stop queue if free space less than this 9424807e736SMordechay Goodstein * 9434807e736SMordechay Goodstein * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 9444807e736SMordechay Goodstein * descriptors) and required locking structures. 9454807e736SMordechay Goodstein * 9464807e736SMordechay Goodstein * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 9474807e736SMordechay Goodstein * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 9484807e736SMordechay Goodstein * there might be HW changes in the future). For the normal TX 9494807e736SMordechay Goodstein * queues, n_window, which is the size of the software queue data 9504807e736SMordechay Goodstein * is also 256; however, for the command queue, n_window is only 9514807e736SMordechay Goodstein * 32 since we don't need so many commands pending. Since the HW 9524807e736SMordechay Goodstein * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 9534807e736SMordechay Goodstein * This means that we end up with the following: 9544807e736SMordechay Goodstein * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 9554807e736SMordechay Goodstein * SW entries: | 0 | ... | 31 | 9564807e736SMordechay Goodstein * where N is a number between 0 and 7. This means that the SW 9574807e736SMordechay Goodstein * data is a window overlayed over the HW queue. 9584807e736SMordechay Goodstein */ 9594807e736SMordechay Goodstein struct iwl_txq { 9604807e736SMordechay Goodstein void *tfds; 9614807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf *first_tb_bufs; 9624807e736SMordechay Goodstein dma_addr_t first_tb_dma; 9634807e736SMordechay Goodstein struct iwl_pcie_txq_entry *entries; 9644807e736SMordechay Goodstein /* lock for syncing changes on the queue */ 9654807e736SMordechay Goodstein spinlock_t lock; 9664807e736SMordechay Goodstein unsigned long frozen_expiry_remainder; 9674807e736SMordechay Goodstein struct timer_list stuck_timer; 9684807e736SMordechay Goodstein struct iwl_trans *trans; 9694807e736SMordechay Goodstein bool need_update; 9704807e736SMordechay Goodstein bool frozen; 9714807e736SMordechay Goodstein bool ampdu; 9724807e736SMordechay Goodstein int block; 9734807e736SMordechay Goodstein unsigned long wd_timeout; 9744807e736SMordechay Goodstein struct sk_buff_head overflow_q; 9754807e736SMordechay Goodstein struct iwl_dma_ptr bc_tbl; 9764807e736SMordechay Goodstein 9774807e736SMordechay Goodstein int write_ptr; 9784807e736SMordechay Goodstein int read_ptr; 9794807e736SMordechay Goodstein dma_addr_t dma_addr; 9804807e736SMordechay Goodstein int n_window; 9814807e736SMordechay Goodstein u32 id; 9824807e736SMordechay Goodstein int low_mark; 9834807e736SMordechay Goodstein int high_mark; 9844807e736SMordechay Goodstein 9854807e736SMordechay Goodstein bool overflow_tx; 9864807e736SMordechay Goodstein }; 9874f4822b7SMordechay Goodstein 9884f4822b7SMordechay Goodstein /** 9894f4822b7SMordechay Goodstein * struct iwl_trans_txqs - transport tx queues data 9904f4822b7SMordechay Goodstein * 9918e3b79f8SMordechay Goodstein * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 99222852fadSMordechay Goodstein * @page_offs: offset from skb->cb to mac header page pointer 99322852fadSMordechay Goodstein * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 9944f4822b7SMordechay Goodstein * @queue_used - bit mask of used queues 9954f4822b7SMordechay Goodstein * @queue_stopped - bit mask of stopped queues 9960179bfffSMordechay Goodstein * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 997227f2597SJohannes Berg * @queue_alloc_cmd_ver: queue allocation command version 9984f4822b7SMordechay Goodstein */ 9994f4822b7SMordechay Goodstein struct iwl_trans_txqs { 10004f4822b7SMordechay Goodstein unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 10014f4822b7SMordechay Goodstein unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 10024f4822b7SMordechay Goodstein struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 1003a26014e2SMordechay Goodstein struct dma_pool *bc_pool; 1004a26014e2SMordechay Goodstein size_t bc_tbl_size; 10058e3b79f8SMordechay Goodstein bool bc_table_dword; 100622852fadSMordechay Goodstein u8 page_offs; 100722852fadSMordechay Goodstein u8 dev_cmd_offs; 10084246465eSJohannes Berg struct iwl_tso_hdr_page __percpu *tso_hdr_page; 10098e3b79f8SMordechay Goodstein 10104f4822b7SMordechay Goodstein struct { 10114f4822b7SMordechay Goodstein u8 fifo; 10124f4822b7SMordechay Goodstein u8 q_id; 10134f4822b7SMordechay Goodstein unsigned int wdg_timeout; 10144f4822b7SMordechay Goodstein } cmd; 10154f4822b7SMordechay Goodstein 1016885375d0SMordechay Goodstein struct { 1017885375d0SMordechay Goodstein u8 max_tbs; 1018885375d0SMordechay Goodstein u16 size; 1019885375d0SMordechay Goodstein u8 addr_size; 1020885375d0SMordechay Goodstein } tfd; 10210179bfffSMordechay Goodstein 10220179bfffSMordechay Goodstein struct iwl_dma_ptr scd_bc_tbls; 1023227f2597SJohannes Berg 1024227f2597SJohannes Berg u8 queue_alloc_cmd_ver; 10254f4822b7SMordechay Goodstein }; 10264f4822b7SMordechay Goodstein 102791c28b83SShahar S Matityahu /** 1028e705c121SKalle Valo * struct iwl_trans - transport common data 1029e705c121SKalle Valo * 10306d19a5ebSEmmanuel Grumbach * @csme_own - true if we couldn't get ownership on the device 1031e705c121SKalle Valo * @ops - pointer to iwl_trans_ops 1032e705c121SKalle Valo * @op_mode - pointer to the op_mode 1033286ca8ebSLuca Coelho * @trans_cfg: the trans-specific configuration part 1034e705c121SKalle Valo * @cfg - pointer to the configuration 10356f482e37SSara Sharon * @drv - pointer to iwl_drv 1036e705c121SKalle Valo * @status: a bit-mask of transport status flags 1037e705c121SKalle Valo * @dev - pointer to struct device * that represents the device 1038e705c121SKalle Valo * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 1039e705c121SKalle Valo * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 10401afb0ae4SHaim Dreyfuss * @hw_rf_id a u32 with the device RF ID 10413a27a1a1SMukesh Sisodiya * @hw_crf_id a u32 with the device CRF ID 104272904029SMukesh Sisodiya * @hw_wfpm_id a u32 with the device wfpm ID 1043e705c121SKalle Valo * @hw_id: a u32 with the ID of the device / sub-device. 1044e705c121SKalle Valo * Set during transport allocation. 1045e705c121SKalle Valo * @hw_id_str: a string with info about HW ID. Set during transport allocation. 104655c6d8f8SMike Golant * @hw_rev_step: The mac step of the HW 1047e705c121SKalle Valo * @pm_support: set to true in start_hw if link pm is supported 1048e705c121SKalle Valo * @ltr_enabled: set to true if the LTR is enabled 1049b99e32cbSAlon Giladi * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed 1050380bf72dSAlon Giladi * @failed_to_load_reduce_power_image: set to true if pnvm loading failed 1051b7d96bcaSLuca Coelho * @wide_cmd_header: true when ucode supports wide command header format 105213f028b4SMordechay Goodstein * @wait_command_queue: wait queue for sync commands 1053e705c121SKalle Valo * @num_rx_queues: number of RX queues allocated by the transport; 1054e705c121SKalle Valo * the transport must set this before calling iwl_drv_start() 1055132db31cSGolan Ben-Ami * @iml_len: the length of the image loader 1056132db31cSGolan Ben-Ami * @iml: a pointer to the image loader itself 1057e705c121SKalle Valo * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 1058e705c121SKalle Valo * The user should use iwl_trans_{alloc,free}_tx_cmd. 1059e705c121SKalle Valo * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 1060e705c121SKalle Valo * starting the firmware, used for tracing 1061e705c121SKalle Valo * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 1062e705c121SKalle Valo * start of the 802.11 header in the @rx_mpdu_cmd 1063e705c121SKalle Valo * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 1064b7282643SLuca Coelho * @system_pm_mode: the system-wide power management mode in use. 1065b7282643SLuca Coelho * This mode is set dynamically, depending on the WoWLAN values 1066b7282643SLuca Coelho * configured from the userspace at runtime. 10674f4822b7SMordechay Goodstein * @iwl_trans_txqs: transport tx queues data. 106809b4c35dSAyala Barazani * @mbx_addr_0_step: step address data 0 106909b4c35dSAyala Barazani * @mbx_addr_1_step: step address data 1 10703a9690d0SJohannes Berg * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*), 10713a9690d0SJohannes Berg * only valid for discrete (not integrated) NICs 1072*c83031afSJohannes Berg * @invalid_tx_cmd: invalid TX command buffer 1073e705c121SKalle Valo */ 1074e705c121SKalle Valo struct iwl_trans { 10756d19a5ebSEmmanuel Grumbach bool csme_own; 1076e705c121SKalle Valo const struct iwl_trans_ops *ops; 1077e705c121SKalle Valo struct iwl_op_mode *op_mode; 1078286ca8ebSLuca Coelho const struct iwl_cfg_trans_params *trans_cfg; 1079e705c121SKalle Valo const struct iwl_cfg *cfg; 10806f482e37SSara Sharon struct iwl_drv *drv; 1081e705c121SKalle Valo enum iwl_trans_state state; 1082e705c121SKalle Valo unsigned long status; 1083e705c121SKalle Valo 1084e705c121SKalle Valo struct device *dev; 1085e705c121SKalle Valo u32 max_skb_frags; 1086e705c121SKalle Valo u32 hw_rev; 108755c6d8f8SMike Golant u32 hw_rev_step; 10881afb0ae4SHaim Dreyfuss u32 hw_rf_id; 10893a27a1a1SMukesh Sisodiya u32 hw_crf_id; 109072904029SMukesh Sisodiya u32 hw_cnv_id; 109172904029SMukesh Sisodiya u32 hw_wfpm_id; 1092e705c121SKalle Valo u32 hw_id; 1093e705c121SKalle Valo char hw_id_str[52]; 109490824f2fSLuca Coelho u32 sku_id[3]; 1095e705c121SKalle Valo 1096e705c121SKalle Valo u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 1097e705c121SKalle Valo 1098e705c121SKalle Valo bool pm_support; 1099e705c121SKalle Valo bool ltr_enabled; 110069725928SLuca Coelho u8 pnvm_loaded:1; 1101b99e32cbSAlon Giladi u8 fail_to_parse_pnvm_image:1; 11029dad325fSLuca Coelho u8 reduce_power_loaded:1; 1103380bf72dSAlon Giladi u8 failed_to_load_reduce_power_image:1; 1104e705c121SKalle Valo 110539bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 110639bdb17eSSharon Dvir int command_groups_size; 1107b7d96bcaSLuca Coelho bool wide_cmd_header; 110839bdb17eSSharon Dvir 110913f028b4SMordechay Goodstein wait_queue_head_t wait_command_queue; 1110e705c121SKalle Valo u8 num_rx_queues; 1111e705c121SKalle Valo 1112132db31cSGolan Ben-Ami size_t iml_len; 1113132db31cSGolan Ben-Ami u8 *iml; 1114132db31cSGolan Ben-Ami 1115e705c121SKalle Valo /* The following fields are internal only */ 1116e705c121SKalle Valo struct kmem_cache *dev_cmd_pool; 1117e705c121SKalle Valo char dev_cmd_pool_name[50]; 1118e705c121SKalle Valo 1119e705c121SKalle Valo struct dentry *dbgfs_dir; 1120e705c121SKalle Valo 1121e705c121SKalle Valo #ifdef CONFIG_LOCKDEP 1122e705c121SKalle Valo struct lockdep_map sync_cmd_lockdep_map; 1123e705c121SKalle Valo #endif 1124e705c121SKalle Valo 112591c28b83SShahar S Matityahu struct iwl_trans_debug dbg; 1126505a00c0SShahar S Matityahu struct iwl_self_init_dram init_dram; 1127e705c121SKalle Valo 1128b7282643SLuca Coelho enum iwl_plat_pm_mode system_pm_mode; 1129700b3799SShahar S Matityahu 11300b295a1eSLuca Coelho const char *name; 11314f4822b7SMordechay Goodstein struct iwl_trans_txqs txqs; 113209b4c35dSAyala Barazani u32 mbx_addr_0_step; 113309b4c35dSAyala Barazani u32 mbx_addr_1_step; 11340b295a1eSLuca Coelho 11353a9690d0SJohannes Berg u8 pcie_link_speed; 11363a9690d0SJohannes Berg 1137*c83031afSJohannes Berg struct iwl_dma_ptr invalid_tx_cmd; 1138*c83031afSJohannes Berg 1139e705c121SKalle Valo /* pointer to trans specific struct */ 1140e705c121SKalle Valo /*Ensure that this pointer will always be aligned to sizeof pointer */ 114145c21a0eSGustavo A. R. Silva char trans_specific[] __aligned(sizeof(void *)); 1142e705c121SKalle Valo }; 1143e705c121SKalle Valo 114439bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 114539bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 114639bdb17eSSharon Dvir 1147e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans, 1148e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1149e705c121SKalle Valo { 1150e705c121SKalle Valo trans->op_mode = trans_cfg->op_mode; 1151e705c121SKalle Valo 1152e705c121SKalle Valo trans->ops->configure(trans, trans_cfg); 115339bdb17eSSharon Dvir WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1154e705c121SKalle Valo } 1155e705c121SKalle Valo 1156bab3cb92SEmmanuel Grumbach static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1157e705c121SKalle Valo { 1158e705c121SKalle Valo might_sleep(); 1159e705c121SKalle Valo 1160bab3cb92SEmmanuel Grumbach return trans->ops->start_hw(trans); 1161e705c121SKalle Valo } 1162e705c121SKalle Valo 1163e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1164e705c121SKalle Valo { 1165e705c121SKalle Valo might_sleep(); 1166e705c121SKalle Valo 1167e705c121SKalle Valo if (trans->ops->op_mode_leave) 1168e705c121SKalle Valo trans->ops->op_mode_leave(trans); 1169e705c121SKalle Valo 1170e705c121SKalle Valo trans->op_mode = NULL; 1171e705c121SKalle Valo 1172e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1173e705c121SKalle Valo } 1174e705c121SKalle Valo 1175e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1176e705c121SKalle Valo { 1177e705c121SKalle Valo might_sleep(); 1178e705c121SKalle Valo 1179e705c121SKalle Valo trans->state = IWL_TRANS_FW_ALIVE; 1180e705c121SKalle Valo 1181e705c121SKalle Valo trans->ops->fw_alive(trans, scd_addr); 1182e705c121SKalle Valo } 1183e705c121SKalle Valo 1184e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1185e705c121SKalle Valo const struct fw_img *fw, 1186e705c121SKalle Valo bool run_in_rfkill) 1187e705c121SKalle Valo { 1188b2ed841eSJohannes Berg int ret; 1189b2ed841eSJohannes Berg 1190e705c121SKalle Valo might_sleep(); 1191e705c121SKalle Valo 1192e705c121SKalle Valo WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1193e705c121SKalle Valo 1194e705c121SKalle Valo clear_bit(STATUS_FW_ERROR, &trans->status); 1195b2ed841eSJohannes Berg ret = trans->ops->start_fw(trans, fw, run_in_rfkill); 1196b2ed841eSJohannes Berg if (ret == 0) 1197b2ed841eSJohannes Berg trans->state = IWL_TRANS_FW_STARTED; 1198b2ed841eSJohannes Berg 1199b2ed841eSJohannes Berg return ret; 1200e705c121SKalle Valo } 1201e705c121SKalle Valo 1202bab3cb92SEmmanuel Grumbach static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1203e705c121SKalle Valo { 1204e705c121SKalle Valo might_sleep(); 1205e705c121SKalle Valo 1206bab3cb92SEmmanuel Grumbach trans->ops->stop_device(trans); 1207e705c121SKalle Valo 1208e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1209e705c121SKalle Valo } 1210e705c121SKalle Valo 1211e5f3f215SHaim Dreyfuss static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 121223ae6128SMatti Gottlieb bool reset) 1213e705c121SKalle Valo { 1214e705c121SKalle Valo might_sleep(); 1215e5f3f215SHaim Dreyfuss if (!trans->ops->d3_suspend) 1216cad7850aSHaim Dreyfuss return -EOPNOTSUPP; 1217e5f3f215SHaim Dreyfuss 1218e5f3f215SHaim Dreyfuss return trans->ops->d3_suspend(trans, test, reset); 1219e705c121SKalle Valo } 1220e705c121SKalle Valo 1221e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1222e705c121SKalle Valo enum iwl_d3_status *status, 122323ae6128SMatti Gottlieb bool test, bool reset) 1224e705c121SKalle Valo { 1225e705c121SKalle Valo might_sleep(); 1226e705c121SKalle Valo if (!trans->ops->d3_resume) 1227cad7850aSHaim Dreyfuss return -EOPNOTSUPP; 1228e705c121SKalle Valo 122923ae6128SMatti Gottlieb return trans->ops->d3_resume(trans, status, test, reset); 1230e705c121SKalle Valo } 1231e705c121SKalle Valo 1232e705c121SKalle Valo static inline struct iwl_trans_dump_data * 1233fdb70083SJohannes Berg iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask, 1234fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 1235fdb70083SJohannes Berg void *sanitize_ctx) 1236e705c121SKalle Valo { 1237e705c121SKalle Valo if (!trans->ops->dump_data) 1238e705c121SKalle Valo return NULL; 1239fdb70083SJohannes Berg return trans->ops->dump_data(trans, dump_mask, 1240fdb70083SJohannes Berg sanitize_ops, sanitize_ctx); 1241e705c121SKalle Valo } 1242e705c121SKalle Valo 1243a89c72ffSJohannes Berg static inline struct iwl_device_tx_cmd * 1244e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1245e705c121SKalle Valo { 1246a89c72ffSJohannes Berg return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1247e705c121SKalle Valo } 1248e705c121SKalle Valo 124992fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 125092fe8343SEmmanuel Grumbach 1251e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1252a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd) 1253e705c121SKalle Valo { 12541ea423b0SLuca Coelho kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1255e705c121SKalle Valo } 1256e705c121SKalle Valo 1257e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1258a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue) 1259e705c121SKalle Valo { 1260e705c121SKalle Valo if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1261e705c121SKalle Valo return -EIO; 1262e705c121SKalle Valo 1263e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1264e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1265e5d15cb5SEliad Peller return -EIO; 1266e5d15cb5SEliad Peller } 1267e705c121SKalle Valo 1268e705c121SKalle Valo return trans->ops->tx(trans, skb, dev_cmd, queue); 1269e705c121SKalle Valo } 1270e705c121SKalle Valo 1271e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1272e705c121SKalle Valo int ssn, struct sk_buff_head *skbs) 1273e705c121SKalle Valo { 1274e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1275e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1276e5d15cb5SEliad Peller return; 1277e5d15cb5SEliad Peller } 1278e705c121SKalle Valo 1279e705c121SKalle Valo trans->ops->reclaim(trans, queue, ssn, skbs); 1280e705c121SKalle Valo } 1281e705c121SKalle Valo 1282ba7136f3SAlex Malamud static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1283ba7136f3SAlex Malamud int ptr) 1284ba7136f3SAlex Malamud { 1285ba7136f3SAlex Malamud if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1286ba7136f3SAlex Malamud IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1287ba7136f3SAlex Malamud return; 1288ba7136f3SAlex Malamud } 1289ba7136f3SAlex Malamud 1290ba7136f3SAlex Malamud trans->ops->set_q_ptrs(trans, queue, ptr); 1291ba7136f3SAlex Malamud } 1292ba7136f3SAlex Malamud 1293e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1294e705c121SKalle Valo bool configure_scd) 1295e705c121SKalle Valo { 1296e705c121SKalle Valo trans->ops->txq_disable(trans, queue, configure_scd); 1297e705c121SKalle Valo } 1298e705c121SKalle Valo 1299dcfbd67bSEmmanuel Grumbach static inline bool 1300e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1301e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1302e705c121SKalle Valo unsigned int queue_wdg_timeout) 1303e705c121SKalle Valo { 1304e705c121SKalle Valo might_sleep(); 1305e705c121SKalle Valo 1306e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1307e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1308dcfbd67bSEmmanuel Grumbach return false; 1309e5d15cb5SEliad Peller } 1310e705c121SKalle Valo 1311dcfbd67bSEmmanuel Grumbach return trans->ops->txq_enable(trans, queue, ssn, 1312dcfbd67bSEmmanuel Grumbach cfg, queue_wdg_timeout); 1313e705c121SKalle Valo } 1314e705c121SKalle Valo 131592536c96SSara Sharon static inline int 131692536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 131792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 131892536c96SSara Sharon { 131992536c96SSara Sharon if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 132092536c96SSara Sharon return -ENOTSUPP; 132192536c96SSara Sharon 132292536c96SSara Sharon return trans->ops->rxq_dma_data(trans, queue, data); 132392536c96SSara Sharon } 132492536c96SSara Sharon 13256b35ff91SSara Sharon static inline void 13266b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue) 13276b35ff91SSara Sharon { 13286b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_free)) 13296b35ff91SSara Sharon return; 13306b35ff91SSara Sharon 13316b35ff91SSara Sharon trans->ops->txq_free(trans, queue); 13326b35ff91SSara Sharon } 13336b35ff91SSara Sharon 13346b35ff91SSara Sharon static inline int 13356b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans, 1336227f2597SJohannes Berg u32 flags, u32 sta_mask, u8 tid, 133785b17a33SJohannes Berg int size, unsigned int wdg_timeout) 13386b35ff91SSara Sharon { 13396b35ff91SSara Sharon might_sleep(); 13406b35ff91SSara Sharon 13416b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 13426b35ff91SSara Sharon return -ENOTSUPP; 13436b35ff91SSara Sharon 13446b35ff91SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 13456b35ff91SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 13466b35ff91SSara Sharon return -EIO; 13476b35ff91SSara Sharon } 13486b35ff91SSara Sharon 1349227f2597SJohannes Berg return trans->ops->txq_alloc(trans, flags, sta_mask, tid, 135085b17a33SJohannes Berg size, wdg_timeout); 13516b35ff91SSara Sharon } 13526b35ff91SSara Sharon 135342db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 135442db09c1SLiad Kaufman int queue, bool shared_mode) 135542db09c1SLiad Kaufman { 135642db09c1SLiad Kaufman if (trans->ops->txq_set_shared_mode) 135742db09c1SLiad Kaufman trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 135842db09c1SLiad Kaufman } 135942db09c1SLiad Kaufman 1360e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1361e705c121SKalle Valo int fifo, int sta_id, int tid, 1362e705c121SKalle Valo int frame_limit, u16 ssn, 1363e705c121SKalle Valo unsigned int queue_wdg_timeout) 1364e705c121SKalle Valo { 1365e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1366e705c121SKalle Valo .fifo = fifo, 1367e705c121SKalle Valo .sta_id = sta_id, 1368e705c121SKalle Valo .tid = tid, 1369e705c121SKalle Valo .frame_limit = frame_limit, 1370e705c121SKalle Valo .aggregate = sta_id >= 0, 1371e705c121SKalle Valo }; 1372e705c121SKalle Valo 1373e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1374e705c121SKalle Valo } 1375e705c121SKalle Valo 1376e705c121SKalle Valo static inline 1377e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1378e705c121SKalle Valo unsigned int queue_wdg_timeout) 1379e705c121SKalle Valo { 1380e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1381e705c121SKalle Valo .fifo = fifo, 1382e705c121SKalle Valo .sta_id = -1, 1383e705c121SKalle Valo .tid = IWL_MAX_TID_COUNT, 1384e705c121SKalle Valo .frame_limit = IWL_FRAME_LIMIT, 1385e705c121SKalle Valo .aggregate = false, 1386e705c121SKalle Valo }; 1387e705c121SKalle Valo 1388e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1389e705c121SKalle Valo } 1390e705c121SKalle Valo 1391e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1392e705c121SKalle Valo unsigned long txqs, 1393e705c121SKalle Valo bool freeze) 1394e705c121SKalle Valo { 1395e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1396e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1397e5d15cb5SEliad Peller return; 1398e5d15cb5SEliad Peller } 1399e705c121SKalle Valo 1400e705c121SKalle Valo if (trans->ops->freeze_txq_timer) 1401e705c121SKalle Valo trans->ops->freeze_txq_timer(trans, txqs, freeze); 1402e705c121SKalle Valo } 1403e705c121SKalle Valo 14040cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 14050cd58eaaSEmmanuel Grumbach bool block) 14060cd58eaaSEmmanuel Grumbach { 1407e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 14080cd58eaaSEmmanuel Grumbach IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1409e5d15cb5SEliad Peller return; 1410e5d15cb5SEliad Peller } 14110cd58eaaSEmmanuel Grumbach 14120cd58eaaSEmmanuel Grumbach if (trans->ops->block_txq_ptrs) 14130cd58eaaSEmmanuel Grumbach trans->ops->block_txq_ptrs(trans, block); 14140cd58eaaSEmmanuel Grumbach } 14150cd58eaaSEmmanuel Grumbach 1416a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1417e705c121SKalle Valo u32 txqs) 1418e705c121SKalle Valo { 1419d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1420d6d517b7SSara Sharon return -ENOTSUPP; 1421d6d517b7SSara Sharon 14222b84e632SEmmanuel Grumbach /* No need to wait if the firmware is not alive */ 14232b84e632SEmmanuel Grumbach if (trans->state != IWL_TRANS_FW_ALIVE) { 1424e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1425e5d15cb5SEliad Peller return -EIO; 1426e5d15cb5SEliad Peller } 1427e705c121SKalle Valo 1428a1a57877SSara Sharon return trans->ops->wait_tx_queues_empty(trans, txqs); 1429e705c121SKalle Valo } 1430e705c121SKalle Valo 1431d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1432d6d517b7SSara Sharon { 1433d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1434d6d517b7SSara Sharon return -ENOTSUPP; 1435d6d517b7SSara Sharon 1436d6d517b7SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1437d6d517b7SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1438d6d517b7SSara Sharon return -EIO; 1439d6d517b7SSara Sharon } 1440d6d517b7SSara Sharon 1441d6d517b7SSara Sharon return trans->ops->wait_txq_empty(trans, queue); 1442d6d517b7SSara Sharon } 1443d6d517b7SSara Sharon 1444e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1445e705c121SKalle Valo { 1446e705c121SKalle Valo trans->ops->write8(trans, ofs, val); 1447e705c121SKalle Valo } 1448e705c121SKalle Valo 1449e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1450e705c121SKalle Valo { 1451e705c121SKalle Valo trans->ops->write32(trans, ofs, val); 1452e705c121SKalle Valo } 1453e705c121SKalle Valo 1454e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1455e705c121SKalle Valo { 1456e705c121SKalle Valo return trans->ops->read32(trans, ofs); 1457e705c121SKalle Valo } 1458e705c121SKalle Valo 1459e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1460e705c121SKalle Valo { 1461e705c121SKalle Valo return trans->ops->read_prph(trans, ofs); 1462e705c121SKalle Valo } 1463e705c121SKalle Valo 1464e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1465e705c121SKalle Valo u32 val) 1466e705c121SKalle Valo { 1467e705c121SKalle Valo return trans->ops->write_prph(trans, ofs, val); 1468e705c121SKalle Valo } 1469e705c121SKalle Valo 1470e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1471e705c121SKalle Valo void *buf, int dwords) 1472e705c121SKalle Valo { 1473e705c121SKalle Valo return trans->ops->read_mem(trans, addr, buf, dwords); 1474e705c121SKalle Valo } 1475e705c121SKalle Valo 1476e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1477e705c121SKalle Valo do { \ 1478e705c121SKalle Valo if (__builtin_constant_p(bufsize)) \ 1479e705c121SKalle Valo BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1480e705c121SKalle Valo iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1481e705c121SKalle Valo } while (0) 1482e705c121SKalle Valo 1483c0941aceSMukesh Sisodiya static inline int iwl_trans_write_imr_mem(struct iwl_trans *trans, 1484c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, 1485c0941aceSMukesh Sisodiya u32 byte_cnt) 1486c0941aceSMukesh Sisodiya { 1487c0941aceSMukesh Sisodiya if (trans->ops->imr_dma_data) 1488c0941aceSMukesh Sisodiya return trans->ops->imr_dma_data(trans, dst_addr, src_addr, byte_cnt); 1489c0941aceSMukesh Sisodiya return 0; 1490c0941aceSMukesh Sisodiya } 1491c0941aceSMukesh Sisodiya 1492e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1493e705c121SKalle Valo { 1494e705c121SKalle Valo u32 value; 1495e705c121SKalle Valo 1496d9d115feSJohannes Berg if (iwl_trans_read_mem(trans, addr, &value, 1)) 1497e705c121SKalle Valo return 0xa5a5a5a5; 1498e705c121SKalle Valo 1499e705c121SKalle Valo return value; 1500e705c121SKalle Valo } 1501e705c121SKalle Valo 1502e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1503e705c121SKalle Valo const void *buf, int dwords) 1504e705c121SKalle Valo { 1505e705c121SKalle Valo return trans->ops->write_mem(trans, addr, buf, dwords); 1506e705c121SKalle Valo } 1507e705c121SKalle Valo 1508e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1509e705c121SKalle Valo u32 val) 1510e705c121SKalle Valo { 1511e705c121SKalle Valo return iwl_trans_write_mem(trans, addr, &val, 1); 1512e705c121SKalle Valo } 1513e705c121SKalle Valo 1514e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1515e705c121SKalle Valo { 1516e705c121SKalle Valo if (trans->ops->set_pmi) 1517e705c121SKalle Valo trans->ops->set_pmi(trans, state); 1518e705c121SKalle Valo } 1519e705c121SKalle Valo 152015bf5ac6SJohannes Berg static inline int iwl_trans_sw_reset(struct iwl_trans *trans, 152115bf5ac6SJohannes Berg bool retake_ownership) 1522870c2a11SGolan Ben Ami { 1523870c2a11SGolan Ben Ami if (trans->ops->sw_reset) 152415bf5ac6SJohannes Berg return trans->ops->sw_reset(trans, retake_ownership); 152515bf5ac6SJohannes Berg return 0; 1526870c2a11SGolan Ben Ami } 1527870c2a11SGolan Ben Ami 1528e705c121SKalle Valo static inline void 1529e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1530e705c121SKalle Valo { 1531e705c121SKalle Valo trans->ops->set_bits_mask(trans, reg, mask, value); 1532e705c121SKalle Valo } 1533e705c121SKalle Valo 15341ed08f6fSJohannes Berg #define iwl_trans_grab_nic_access(trans) \ 1535e705c121SKalle Valo __cond_lock(nic_access, \ 15361ed08f6fSJohannes Berg likely((trans)->ops->grab_nic_access(trans))) 1537e705c121SKalle Valo 1538e705c121SKalle Valo static inline void __releases(nic_access) 15391ed08f6fSJohannes Berg iwl_trans_release_nic_access(struct iwl_trans *trans) 1540e705c121SKalle Valo { 15411ed08f6fSJohannes Berg trans->ops->release_nic_access(trans); 1542e705c121SKalle Valo __release(nic_access); 1543e705c121SKalle Valo } 1544e705c121SKalle Valo 1545b8221b0fSJohannes Berg static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync) 1546e705c121SKalle Valo { 1547e705c121SKalle Valo if (WARN_ON_ONCE(!trans->op_mode)) 1548e705c121SKalle Valo return; 1549e705c121SKalle Valo 1550e705c121SKalle Valo /* prevent double restarts due to the same erroneous FW */ 1551152fdc0fSJohannes Berg if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1552b8221b0fSJohannes Berg iwl_op_mode_nic_error(trans->op_mode, sync); 1553152fdc0fSJohannes Berg trans->state = IWL_TRANS_NO_FW; 1554152fdc0fSJohannes Berg } 1555e705c121SKalle Valo } 1556e705c121SKalle Valo 1557068893b7SShahar S Matityahu static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1558068893b7SShahar S Matityahu { 1559068893b7SShahar S Matityahu return trans->state == IWL_TRANS_FW_ALIVE; 1560068893b7SShahar S Matityahu } 1561068893b7SShahar S Matityahu 1562d1967ce6SShahar S Matityahu static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1563d1967ce6SShahar S Matityahu { 1564d1967ce6SShahar S Matityahu if (trans->ops->sync_nmi) 1565d1967ce6SShahar S Matityahu trans->ops->sync_nmi(trans); 1566d1967ce6SShahar S Matityahu } 1567d1967ce6SShahar S Matityahu 15683161a34dSMordechay Goodstein void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 15693161a34dSMordechay Goodstein u32 sw_err_bit); 15703161a34dSMordechay Goodstein 1571194d1f84SAlon Giladi static inline int iwl_trans_load_pnvm(struct iwl_trans *trans, 157233182810SAlon Giladi const struct iwl_pnvm_image *pnvm_data, 157333182810SAlon Giladi const struct iwl_ucode_capabilities *capa) 1574a182dfabSLuca Coelho { 157533182810SAlon Giladi return trans->ops->load_pnvm(trans, pnvm_data, capa); 157669725928SLuca Coelho } 157769725928SLuca Coelho 157833182810SAlon Giladi static inline void iwl_trans_set_pnvm(struct iwl_trans *trans, 157933182810SAlon Giladi const struct iwl_ucode_capabilities *capa) 1580194d1f84SAlon Giladi { 1581194d1f84SAlon Giladi if (trans->ops->set_pnvm) 158233182810SAlon Giladi trans->ops->set_pnvm(trans, capa); 1583a182dfabSLuca Coelho } 1584a182dfabSLuca Coelho 1585ea3571f4SAlon Giladi static inline int iwl_trans_load_reduce_power 1586ea3571f4SAlon Giladi (struct iwl_trans *trans, 15877c9c8477SAlon Giladi const struct iwl_pnvm_image *payloads, 15887c9c8477SAlon Giladi const struct iwl_ucode_capabilities *capa) 15899dad325fSLuca Coelho { 15907c9c8477SAlon Giladi return trans->ops->load_reduce_power(trans, payloads, capa); 15919dad325fSLuca Coelho } 15929dad325fSLuca Coelho 15937c9c8477SAlon Giladi static inline void 15947c9c8477SAlon Giladi iwl_trans_set_reduce_power(struct iwl_trans *trans, 15957c9c8477SAlon Giladi const struct iwl_ucode_capabilities *capa) 1596c738fb61SAlon Giladi { 1597c738fb61SAlon Giladi if (trans->ops->set_reduce_power) 15987c9c8477SAlon Giladi trans->ops->set_reduce_power(trans, capa); 15999dad325fSLuca Coelho } 16009dad325fSLuca Coelho 1601a1af4c48SShahar S Matityahu static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1602a1af4c48SShahar S Matityahu { 1603341bd290SShahar S Matityahu return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1604341bd290SShahar S Matityahu trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1605a1af4c48SShahar S Matityahu } 1606a1af4c48SShahar S Matityahu 16073161a34dSMordechay Goodstein static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable) 16083161a34dSMordechay Goodstein { 16093161a34dSMordechay Goodstein if (trans->ops->interrupts) 16103161a34dSMordechay Goodstein trans->ops->interrupts(trans, enable); 16113161a34dSMordechay Goodstein } 16123161a34dSMordechay Goodstein 1613e705c121SKalle Valo /***************************************************** 1614e705c121SKalle Valo * transport helper functions 1615e705c121SKalle Valo *****************************************************/ 1616e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1617e705c121SKalle Valo struct device *dev, 1618a89c72ffSJohannes Berg const struct iwl_trans_ops *ops, 1619fda1bd0dSMordechay Goodstein const struct iwl_cfg_trans_params *cfg_trans); 1620d12455fdSJohannes Berg int iwl_trans_init(struct iwl_trans *trans); 1621e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans); 1622e705c121SKalle Valo 1623d4f1a50cSJohannes Berg static inline bool iwl_trans_is_hw_error_value(u32 val) 1624d4f1a50cSJohannes Berg { 1625d4f1a50cSJohannes Berg return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50); 1626d4f1a50cSJohannes Berg } 1627d4f1a50cSJohannes Berg 1628e705c121SKalle Valo /***************************************************** 1629e705c121SKalle Valo * driver (transport) register/unregister functions 1630e705c121SKalle Valo ******************************************************/ 1631e705c121SKalle Valo int __must_check iwl_pci_register_driver(void); 1632e705c121SKalle Valo void iwl_pci_unregister_driver(void); 1633b8133439SAvraham Stern void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan); 1634e705c121SKalle Valo 1635e705c121SKalle Valo #endif /* __iwl_trans_h__ */ 1636