1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 106b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 336b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #ifndef __iwl_trans_h__ 65e705c121SKalle Valo #define __iwl_trans_h__ 66e705c121SKalle Valo 67e705c121SKalle Valo #include <linux/ieee80211.h> 68e705c121SKalle Valo #include <linux/mm.h> /* for page_address */ 69e705c121SKalle Valo #include <linux/lockdep.h> 7039bdb17eSSharon Dvir #include <linux/kernel.h> 71e705c121SKalle Valo 72e705c121SKalle Valo #include "iwl-debug.h" 73e705c121SKalle Valo #include "iwl-config.h" 74d962f9b1SJohannes Berg #include "fw/img.h" 75e705c121SKalle Valo #include "iwl-op-mode.h" 76d172a5efSJohannes Berg #include "fw/api/cmdhdr.h" 77d172a5efSJohannes Berg #include "fw/api/txq.h" 78f14cda6fSSara Sharon #include "fw/api/dbg-tlv.h" 79f14cda6fSSara Sharon #include "iwl-dbg-tlv.h" 80e705c121SKalle Valo 81e705c121SKalle Valo /** 82e705c121SKalle Valo * DOC: Transport layer - what is it ? 83e705c121SKalle Valo * 84e705c121SKalle Valo * The transport layer is the layer that deals with the HW directly. It provides 85e705c121SKalle Valo * an abstraction of the underlying HW to the upper layer. The transport layer 86e705c121SKalle Valo * doesn't provide any policy, algorithm or anything of this kind, but only 87e705c121SKalle Valo * mechanisms to make the HW do something. It is not completely stateless but 88e705c121SKalle Valo * close to it. 89e705c121SKalle Valo * We will have an implementation for each different supported bus. 90e705c121SKalle Valo */ 91e705c121SKalle Valo 92e705c121SKalle Valo /** 93e705c121SKalle Valo * DOC: Life cycle of the transport layer 94e705c121SKalle Valo * 95e705c121SKalle Valo * The transport layer has a very precise life cycle. 96e705c121SKalle Valo * 97e705c121SKalle Valo * 1) A helper function is called during the module initialization and 98e705c121SKalle Valo * registers the bus driver's ops with the transport's alloc function. 99e705c121SKalle Valo * 2) Bus's probe calls to the transport layer's allocation functions. 100e705c121SKalle Valo * Of course this function is bus specific. 101e705c121SKalle Valo * 3) This allocation functions will spawn the upper layer which will 102e705c121SKalle Valo * register mac80211. 103e705c121SKalle Valo * 104e705c121SKalle Valo * 4) At some point (i.e. mac80211's start call), the op_mode will call 105e705c121SKalle Valo * the following sequence: 106e705c121SKalle Valo * start_hw 107e705c121SKalle Valo * start_fw 108e705c121SKalle Valo * 109e705c121SKalle Valo * 5) Then when finished (or reset): 110e705c121SKalle Valo * stop_device 111e705c121SKalle Valo * 112e705c121SKalle Valo * 6) Eventually, the free function will be called. 113e705c121SKalle Valo */ 114e705c121SKalle Valo 115e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 116e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID 0x55550000 117e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN 0x40 118fbe41127SSara Sharon #define FH_RSCSR_RPA_EN BIT(25) 1199d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN BIT(26) 120ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS 16 121ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK 0x3F0000 122e705c121SKalle Valo 123e705c121SKalle Valo struct iwl_rx_packet { 124e705c121SKalle Valo /* 125e705c121SKalle Valo * The first 4 bytes of the RX frame header contain both the RX frame 126e705c121SKalle Valo * size and some flags. 127e705c121SKalle Valo * Bit fields: 128e705c121SKalle Valo * 31: flag flush RB request 129e705c121SKalle Valo * 30: flag ignore TC (terminal counter) request 130e705c121SKalle Valo * 29: flag fast IRQ request 1319d0fc5a5SDavid Spinadel * 28-27: Reserved 1329d0fc5a5SDavid Spinadel * 26: RADA enabled 133fbe41127SSara Sharon * 25: Offload enabled 134ab2e696bSSara Sharon * 24: RPF enabled 135ab2e696bSSara Sharon * 23: RSS enabled 136ab2e696bSSara Sharon * 22: Checksum enabled 137ab2e696bSSara Sharon * 21-16: RX queue 138ab2e696bSSara Sharon * 15-14: Reserved 139e705c121SKalle Valo * 13-00: RX frame size 140e705c121SKalle Valo */ 141e705c121SKalle Valo __le32 len_n_flags; 142e705c121SKalle Valo struct iwl_cmd_header hdr; 143e705c121SKalle Valo u8 data[]; 144e705c121SKalle Valo } __packed; 145e705c121SKalle Valo 146e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 147e705c121SKalle Valo { 148e705c121SKalle Valo return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 149e705c121SKalle Valo } 150e705c121SKalle Valo 151e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 152e705c121SKalle Valo { 153e705c121SKalle Valo return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 154e705c121SKalle Valo } 155e705c121SKalle Valo 156e705c121SKalle Valo /** 157e705c121SKalle Valo * enum CMD_MODE - how to send the host commands ? 158e705c121SKalle Valo * 159e705c121SKalle Valo * @CMD_ASYNC: Return right away and don't wait for the response 160e705c121SKalle Valo * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 161e705c121SKalle Valo * the response. The caller needs to call iwl_free_resp when done. 162e705c121SKalle Valo * @CMD_HIGH_PRIO: The command is high priority - it goes to the front of the 163e705c121SKalle Valo * command queue, but after other high priority commands. Valid only 164e705c121SKalle Valo * with CMD_ASYNC. 165e705c121SKalle Valo * @CMD_SEND_IN_IDLE: The command should be sent even when the trans is idle. 166e705c121SKalle Valo * @CMD_MAKE_TRANS_IDLE: The command response should mark the trans as idle. 167e705c121SKalle Valo * @CMD_WAKE_UP_TRANS: The command response should wake up the trans 168e705c121SKalle Valo * (i.e. mark it as non-idle). 169dcbb4746SEmmanuel Grumbach * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 170dcbb4746SEmmanuel Grumbach * called after this command completes. Valid only with CMD_ASYNC. 171e705c121SKalle Valo */ 172e705c121SKalle Valo enum CMD_MODE { 173e705c121SKalle Valo CMD_ASYNC = BIT(0), 174e705c121SKalle Valo CMD_WANT_SKB = BIT(1), 175e705c121SKalle Valo CMD_SEND_IN_RFKILL = BIT(2), 176e705c121SKalle Valo CMD_HIGH_PRIO = BIT(3), 177e705c121SKalle Valo CMD_SEND_IN_IDLE = BIT(4), 178e705c121SKalle Valo CMD_MAKE_TRANS_IDLE = BIT(5), 179e705c121SKalle Valo CMD_WAKE_UP_TRANS = BIT(6), 180dcbb4746SEmmanuel Grumbach CMD_WANT_ASYNC_CALLBACK = BIT(7), 181e705c121SKalle Valo }; 182e705c121SKalle Valo 183e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320 184e705c121SKalle Valo 185e705c121SKalle Valo /** 186e705c121SKalle Valo * struct iwl_device_cmd 187e705c121SKalle Valo * 188e705c121SKalle Valo * For allocation of the command and tx queues, this establishes the overall 189e705c121SKalle Valo * size of the largest command we send to uCode, except for commands that 190e705c121SKalle Valo * aren't fully copied and use other TFD space. 191e705c121SKalle Valo */ 192e705c121SKalle Valo struct iwl_device_cmd { 193e705c121SKalle Valo union { 194e705c121SKalle Valo struct { 195e705c121SKalle Valo struct iwl_cmd_header hdr; /* uCode API */ 196e705c121SKalle Valo u8 payload[DEF_CMD_PAYLOAD_SIZE]; 197e705c121SKalle Valo }; 198e705c121SKalle Valo struct { 199e705c121SKalle Valo struct iwl_cmd_header_wide hdr_wide; 200e705c121SKalle Valo u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 201e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide) + 202e705c121SKalle Valo sizeof(struct iwl_cmd_header)]; 203e705c121SKalle Valo }; 204e705c121SKalle Valo }; 205e705c121SKalle Valo } __packed; 206e705c121SKalle Valo 207e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 208e705c121SKalle Valo 209e705c121SKalle Valo /* 210e705c121SKalle Valo * number of transfer buffers (fragments) per transmit frame descriptor; 211e705c121SKalle Valo * this is just the driver's idea, the hardware supports 20 212e705c121SKalle Valo */ 213e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD 2 214e705c121SKalle Valo 215e705c121SKalle Valo /** 216b8aed81cSJohannes Berg * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 217e705c121SKalle Valo * 218e705c121SKalle Valo * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 219e705c121SKalle Valo * ring. The transport layer doesn't map the command's buffer to DMA, but 220e705c121SKalle Valo * rather copies it to a previously allocated DMA buffer. This flag tells 221e705c121SKalle Valo * the transport layer not to copy the command, but to map the existing 222e705c121SKalle Valo * buffer (that is passed in) instead. This saves the memcpy and allows 223e705c121SKalle Valo * commands that are bigger than the fixed buffer to be submitted. 224e705c121SKalle Valo * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 225e705c121SKalle Valo * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 226e705c121SKalle Valo * chunk internally and free it again after the command completes. This 227e705c121SKalle Valo * can (currently) be used only once per command. 228e705c121SKalle Valo * Note that a TFD entry after a DUP one cannot be a normal copied one. 229e705c121SKalle Valo */ 230e705c121SKalle Valo enum iwl_hcmd_dataflag { 231e705c121SKalle Valo IWL_HCMD_DFL_NOCOPY = BIT(0), 232e705c121SKalle Valo IWL_HCMD_DFL_DUP = BIT(1), 233e705c121SKalle Valo }; 234e705c121SKalle Valo 235e705c121SKalle Valo /** 236e705c121SKalle Valo * struct iwl_host_cmd - Host command to the uCode 237e705c121SKalle Valo * 238e705c121SKalle Valo * @data: array of chunks that composes the data of the host command 239e705c121SKalle Valo * @resp_pkt: response packet, if %CMD_WANT_SKB was set 240e705c121SKalle Valo * @_rx_page_order: (internally used to free response packet) 241e705c121SKalle Valo * @_rx_page_addr: (internally used to free response packet) 242e705c121SKalle Valo * @flags: can be CMD_* 243e705c121SKalle Valo * @len: array of the lengths of the chunks in data 244e705c121SKalle Valo * @dataflags: IWL_HCMD_DFL_* 245e705c121SKalle Valo * @id: command id of the host command, for wide commands encoding the 246e705c121SKalle Valo * version and group as well 247e705c121SKalle Valo */ 248e705c121SKalle Valo struct iwl_host_cmd { 249e705c121SKalle Valo const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 250e705c121SKalle Valo struct iwl_rx_packet *resp_pkt; 251e705c121SKalle Valo unsigned long _rx_page_addr; 252e705c121SKalle Valo u32 _rx_page_order; 253e705c121SKalle Valo 254e705c121SKalle Valo u32 flags; 255e705c121SKalle Valo u32 id; 256e705c121SKalle Valo u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 257e705c121SKalle Valo u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 258e705c121SKalle Valo }; 259e705c121SKalle Valo 260e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 261e705c121SKalle Valo { 262e705c121SKalle Valo free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 263e705c121SKalle Valo } 264e705c121SKalle Valo 265e705c121SKalle Valo struct iwl_rx_cmd_buffer { 266e705c121SKalle Valo struct page *_page; 267e705c121SKalle Valo int _offset; 268e705c121SKalle Valo bool _page_stolen; 269e705c121SKalle Valo u32 _rx_page_order; 270e705c121SKalle Valo unsigned int truesize; 2717891965dSSara Sharon u8 status; 272e705c121SKalle Valo }; 273e705c121SKalle Valo 274e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 275e705c121SKalle Valo { 276e705c121SKalle Valo return (void *)((unsigned long)page_address(r->_page) + r->_offset); 277e705c121SKalle Valo } 278e705c121SKalle Valo 279e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 280e705c121SKalle Valo { 281e705c121SKalle Valo return r->_offset; 282e705c121SKalle Valo } 283e705c121SKalle Valo 284e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 285e705c121SKalle Valo { 286e705c121SKalle Valo r->_page_stolen = true; 287e705c121SKalle Valo get_page(r->_page); 288e705c121SKalle Valo return r->_page; 289e705c121SKalle Valo } 290e705c121SKalle Valo 291e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 292e705c121SKalle Valo { 293e705c121SKalle Valo __free_pages(r->_page, r->_rx_page_order); 294e705c121SKalle Valo } 295e705c121SKalle Valo 296e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS 6 297e705c121SKalle Valo 298e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 299e705c121SKalle Valo 300e705c121SKalle Valo /* 301e705c121SKalle Valo * Maximum number of HW queues the transport layer 302e705c121SKalle Valo * currently supports 303e705c121SKalle Valo */ 304e705c121SKalle Valo #define IWL_MAX_HW_QUEUES 32 305e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES 512 306e982bc2cSSara Sharon 307e705c121SKalle Valo #define IWL_MAX_TID_COUNT 8 308c65f4e03SSara Sharon #define IWL_MGMT_TID 15 309e705c121SKalle Valo #define IWL_FRAME_LIMIT 64 310e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES 16 311e705c121SKalle Valo 312e705c121SKalle Valo /** 313e705c121SKalle Valo * enum iwl_wowlan_status - WoWLAN image/device status 314e705c121SKalle Valo * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 315e705c121SKalle Valo * @IWL_D3_STATUS_RESET: device was reset while suspended 316e705c121SKalle Valo */ 317e705c121SKalle Valo enum iwl_d3_status { 318e705c121SKalle Valo IWL_D3_STATUS_ALIVE, 319e705c121SKalle Valo IWL_D3_STATUS_RESET, 320e705c121SKalle Valo }; 321e705c121SKalle Valo 322e705c121SKalle Valo /** 323e705c121SKalle Valo * enum iwl_trans_status: transport status flags 324e705c121SKalle Valo * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 325e705c121SKalle Valo * @STATUS_DEVICE_ENABLED: APM is enabled 326e705c121SKalle Valo * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 327e705c121SKalle Valo * @STATUS_INT_ENABLED: interrupts are enabled 328326477e4SJohannes Berg * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 329326477e4SJohannes Berg * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 330e705c121SKalle Valo * @STATUS_FW_ERROR: the fw is in error state 331e705c121SKalle Valo * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 332e705c121SKalle Valo * are sent 333e705c121SKalle Valo * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 334e705c121SKalle Valo * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 335700b3799SShahar S Matityahu * @STATUS_FW_WAIT_DUMP: if set, wait until cleared before collecting dump 336e705c121SKalle Valo */ 337e705c121SKalle Valo enum iwl_trans_status { 338e705c121SKalle Valo STATUS_SYNC_HCMD_ACTIVE, 339e705c121SKalle Valo STATUS_DEVICE_ENABLED, 340e705c121SKalle Valo STATUS_TPOWER_PMI, 341e705c121SKalle Valo STATUS_INT_ENABLED, 342326477e4SJohannes Berg STATUS_RFKILL_HW, 343326477e4SJohannes Berg STATUS_RFKILL_OPMODE, 344e705c121SKalle Valo STATUS_FW_ERROR, 345e705c121SKalle Valo STATUS_TRANS_GOING_IDLE, 346e705c121SKalle Valo STATUS_TRANS_IDLE, 347e705c121SKalle Valo STATUS_TRANS_DEAD, 348700b3799SShahar S Matityahu STATUS_FW_WAIT_DUMP, 349e705c121SKalle Valo }; 350e705c121SKalle Valo 3516c4fbcbcSEmmanuel Grumbach static inline int 3526c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 3536c4fbcbcSEmmanuel Grumbach { 3546c4fbcbcSEmmanuel Grumbach switch (rb_size) { 3551a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 3561a4968d1SGolan Ben Ami return get_order(2 * 1024); 3576c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 3586c4fbcbcSEmmanuel Grumbach return get_order(4 * 1024); 3596c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 3606c4fbcbcSEmmanuel Grumbach return get_order(8 * 1024); 3616c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 3626c4fbcbcSEmmanuel Grumbach return get_order(12 * 1024); 3636c4fbcbcSEmmanuel Grumbach default: 3646c4fbcbcSEmmanuel Grumbach WARN_ON(1); 3656c4fbcbcSEmmanuel Grumbach return -1; 3666c4fbcbcSEmmanuel Grumbach } 3676c4fbcbcSEmmanuel Grumbach } 3686c4fbcbcSEmmanuel Grumbach 36939bdb17eSSharon Dvir struct iwl_hcmd_names { 37039bdb17eSSharon Dvir u8 cmd_id; 37139bdb17eSSharon Dvir const char *const cmd_name; 37239bdb17eSSharon Dvir }; 37339bdb17eSSharon Dvir 37439bdb17eSSharon Dvir #define HCMD_NAME(x) \ 37539bdb17eSSharon Dvir { .cmd_id = x, .cmd_name = #x } 37639bdb17eSSharon Dvir 37739bdb17eSSharon Dvir struct iwl_hcmd_arr { 37839bdb17eSSharon Dvir const struct iwl_hcmd_names *arr; 37939bdb17eSSharon Dvir int size; 38039bdb17eSSharon Dvir }; 38139bdb17eSSharon Dvir 38239bdb17eSSharon Dvir #define HCMD_ARR(x) \ 38339bdb17eSSharon Dvir { .arr = x, .size = ARRAY_SIZE(x) } 38439bdb17eSSharon Dvir 385e705c121SKalle Valo /** 386e705c121SKalle Valo * struct iwl_trans_config - transport configuration 387e705c121SKalle Valo * 388e705c121SKalle Valo * @op_mode: pointer to the upper layer. 389e705c121SKalle Valo * @cmd_queue: the index of the command queue. 390e705c121SKalle Valo * Must be set before start_fw. 391e705c121SKalle Valo * @cmd_fifo: the fifo for host commands 392e705c121SKalle Valo * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 393e705c121SKalle Valo * @no_reclaim_cmds: Some devices erroneously don't set the 394e705c121SKalle Valo * SEQ_RX_FRAME bit on some notifications, this is the 395e705c121SKalle Valo * list of such notifications to filter. Max length is 396e705c121SKalle Valo * %MAX_NO_RECLAIM_CMDS. 397e705c121SKalle Valo * @n_no_reclaim_cmds: # of commands in list 3986c4fbcbcSEmmanuel Grumbach * @rx_buf_size: RX buffer size needed for A-MSDUs 399e705c121SKalle Valo * if unset 4k will be the RX buffer size 400e705c121SKalle Valo * @bc_table_dword: set to true if the BC table expects the byte count to be 401e705c121SKalle Valo * in DWORD (as opposed to bytes) 402e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 40341837ca9SEmmanuel Grumbach * @sw_csum_tx: transport should compute the TCP checksum 40439bdb17eSSharon Dvir * @command_groups: array of command groups, each member is an array of the 40539bdb17eSSharon Dvir * commands in the group; for debugging only 40639bdb17eSSharon Dvir * @command_groups_size: number of command groups, to avoid illegal access 40721cb3222SJohannes Berg * @cb_data_offs: offset inside skb->cb to store transport data at, must have 40821cb3222SJohannes Berg * space for at least two pointers 409e705c121SKalle Valo */ 410e705c121SKalle Valo struct iwl_trans_config { 411e705c121SKalle Valo struct iwl_op_mode *op_mode; 412e705c121SKalle Valo 413e705c121SKalle Valo u8 cmd_queue; 414e705c121SKalle Valo u8 cmd_fifo; 415e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 416e705c121SKalle Valo const u8 *no_reclaim_cmds; 417e705c121SKalle Valo unsigned int n_no_reclaim_cmds; 418e705c121SKalle Valo 4196c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 420e705c121SKalle Valo bool bc_table_dword; 421e705c121SKalle Valo bool scd_set_active; 42241837ca9SEmmanuel Grumbach bool sw_csum_tx; 42339bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 42439bdb17eSSharon Dvir int command_groups_size; 425e705c121SKalle Valo 42621cb3222SJohannes Berg u8 cb_data_offs; 427e705c121SKalle Valo }; 428e705c121SKalle Valo 429e705c121SKalle Valo struct iwl_trans_dump_data { 430e705c121SKalle Valo u32 len; 431e705c121SKalle Valo u8 data[]; 432e705c121SKalle Valo }; 433e705c121SKalle Valo 434e705c121SKalle Valo struct iwl_trans; 435e705c121SKalle Valo 436e705c121SKalle Valo struct iwl_trans_txq_scd_cfg { 437e705c121SKalle Valo u8 fifo; 4382a2e9d10SLiad Kaufman u8 sta_id; 439e705c121SKalle Valo u8 tid; 440e705c121SKalle Valo bool aggregate; 441e705c121SKalle Valo int frame_limit; 442e705c121SKalle Valo }; 443e705c121SKalle Valo 4446b35ff91SSara Sharon /** 44592536c96SSara Sharon * struct iwl_trans_rxq_dma_data - RX queue DMA data 44692536c96SSara Sharon * @fr_bd_cb: DMA address of free BD cyclic buffer 44792536c96SSara Sharon * @fr_bd_wid: Initial write index of the free BD cyclic buffer 44892536c96SSara Sharon * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 44992536c96SSara Sharon * @ur_bd_cb: DMA address of used BD cyclic buffer 45092536c96SSara Sharon */ 45192536c96SSara Sharon struct iwl_trans_rxq_dma_data { 45292536c96SSara Sharon u64 fr_bd_cb; 45392536c96SSara Sharon u32 fr_bd_wid; 45492536c96SSara Sharon u64 urbd_stts_wrptr; 45592536c96SSara Sharon u64 ur_bd_cb; 45692536c96SSara Sharon }; 45792536c96SSara Sharon 45892536c96SSara Sharon /** 459e705c121SKalle Valo * struct iwl_trans_ops - transport specific operations 460e705c121SKalle Valo * 461e705c121SKalle Valo * All the handlers MUST be implemented 462e705c121SKalle Valo * 463e705c121SKalle Valo * @start_hw: starts the HW. If low_power is true, the NIC needs to be taken 464e705c121SKalle Valo * out of a low power state. From that point on, the HW can send 465e705c121SKalle Valo * interrupts. May sleep. 466e705c121SKalle Valo * @op_mode_leave: Turn off the HW RF kill indication if on 467e705c121SKalle Valo * May sleep 468e705c121SKalle Valo * @start_fw: allocates and inits all the resources for the transport 469e705c121SKalle Valo * layer. Also kick a fw image. 470e705c121SKalle Valo * May sleep 471e705c121SKalle Valo * @fw_alive: called when the fw sends alive notification. If the fw provides 472e705c121SKalle Valo * the SCD base address in SRAM, then provide it here, or 0 otherwise. 473e705c121SKalle Valo * May sleep 474e705c121SKalle Valo * @stop_device: stops the whole device (embedded CPU put to reset) and stops 475e705c121SKalle Valo * the HW. If low_power is true, the NIC will be put in low power state. 476e705c121SKalle Valo * From that point on, the HW will be stopped but will still issue an 477e705c121SKalle Valo * interrupt if the HW RF kill switch is triggered. 478e705c121SKalle Valo * This callback must do the right thing and not crash even if %start_hw() 479e705c121SKalle Valo * was called but not &start_fw(). May sleep. 480e705c121SKalle Valo * @d3_suspend: put the device into the correct mode for WoWLAN during 481e705c121SKalle Valo * suspend. This is optional, if not implemented WoWLAN will not be 482e705c121SKalle Valo * supported. This callback may sleep. 483e705c121SKalle Valo * @d3_resume: resume the device after WoWLAN, enabling the opmode to 484e705c121SKalle Valo * talk to the WoWLAN image to get its status. This is optional, if not 485e705c121SKalle Valo * implemented WoWLAN will not be supported. This callback may sleep. 486e705c121SKalle Valo * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 487e705c121SKalle Valo * If RFkill is asserted in the middle of a SYNC host command, it must 488e705c121SKalle Valo * return -ERFKILL straight away. 489e705c121SKalle Valo * May sleep only if CMD_ASYNC is not set 4903f73b8caSEmmanuel Grumbach * @tx: send an skb. The transport relies on the op_mode to zero the 4916eb5e529SEmmanuel Grumbach * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 4926eb5e529SEmmanuel Grumbach * the CSUM will be taken care of (TCP CSUM and IP header in case of 4936eb5e529SEmmanuel Grumbach * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 4946eb5e529SEmmanuel Grumbach * header if it is IPv4. 495e705c121SKalle Valo * Must be atomic 496e705c121SKalle Valo * @reclaim: free packet until ssn. Returns a list of freed packets. 497e705c121SKalle Valo * Must be atomic 498e705c121SKalle Valo * @txq_enable: setup a queue. To setup an AC queue, use the 499e705c121SKalle Valo * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 500e705c121SKalle Valo * this one. The op_mode must not configure the HCMD queue. The scheduler 501e705c121SKalle Valo * configuration may be %NULL, in which case the hardware will not be 502dcfbd67bSEmmanuel Grumbach * configured. If true is returned, the operation mode needs to increment 503dcfbd67bSEmmanuel Grumbach * the sequence number of the packets routed to this queue because of a 504dcfbd67bSEmmanuel Grumbach * hardware scheduler bug. May sleep. 505e705c121SKalle Valo * @txq_disable: de-configure a Tx queue to send AMPDUs 506e705c121SKalle Valo * Must be atomic 50742db09c1SLiad Kaufman * @txq_set_shared_mode: change Tx queue shared/unshared marking 508d6d517b7SSara Sharon * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 509d6d517b7SSara Sharon * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 510e705c121SKalle Valo * @freeze_txq_timer: prevents the timer of the queue from firing until the 511e705c121SKalle Valo * queue is set to awake. Must be atomic. 5120cd58eaaSEmmanuel Grumbach * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 5130cd58eaaSEmmanuel Grumbach * that the transport needs to refcount the calls since this function 5140cd58eaaSEmmanuel Grumbach * will be called several times with block = true, and then the queues 5150cd58eaaSEmmanuel Grumbach * need to be unblocked only after the same number of calls with 5160cd58eaaSEmmanuel Grumbach * block = false. 517e705c121SKalle Valo * @write8: write a u8 to a register at offset ofs from the BAR 518e705c121SKalle Valo * @write32: write a u32 to a register at offset ofs from the BAR 519e705c121SKalle Valo * @read32: read a u32 register at offset ofs from the BAR 520e705c121SKalle Valo * @read_prph: read a DWORD from a periphery register 521e705c121SKalle Valo * @write_prph: write a DWORD to a periphery register 522e705c121SKalle Valo * @read_mem: read device's SRAM in DWORD 523e705c121SKalle Valo * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 524e705c121SKalle Valo * will be zeroed. 525e705c121SKalle Valo * @configure: configure parameters required by the transport layer from 526e705c121SKalle Valo * the op_mode. May be called several times before start_fw, can't be 527e705c121SKalle Valo * called after that. 528e705c121SKalle Valo * @set_pmi: set the power pmi state 529e705c121SKalle Valo * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 530e705c121SKalle Valo * Sleeping is not allowed between grab_nic_access and 531e705c121SKalle Valo * release_nic_access. 532e705c121SKalle Valo * @release_nic_access: let the NIC go to sleep. The "flags" parameter 533e705c121SKalle Valo * must be the same one that was sent before to the grab_nic_access. 534e705c121SKalle Valo * @set_bits_mask - set SRAM register according to value and mask. 535e705c121SKalle Valo * @ref: grab a reference to the transport/FW layers, disallowing 536e705c121SKalle Valo * certain low power states 537e705c121SKalle Valo * @unref: release a reference previously taken with @ref. Note that 538e705c121SKalle Valo * initially the reference count is 1, making an initial @unref 539e705c121SKalle Valo * necessary to allow low power states. 540e705c121SKalle Valo * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 541e705c121SKalle Valo * TX'ed commands and similar. The buffer will be vfree'd by the caller. 542e705c121SKalle Valo * Note that the transport must fill in the proper file headers. 543f7805b33SLior Cohen * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 544f7805b33SLior Cohen * of the trans debugfs 545e705c121SKalle Valo */ 546e705c121SKalle Valo struct iwl_trans_ops { 547e705c121SKalle Valo 548e705c121SKalle Valo int (*start_hw)(struct iwl_trans *iwl_trans, bool low_power); 549e705c121SKalle Valo void (*op_mode_leave)(struct iwl_trans *iwl_trans); 550e705c121SKalle Valo int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 551e705c121SKalle Valo bool run_in_rfkill); 552e705c121SKalle Valo void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 553e705c121SKalle Valo void (*stop_device)(struct iwl_trans *trans, bool low_power); 554e705c121SKalle Valo 55523ae6128SMatti Gottlieb void (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 556e705c121SKalle Valo int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 55723ae6128SMatti Gottlieb bool test, bool reset); 558e705c121SKalle Valo 559e705c121SKalle Valo int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 560e705c121SKalle Valo 561e705c121SKalle Valo int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 562e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int queue); 563e705c121SKalle Valo void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 564e705c121SKalle Valo struct sk_buff_head *skbs); 565e705c121SKalle Valo 566dcfbd67bSEmmanuel Grumbach bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 567e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 568e705c121SKalle Valo unsigned int queue_wdg_timeout); 569e705c121SKalle Valo void (*txq_disable)(struct iwl_trans *trans, int queue, 570e705c121SKalle Valo bool configure_scd); 5712f7a3863SLuca Coelho /* 22000 functions */ 5726b35ff91SSara Sharon int (*txq_alloc)(struct iwl_trans *trans, 5731169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 5745369774cSSara Sharon int cmd_id, int size, 5756b35ff91SSara Sharon unsigned int queue_wdg_timeout); 5766b35ff91SSara Sharon void (*txq_free)(struct iwl_trans *trans, int queue); 57792536c96SSara Sharon int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 57892536c96SSara Sharon struct iwl_trans_rxq_dma_data *data); 579e705c121SKalle Valo 58042db09c1SLiad Kaufman void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 58142db09c1SLiad Kaufman bool shared); 58242db09c1SLiad Kaufman 583a1a57877SSara Sharon int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 584d6d517b7SSara Sharon int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 585e705c121SKalle Valo void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 586e705c121SKalle Valo bool freeze); 5870cd58eaaSEmmanuel Grumbach void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 588e705c121SKalle Valo 589e705c121SKalle Valo void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 590e705c121SKalle Valo void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 591e705c121SKalle Valo u32 (*read32)(struct iwl_trans *trans, u32 ofs); 592e705c121SKalle Valo u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 593e705c121SKalle Valo void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 594e705c121SKalle Valo int (*read_mem)(struct iwl_trans *trans, u32 addr, 595e705c121SKalle Valo void *buf, int dwords); 596e705c121SKalle Valo int (*write_mem)(struct iwl_trans *trans, u32 addr, 597e705c121SKalle Valo const void *buf, int dwords); 598e705c121SKalle Valo void (*configure)(struct iwl_trans *trans, 599e705c121SKalle Valo const struct iwl_trans_config *trans_cfg); 600e705c121SKalle Valo void (*set_pmi)(struct iwl_trans *trans, bool state); 601870c2a11SGolan Ben Ami void (*sw_reset)(struct iwl_trans *trans); 60223ba9340SEmmanuel Grumbach bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags); 603e705c121SKalle Valo void (*release_nic_access)(struct iwl_trans *trans, 604e705c121SKalle Valo unsigned long *flags); 605e705c121SKalle Valo void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 606e705c121SKalle Valo u32 value); 607e705c121SKalle Valo void (*ref)(struct iwl_trans *trans); 608e705c121SKalle Valo void (*unref)(struct iwl_trans *trans); 609e705c121SKalle Valo int (*suspend)(struct iwl_trans *trans); 610e705c121SKalle Valo void (*resume)(struct iwl_trans *trans); 611e705c121SKalle Valo 612e705c121SKalle Valo struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 61379f033f6SSara Sharon u32 dump_mask); 614f7805b33SLior Cohen void (*debugfs_cleanup)(struct iwl_trans *trans); 615e705c121SKalle Valo }; 616e705c121SKalle Valo 617e705c121SKalle Valo /** 618e705c121SKalle Valo * enum iwl_trans_state - state of the transport layer 619e705c121SKalle Valo * 620e705c121SKalle Valo * @IWL_TRANS_NO_FW: no fw has sent an alive response 621e705c121SKalle Valo * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response 622e705c121SKalle Valo */ 623e705c121SKalle Valo enum iwl_trans_state { 624e705c121SKalle Valo IWL_TRANS_NO_FW = 0, 625e705c121SKalle Valo IWL_TRANS_FW_ALIVE = 1, 626e705c121SKalle Valo }; 627e705c121SKalle Valo 628e705c121SKalle Valo /** 629b7282643SLuca Coelho * DOC: Platform power management 630e705c121SKalle Valo * 631b7282643SLuca Coelho * There are two types of platform power management: system-wide 632b7282643SLuca Coelho * (WoWLAN) and runtime. 633b7282643SLuca Coelho * 634b7282643SLuca Coelho * In system-wide power management the entire platform goes into a low 635b7282643SLuca Coelho * power state (e.g. idle or suspend to RAM) at the same time and the 636b7282643SLuca Coelho * device is configured as a wakeup source for the entire platform. 637b7282643SLuca Coelho * This is usually triggered by userspace activity (e.g. the user 638b7282643SLuca Coelho * presses the suspend button or a power management daemon decides to 639b7282643SLuca Coelho * put the platform in low power mode). The device's behavior in this 640b7282643SLuca Coelho * mode is dictated by the wake-on-WLAN configuration. 641b7282643SLuca Coelho * 642b7282643SLuca Coelho * In runtime power management, only the devices which are themselves 643b7282643SLuca Coelho * idle enter a low power state. This is done at runtime, which means 644b7282643SLuca Coelho * that the entire system is still running normally. This mode is 645b7282643SLuca Coelho * usually triggered automatically by the device driver and requires 646b7282643SLuca Coelho * the ability to enter and exit the low power modes in a very short 647b7282643SLuca Coelho * time, so there is not much impact in usability. 648b7282643SLuca Coelho * 649b7282643SLuca Coelho * The terms used for the device's behavior are as follows: 650b7282643SLuca Coelho * 651b7282643SLuca Coelho * - D0: the device is fully powered and the host is awake; 652b7282643SLuca Coelho * - D3: the device is in low power mode and only reacts to 653b7282643SLuca Coelho * specific events (e.g. magic-packet received or scan 654b7282643SLuca Coelho * results found); 655b7282643SLuca Coelho * - D0I3: the device is in low power mode and reacts to any 656b7282643SLuca Coelho * activity (e.g. RX); 657b7282643SLuca Coelho * 658b7282643SLuca Coelho * These terms reflect the power modes in the firmware and are not to 659b7282643SLuca Coelho * be confused with the physical device power state. The NIC can be 660b7282643SLuca Coelho * in D0I3 mode even if, for instance, the PCI device is in D3 state. 661e705c121SKalle Valo */ 662b7282643SLuca Coelho 663b7282643SLuca Coelho /** 664b7282643SLuca Coelho * enum iwl_plat_pm_mode - platform power management mode 665b7282643SLuca Coelho * 666b7282643SLuca Coelho * This enumeration describes the device's platform power management 667b7282643SLuca Coelho * behavior when in idle mode (i.e. runtime power management) or when 668b7282643SLuca Coelho * in system-wide suspend (i.e WoWLAN). 669b7282643SLuca Coelho * 670b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 671b7282643SLuca Coelho * device. At runtime, this means that nothing happens and the 672b7282643SLuca Coelho * device always remains in active. In system-wide suspend mode, 673b7282643SLuca Coelho * it means that the all connections will be closed automatically 674b7282643SLuca Coelho * by mac80211 before the platform is suspended. 675b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 676b7282643SLuca Coelho * For runtime power management, this mode is not officially 677b7282643SLuca Coelho * supported. 678b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_D0I3: the device goes into D0I3 mode. 679b7282643SLuca Coelho */ 680b7282643SLuca Coelho enum iwl_plat_pm_mode { 681b7282643SLuca Coelho IWL_PLAT_PM_MODE_DISABLED, 682b7282643SLuca Coelho IWL_PLAT_PM_MODE_D3, 683b7282643SLuca Coelho IWL_PLAT_PM_MODE_D0I3, 684e705c121SKalle Valo }; 685e705c121SKalle Valo 6864cbb8e50SLuciano Coelho /* Max time to wait for trans to become idle/non-idle on d0i3 6874cbb8e50SLuciano Coelho * enter/exit (in msecs). 6884cbb8e50SLuciano Coelho */ 6894cbb8e50SLuciano Coelho #define IWL_TRANS_IDLE_TIMEOUT 2000 69088964b2eSSara Sharon 691b8a7547dSShahar S Matityahu /* Max time to wait for nmi interrupt */ 692b8a7547dSShahar S Matityahu #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 693b8a7547dSShahar S Matityahu 69488964b2eSSara Sharon /** 69588964b2eSSara Sharon * struct iwl_dram_data 69688964b2eSSara Sharon * @physical: page phy pointer 69788964b2eSSara Sharon * @block: pointer to the allocated block/page 69888964b2eSSara Sharon * @size: size of the block/page 69988964b2eSSara Sharon */ 70088964b2eSSara Sharon struct iwl_dram_data { 70188964b2eSSara Sharon dma_addr_t physical; 70288964b2eSSara Sharon void *block; 70388964b2eSSara Sharon int size; 70488964b2eSSara Sharon }; 7054cbb8e50SLuciano Coelho 706e705c121SKalle Valo /** 707505a00c0SShahar S Matityahu * struct iwl_self_init_dram - dram data used by self init process 708505a00c0SShahar S Matityahu * @fw: lmac and umac dram data 709505a00c0SShahar S Matityahu * @fw_cnt: total number of items in array 710505a00c0SShahar S Matityahu * @paging: paging dram data 711505a00c0SShahar S Matityahu * @paging_cnt: total number of items in array 712505a00c0SShahar S Matityahu */ 713505a00c0SShahar S Matityahu struct iwl_self_init_dram { 714505a00c0SShahar S Matityahu struct iwl_dram_data *fw; 715505a00c0SShahar S Matityahu int fw_cnt; 716505a00c0SShahar S Matityahu struct iwl_dram_data *paging; 717505a00c0SShahar S Matityahu int paging_cnt; 718505a00c0SShahar S Matityahu }; 719505a00c0SShahar S Matityahu 720505a00c0SShahar S Matityahu /** 721e705c121SKalle Valo * struct iwl_trans - transport common data 722e705c121SKalle Valo * 723e705c121SKalle Valo * @ops - pointer to iwl_trans_ops 724e705c121SKalle Valo * @op_mode - pointer to the op_mode 725e705c121SKalle Valo * @cfg - pointer to the configuration 7266f482e37SSara Sharon * @drv - pointer to iwl_drv 727e705c121SKalle Valo * @status: a bit-mask of transport status flags 728e705c121SKalle Valo * @dev - pointer to struct device * that represents the device 729e705c121SKalle Valo * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 730e705c121SKalle Valo * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 7311afb0ae4SHaim Dreyfuss * @hw_rf_id a u32 with the device RF ID 732e705c121SKalle Valo * @hw_id: a u32 with the ID of the device / sub-device. 733e705c121SKalle Valo * Set during transport allocation. 734e705c121SKalle Valo * @hw_id_str: a string with info about HW ID. Set during transport allocation. 735e705c121SKalle Valo * @pm_support: set to true in start_hw if link pm is supported 736e705c121SKalle Valo * @ltr_enabled: set to true if the LTR is enabled 7375b88792cSSara Sharon * @wide_cmd_header: true when ucode supports wide command header format 738e705c121SKalle Valo * @num_rx_queues: number of RX queues allocated by the transport; 739e705c121SKalle Valo * the transport must set this before calling iwl_drv_start() 740132db31cSGolan Ben-Ami * @iml_len: the length of the image loader 741132db31cSGolan Ben-Ami * @iml: a pointer to the image loader itself 742e705c121SKalle Valo * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 743e705c121SKalle Valo * The user should use iwl_trans_{alloc,free}_tx_cmd. 744e705c121SKalle Valo * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 745e705c121SKalle Valo * starting the firmware, used for tracing 746e705c121SKalle Valo * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 747e705c121SKalle Valo * start of the 802.11 header in the @rx_mpdu_cmd 748e705c121SKalle Valo * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 749e705c121SKalle Valo * @dbg_dest_tlv: points to the destination TLV for debug 750e705c121SKalle Valo * @dbg_conf_tlv: array of pointers to configuration TLVs for debug 751e705c121SKalle Valo * @dbg_trigger_tlv: array of pointers to triggers TLVs for debug 75217b809c9SSara Sharon * @dbg_n_dest_reg: num of reg_ops in %dbg_dest_tlv 75388964b2eSSara Sharon * @num_blocks: number of blocks in fw_mon 75488964b2eSSara Sharon * @fw_mon: address of the buffers for firmware monitor 755b7282643SLuca Coelho * @system_pm_mode: the system-wide power management mode in use. 756b7282643SLuca Coelho * This mode is set dynamically, depending on the WoWLAN values 757b7282643SLuca Coelho * configured from the userspace at runtime. 758b7282643SLuca Coelho * @runtime_pm_mode: the runtime power management mode in use. This 759b7282643SLuca Coelho * mode is set during the initialization phase and is not 760b7282643SLuca Coelho * supposed to change during runtime. 761f7805b33SLior Cohen * @dbg_rec_on: true iff there is a fw debug recording currently active 762e705c121SKalle Valo */ 763e705c121SKalle Valo struct iwl_trans { 764e705c121SKalle Valo const struct iwl_trans_ops *ops; 765e705c121SKalle Valo struct iwl_op_mode *op_mode; 766e705c121SKalle Valo const struct iwl_cfg *cfg; 7676f482e37SSara Sharon struct iwl_drv *drv; 768e705c121SKalle Valo enum iwl_trans_state state; 769e705c121SKalle Valo unsigned long status; 770e705c121SKalle Valo 771e705c121SKalle Valo struct device *dev; 772e705c121SKalle Valo u32 max_skb_frags; 773e705c121SKalle Valo u32 hw_rev; 7741afb0ae4SHaim Dreyfuss u32 hw_rf_id; 775e705c121SKalle Valo u32 hw_id; 776e705c121SKalle Valo char hw_id_str[52]; 777e705c121SKalle Valo 778e705c121SKalle Valo u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 779e705c121SKalle Valo 780e705c121SKalle Valo bool pm_support; 781e705c121SKalle Valo bool ltr_enabled; 782e705c121SKalle Valo 78339bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 78439bdb17eSSharon Dvir int command_groups_size; 7855b88792cSSara Sharon bool wide_cmd_header; 78639bdb17eSSharon Dvir 787e705c121SKalle Valo u8 num_rx_queues; 788e705c121SKalle Valo 789132db31cSGolan Ben-Ami size_t iml_len; 790132db31cSGolan Ben-Ami u8 *iml; 791132db31cSGolan Ben-Ami 792e705c121SKalle Valo /* The following fields are internal only */ 793e705c121SKalle Valo struct kmem_cache *dev_cmd_pool; 794e705c121SKalle Valo char dev_cmd_pool_name[50]; 795e705c121SKalle Valo 796e705c121SKalle Valo struct dentry *dbgfs_dir; 797e705c121SKalle Valo 798e705c121SKalle Valo #ifdef CONFIG_LOCKDEP 799e705c121SKalle Valo struct lockdep_map sync_cmd_lockdep_map; 800e705c121SKalle Valo #endif 801e705c121SKalle Valo 802f14cda6fSSara Sharon struct iwl_apply_point_data apply_points[IWL_FW_INI_APPLY_NUM]; 80368f6f492SSara Sharon struct iwl_apply_point_data apply_points_ext[IWL_FW_INI_APPLY_NUM]; 80468f6f492SSara Sharon 80568f6f492SSara Sharon bool external_ini_loaded; 80674374223SSara Sharon bool ini_valid; 807f14cda6fSSara Sharon 808fd527eb5SGolan Ben Ami const struct iwl_fw_dbg_dest_tlv_v1 *dbg_dest_tlv; 809e705c121SKalle Valo const struct iwl_fw_dbg_conf_tlv *dbg_conf_tlv[FW_DBG_CONF_MAX]; 810e705c121SKalle Valo struct iwl_fw_dbg_trigger_tlv * const *dbg_trigger_tlv; 81117b809c9SSara Sharon u8 dbg_n_dest_reg; 81288964b2eSSara Sharon int num_blocks; 813d47902f9SSara Sharon struct iwl_dram_data fw_mon[IWL_FW_INI_APPLY_NUM]; 814505a00c0SShahar S Matityahu struct iwl_self_init_dram init_dram; 815e705c121SKalle Valo 816b7282643SLuca Coelho enum iwl_plat_pm_mode system_pm_mode; 817b7282643SLuca Coelho enum iwl_plat_pm_mode runtime_pm_mode; 818863eac30SLuca Coelho bool suspending; 819f7805b33SLior Cohen bool dbg_rec_on; 820e705c121SKalle Valo 821700b3799SShahar S Matityahu u32 lmac_error_event_table[2]; 822700b3799SShahar S Matityahu u32 umac_error_event_table; 823700b3799SShahar S Matityahu unsigned int error_event_table_tlv_status; 824700b3799SShahar S Matityahu wait_queue_head_t fw_halt_waitq; 825700b3799SShahar S Matityahu 826e705c121SKalle Valo /* pointer to trans specific struct */ 827e705c121SKalle Valo /*Ensure that this pointer will always be aligned to sizeof pointer */ 828e705c121SKalle Valo char trans_specific[0] __aligned(sizeof(void *)); 829e705c121SKalle Valo }; 830e705c121SKalle Valo 83139bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 83239bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 83339bdb17eSSharon Dvir 834e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans, 835e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 836e705c121SKalle Valo { 837e705c121SKalle Valo trans->op_mode = trans_cfg->op_mode; 838e705c121SKalle Valo 839e705c121SKalle Valo trans->ops->configure(trans, trans_cfg); 84039bdb17eSSharon Dvir WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 841e705c121SKalle Valo } 842e705c121SKalle Valo 843e705c121SKalle Valo static inline int _iwl_trans_start_hw(struct iwl_trans *trans, bool low_power) 844e705c121SKalle Valo { 845e705c121SKalle Valo might_sleep(); 846e705c121SKalle Valo 847e705c121SKalle Valo return trans->ops->start_hw(trans, low_power); 848e705c121SKalle Valo } 849e705c121SKalle Valo 850e705c121SKalle Valo static inline int iwl_trans_start_hw(struct iwl_trans *trans) 851e705c121SKalle Valo { 852e705c121SKalle Valo return trans->ops->start_hw(trans, true); 853e705c121SKalle Valo } 854e705c121SKalle Valo 855e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 856e705c121SKalle Valo { 857e705c121SKalle Valo might_sleep(); 858e705c121SKalle Valo 859e705c121SKalle Valo if (trans->ops->op_mode_leave) 860e705c121SKalle Valo trans->ops->op_mode_leave(trans); 861e705c121SKalle Valo 862e705c121SKalle Valo trans->op_mode = NULL; 863e705c121SKalle Valo 864e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 865e705c121SKalle Valo } 866e705c121SKalle Valo 867e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 868e705c121SKalle Valo { 869e705c121SKalle Valo might_sleep(); 870e705c121SKalle Valo 871e705c121SKalle Valo trans->state = IWL_TRANS_FW_ALIVE; 872e705c121SKalle Valo 873e705c121SKalle Valo trans->ops->fw_alive(trans, scd_addr); 874e705c121SKalle Valo } 875e705c121SKalle Valo 876e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans, 877e705c121SKalle Valo const struct fw_img *fw, 878e705c121SKalle Valo bool run_in_rfkill) 879e705c121SKalle Valo { 880e705c121SKalle Valo might_sleep(); 881e705c121SKalle Valo 882e705c121SKalle Valo WARN_ON_ONCE(!trans->rx_mpdu_cmd); 883e705c121SKalle Valo 884e705c121SKalle Valo clear_bit(STATUS_FW_ERROR, &trans->status); 885e705c121SKalle Valo return trans->ops->start_fw(trans, fw, run_in_rfkill); 886e705c121SKalle Valo } 887e705c121SKalle Valo 888e705c121SKalle Valo static inline void _iwl_trans_stop_device(struct iwl_trans *trans, 889e705c121SKalle Valo bool low_power) 890e705c121SKalle Valo { 891e705c121SKalle Valo might_sleep(); 892e705c121SKalle Valo 893e705c121SKalle Valo trans->ops->stop_device(trans, low_power); 894e705c121SKalle Valo 895e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 896e705c121SKalle Valo } 897e705c121SKalle Valo 898e705c121SKalle Valo static inline void iwl_trans_stop_device(struct iwl_trans *trans) 899e705c121SKalle Valo { 900e705c121SKalle Valo _iwl_trans_stop_device(trans, true); 901e705c121SKalle Valo } 902e705c121SKalle Valo 90323ae6128SMatti Gottlieb static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 90423ae6128SMatti Gottlieb bool reset) 905e705c121SKalle Valo { 906e705c121SKalle Valo might_sleep(); 907e705c121SKalle Valo if (trans->ops->d3_suspend) 90823ae6128SMatti Gottlieb trans->ops->d3_suspend(trans, test, reset); 909e705c121SKalle Valo } 910e705c121SKalle Valo 911e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 912e705c121SKalle Valo enum iwl_d3_status *status, 91323ae6128SMatti Gottlieb bool test, bool reset) 914e705c121SKalle Valo { 915e705c121SKalle Valo might_sleep(); 916e705c121SKalle Valo if (!trans->ops->d3_resume) 917e705c121SKalle Valo return 0; 918e705c121SKalle Valo 91923ae6128SMatti Gottlieb return trans->ops->d3_resume(trans, status, test, reset); 920e705c121SKalle Valo } 921e705c121SKalle Valo 922e705c121SKalle Valo static inline int iwl_trans_suspend(struct iwl_trans *trans) 923e705c121SKalle Valo { 924e705c121SKalle Valo if (!trans->ops->suspend) 925e705c121SKalle Valo return 0; 926e705c121SKalle Valo 927e705c121SKalle Valo return trans->ops->suspend(trans); 928e705c121SKalle Valo } 929e705c121SKalle Valo 930e705c121SKalle Valo static inline void iwl_trans_resume(struct iwl_trans *trans) 931e705c121SKalle Valo { 932e705c121SKalle Valo if (trans->ops->resume) 933e705c121SKalle Valo trans->ops->resume(trans); 934e705c121SKalle Valo } 935e705c121SKalle Valo 936e705c121SKalle Valo static inline struct iwl_trans_dump_data * 93779f033f6SSara Sharon iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask) 938e705c121SKalle Valo { 939e705c121SKalle Valo if (!trans->ops->dump_data) 940e705c121SKalle Valo return NULL; 94179f033f6SSara Sharon return trans->ops->dump_data(trans, dump_mask); 942e705c121SKalle Valo } 943e705c121SKalle Valo 944e705c121SKalle Valo static inline struct iwl_device_cmd * 945e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 946e705c121SKalle Valo { 9470ae0bb3fSLuca Coelho return kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC); 948e705c121SKalle Valo } 949e705c121SKalle Valo 95092fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 95192fe8343SEmmanuel Grumbach 952e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 953e705c121SKalle Valo struct iwl_device_cmd *dev_cmd) 954e705c121SKalle Valo { 9551ea423b0SLuca Coelho kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 956e705c121SKalle Valo } 957e705c121SKalle Valo 958e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 959e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int queue) 960e705c121SKalle Valo { 961e705c121SKalle Valo if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 962e705c121SKalle Valo return -EIO; 963e705c121SKalle Valo 964e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 965e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 966e5d15cb5SEliad Peller return -EIO; 967e5d15cb5SEliad Peller } 968e705c121SKalle Valo 969e705c121SKalle Valo return trans->ops->tx(trans, skb, dev_cmd, queue); 970e705c121SKalle Valo } 971e705c121SKalle Valo 972e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 973e705c121SKalle Valo int ssn, struct sk_buff_head *skbs) 974e705c121SKalle Valo { 975e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 976e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 977e5d15cb5SEliad Peller return; 978e5d15cb5SEliad Peller } 979e705c121SKalle Valo 980e705c121SKalle Valo trans->ops->reclaim(trans, queue, ssn, skbs); 981e705c121SKalle Valo } 982e705c121SKalle Valo 983e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 984e705c121SKalle Valo bool configure_scd) 985e705c121SKalle Valo { 986e705c121SKalle Valo trans->ops->txq_disable(trans, queue, configure_scd); 987e705c121SKalle Valo } 988e705c121SKalle Valo 989dcfbd67bSEmmanuel Grumbach static inline bool 990e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 991e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 992e705c121SKalle Valo unsigned int queue_wdg_timeout) 993e705c121SKalle Valo { 994e705c121SKalle Valo might_sleep(); 995e705c121SKalle Valo 996e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 997e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 998dcfbd67bSEmmanuel Grumbach return false; 999e5d15cb5SEliad Peller } 1000e705c121SKalle Valo 1001dcfbd67bSEmmanuel Grumbach return trans->ops->txq_enable(trans, queue, ssn, 1002dcfbd67bSEmmanuel Grumbach cfg, queue_wdg_timeout); 1003e705c121SKalle Valo } 1004e705c121SKalle Valo 100592536c96SSara Sharon static inline int 100692536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 100792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 100892536c96SSara Sharon { 100992536c96SSara Sharon if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 101092536c96SSara Sharon return -ENOTSUPP; 101192536c96SSara Sharon 101292536c96SSara Sharon return trans->ops->rxq_dma_data(trans, queue, data); 101392536c96SSara Sharon } 101492536c96SSara Sharon 10156b35ff91SSara Sharon static inline void 10166b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue) 10176b35ff91SSara Sharon { 10186b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_free)) 10196b35ff91SSara Sharon return; 10206b35ff91SSara Sharon 10216b35ff91SSara Sharon trans->ops->txq_free(trans, queue); 10226b35ff91SSara Sharon } 10236b35ff91SSara Sharon 10246b35ff91SSara Sharon static inline int 10256b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans, 10261169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 10275369774cSSara Sharon int cmd_id, int size, 10285369774cSSara Sharon unsigned int wdg_timeout) 10296b35ff91SSara Sharon { 10306b35ff91SSara Sharon might_sleep(); 10316b35ff91SSara Sharon 10326b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 10336b35ff91SSara Sharon return -ENOTSUPP; 10346b35ff91SSara Sharon 10356b35ff91SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 10366b35ff91SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 10376b35ff91SSara Sharon return -EIO; 10386b35ff91SSara Sharon } 10396b35ff91SSara Sharon 10401169310fSGolan Ben Ami return trans->ops->txq_alloc(trans, flags, sta_id, tid, 10411169310fSGolan Ben Ami cmd_id, size, wdg_timeout); 10426b35ff91SSara Sharon } 10436b35ff91SSara Sharon 104442db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 104542db09c1SLiad Kaufman int queue, bool shared_mode) 104642db09c1SLiad Kaufman { 104742db09c1SLiad Kaufman if (trans->ops->txq_set_shared_mode) 104842db09c1SLiad Kaufman trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 104942db09c1SLiad Kaufman } 105042db09c1SLiad Kaufman 1051e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1052e705c121SKalle Valo int fifo, int sta_id, int tid, 1053e705c121SKalle Valo int frame_limit, u16 ssn, 1054e705c121SKalle Valo unsigned int queue_wdg_timeout) 1055e705c121SKalle Valo { 1056e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1057e705c121SKalle Valo .fifo = fifo, 1058e705c121SKalle Valo .sta_id = sta_id, 1059e705c121SKalle Valo .tid = tid, 1060e705c121SKalle Valo .frame_limit = frame_limit, 1061e705c121SKalle Valo .aggregate = sta_id >= 0, 1062e705c121SKalle Valo }; 1063e705c121SKalle Valo 1064e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1065e705c121SKalle Valo } 1066e705c121SKalle Valo 1067e705c121SKalle Valo static inline 1068e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1069e705c121SKalle Valo unsigned int queue_wdg_timeout) 1070e705c121SKalle Valo { 1071e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1072e705c121SKalle Valo .fifo = fifo, 1073e705c121SKalle Valo .sta_id = -1, 1074e705c121SKalle Valo .tid = IWL_MAX_TID_COUNT, 1075e705c121SKalle Valo .frame_limit = IWL_FRAME_LIMIT, 1076e705c121SKalle Valo .aggregate = false, 1077e705c121SKalle Valo }; 1078e705c121SKalle Valo 1079e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1080e705c121SKalle Valo } 1081e705c121SKalle Valo 1082e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1083e705c121SKalle Valo unsigned long txqs, 1084e705c121SKalle Valo bool freeze) 1085e705c121SKalle Valo { 1086e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1087e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1088e5d15cb5SEliad Peller return; 1089e5d15cb5SEliad Peller } 1090e705c121SKalle Valo 1091e705c121SKalle Valo if (trans->ops->freeze_txq_timer) 1092e705c121SKalle Valo trans->ops->freeze_txq_timer(trans, txqs, freeze); 1093e705c121SKalle Valo } 1094e705c121SKalle Valo 10950cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 10960cd58eaaSEmmanuel Grumbach bool block) 10970cd58eaaSEmmanuel Grumbach { 1098e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 10990cd58eaaSEmmanuel Grumbach IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1100e5d15cb5SEliad Peller return; 1101e5d15cb5SEliad Peller } 11020cd58eaaSEmmanuel Grumbach 11030cd58eaaSEmmanuel Grumbach if (trans->ops->block_txq_ptrs) 11040cd58eaaSEmmanuel Grumbach trans->ops->block_txq_ptrs(trans, block); 11050cd58eaaSEmmanuel Grumbach } 11060cd58eaaSEmmanuel Grumbach 1107a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1108e705c121SKalle Valo u32 txqs) 1109e705c121SKalle Valo { 1110d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1111d6d517b7SSara Sharon return -ENOTSUPP; 1112d6d517b7SSara Sharon 1113e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1114e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1115e5d15cb5SEliad Peller return -EIO; 1116e5d15cb5SEliad Peller } 1117e705c121SKalle Valo 1118a1a57877SSara Sharon return trans->ops->wait_tx_queues_empty(trans, txqs); 1119e705c121SKalle Valo } 1120e705c121SKalle Valo 1121d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1122d6d517b7SSara Sharon { 1123d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1124d6d517b7SSara Sharon return -ENOTSUPP; 1125d6d517b7SSara Sharon 1126d6d517b7SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1127d6d517b7SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1128d6d517b7SSara Sharon return -EIO; 1129d6d517b7SSara Sharon } 1130d6d517b7SSara Sharon 1131d6d517b7SSara Sharon return trans->ops->wait_txq_empty(trans, queue); 1132d6d517b7SSara Sharon } 1133d6d517b7SSara Sharon 1134e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1135e705c121SKalle Valo { 1136e705c121SKalle Valo trans->ops->write8(trans, ofs, val); 1137e705c121SKalle Valo } 1138e705c121SKalle Valo 1139e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1140e705c121SKalle Valo { 1141e705c121SKalle Valo trans->ops->write32(trans, ofs, val); 1142e705c121SKalle Valo } 1143e705c121SKalle Valo 1144e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1145e705c121SKalle Valo { 1146e705c121SKalle Valo return trans->ops->read32(trans, ofs); 1147e705c121SKalle Valo } 1148e705c121SKalle Valo 1149e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1150e705c121SKalle Valo { 1151e705c121SKalle Valo return trans->ops->read_prph(trans, ofs); 1152e705c121SKalle Valo } 1153e705c121SKalle Valo 1154e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1155e705c121SKalle Valo u32 val) 1156e705c121SKalle Valo { 1157e705c121SKalle Valo return trans->ops->write_prph(trans, ofs, val); 1158e705c121SKalle Valo } 1159e705c121SKalle Valo 1160e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1161e705c121SKalle Valo void *buf, int dwords) 1162e705c121SKalle Valo { 1163e705c121SKalle Valo return trans->ops->read_mem(trans, addr, buf, dwords); 1164e705c121SKalle Valo } 1165e705c121SKalle Valo 1166e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1167e705c121SKalle Valo do { \ 1168e705c121SKalle Valo if (__builtin_constant_p(bufsize)) \ 1169e705c121SKalle Valo BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1170e705c121SKalle Valo iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1171e705c121SKalle Valo } while (0) 1172e705c121SKalle Valo 1173e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1174e705c121SKalle Valo { 1175e705c121SKalle Valo u32 value; 1176e705c121SKalle Valo 1177e705c121SKalle Valo if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1178e705c121SKalle Valo return 0xa5a5a5a5; 1179e705c121SKalle Valo 1180e705c121SKalle Valo return value; 1181e705c121SKalle Valo } 1182e705c121SKalle Valo 1183e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1184e705c121SKalle Valo const void *buf, int dwords) 1185e705c121SKalle Valo { 1186e705c121SKalle Valo return trans->ops->write_mem(trans, addr, buf, dwords); 1187e705c121SKalle Valo } 1188e705c121SKalle Valo 1189e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1190e705c121SKalle Valo u32 val) 1191e705c121SKalle Valo { 1192e705c121SKalle Valo return iwl_trans_write_mem(trans, addr, &val, 1); 1193e705c121SKalle Valo } 1194e705c121SKalle Valo 1195e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1196e705c121SKalle Valo { 1197e705c121SKalle Valo if (trans->ops->set_pmi) 1198e705c121SKalle Valo trans->ops->set_pmi(trans, state); 1199e705c121SKalle Valo } 1200e705c121SKalle Valo 1201870c2a11SGolan Ben Ami static inline void iwl_trans_sw_reset(struct iwl_trans *trans) 1202870c2a11SGolan Ben Ami { 1203870c2a11SGolan Ben Ami if (trans->ops->sw_reset) 1204870c2a11SGolan Ben Ami trans->ops->sw_reset(trans); 1205870c2a11SGolan Ben Ami } 1206870c2a11SGolan Ben Ami 1207e705c121SKalle Valo static inline void 1208e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1209e705c121SKalle Valo { 1210e705c121SKalle Valo trans->ops->set_bits_mask(trans, reg, mask, value); 1211e705c121SKalle Valo } 1212e705c121SKalle Valo 121323ba9340SEmmanuel Grumbach #define iwl_trans_grab_nic_access(trans, flags) \ 1214e705c121SKalle Valo __cond_lock(nic_access, \ 121523ba9340SEmmanuel Grumbach likely((trans)->ops->grab_nic_access(trans, flags))) 1216e705c121SKalle Valo 1217e705c121SKalle Valo static inline void __releases(nic_access) 1218e705c121SKalle Valo iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) 1219e705c121SKalle Valo { 1220e705c121SKalle Valo trans->ops->release_nic_access(trans, flags); 1221e705c121SKalle Valo __release(nic_access); 1222e705c121SKalle Valo } 1223e705c121SKalle Valo 1224e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans) 1225e705c121SKalle Valo { 1226e705c121SKalle Valo if (WARN_ON_ONCE(!trans->op_mode)) 1227e705c121SKalle Valo return; 1228e705c121SKalle Valo 1229e705c121SKalle Valo /* prevent double restarts due to the same erroneous FW */ 1230e705c121SKalle Valo if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) 1231e705c121SKalle Valo iwl_op_mode_nic_error(trans->op_mode); 1232700b3799SShahar S Matityahu 1233700b3799SShahar S Matityahu if (test_and_clear_bit(STATUS_FW_WAIT_DUMP, &trans->status)) 1234700b3799SShahar S Matityahu wake_up(&trans->fw_halt_waitq); 1235700b3799SShahar S Matityahu 1236e705c121SKalle Valo } 1237e705c121SKalle Valo 1238e705c121SKalle Valo /***************************************************** 1239e705c121SKalle Valo * transport helper functions 1240e705c121SKalle Valo *****************************************************/ 1241e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1242e705c121SKalle Valo struct device *dev, 1243e705c121SKalle Valo const struct iwl_cfg *cfg, 12441ea423b0SLuca Coelho const struct iwl_trans_ops *ops); 1245e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans); 1246d621d3c7SLuca Coelho void iwl_trans_ref(struct iwl_trans *trans); 1247d621d3c7SLuca Coelho void iwl_trans_unref(struct iwl_trans *trans); 1248e705c121SKalle Valo 1249e705c121SKalle Valo /***************************************************** 1250e705c121SKalle Valo * driver (transport) register/unregister functions 1251e705c121SKalle Valo ******************************************************/ 1252e705c121SKalle Valo int __must_check iwl_pci_register_driver(void); 1253e705c121SKalle Valo void iwl_pci_unregister_driver(void); 1254e705c121SKalle Valo 1255e705c121SKalle Valo #endif /* __iwl_trans_h__ */ 1256