1e705c121SKalle Valo /******************************************************************************
2e705c121SKalle Valo  *
3e705c121SKalle Valo  * This file is provided under a dual BSD/GPLv2 license.  When using or
4e705c121SKalle Valo  * redistributing this file, you may do so under either license.
5e705c121SKalle Valo  *
6e705c121SKalle Valo  * GPL LICENSE SUMMARY
7e705c121SKalle Valo  *
8e705c121SKalle Valo  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10e705c121SKalle Valo  *
11e705c121SKalle Valo  * This program is free software; you can redistribute it and/or modify
12e705c121SKalle Valo  * it under the terms of version 2 of the GNU General Public License as
13e705c121SKalle Valo  * published by the Free Software Foundation.
14e705c121SKalle Valo  *
15e705c121SKalle Valo  * This program is distributed in the hope that it will be useful, but
16e705c121SKalle Valo  * WITHOUT ANY WARRANTY; without even the implied warranty of
17e705c121SKalle Valo  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18e705c121SKalle Valo  * General Public License for more details.
19e705c121SKalle Valo  *
20e705c121SKalle Valo  * You should have received a copy of the GNU General Public License
21e705c121SKalle Valo  * along with this program; if not, write to the Free Software
22e705c121SKalle Valo  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23e705c121SKalle Valo  * USA
24e705c121SKalle Valo  *
25e705c121SKalle Valo  * The full GNU General Public License is included in this distribution
26e705c121SKalle Valo  * in the file called COPYING.
27e705c121SKalle Valo  *
28e705c121SKalle Valo  * Contact Information:
29e705c121SKalle Valo  *  Intel Linux Wireless <ilw@linux.intel.com>
30e705c121SKalle Valo  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31e705c121SKalle Valo  *
32e705c121SKalle Valo  * BSD LICENSE
33e705c121SKalle Valo  *
34e705c121SKalle Valo  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
36e705c121SKalle Valo  * All rights reserved.
37e705c121SKalle Valo  *
38e705c121SKalle Valo  * Redistribution and use in source and binary forms, with or without
39e705c121SKalle Valo  * modification, are permitted provided that the following conditions
40e705c121SKalle Valo  * are met:
41e705c121SKalle Valo  *
42e705c121SKalle Valo  *  * Redistributions of source code must retain the above copyright
43e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer.
44e705c121SKalle Valo  *  * Redistributions in binary form must reproduce the above copyright
45e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer in
46e705c121SKalle Valo  *    the documentation and/or other materials provided with the
47e705c121SKalle Valo  *    distribution.
48e705c121SKalle Valo  *  * Neither the name Intel Corporation nor the names of its
49e705c121SKalle Valo  *    contributors may be used to endorse or promote products derived
50e705c121SKalle Valo  *    from this software without specific prior written permission.
51e705c121SKalle Valo  *
52e705c121SKalle Valo  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53e705c121SKalle Valo  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54e705c121SKalle Valo  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55e705c121SKalle Valo  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56e705c121SKalle Valo  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57e705c121SKalle Valo  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58e705c121SKalle Valo  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59e705c121SKalle Valo  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60e705c121SKalle Valo  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61e705c121SKalle Valo  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62e705c121SKalle Valo  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63e705c121SKalle Valo  *
64e705c121SKalle Valo  *****************************************************************************/
65e705c121SKalle Valo #ifndef __iwl_trans_h__
66e705c121SKalle Valo #define __iwl_trans_h__
67e705c121SKalle Valo 
68e705c121SKalle Valo #include <linux/ieee80211.h>
69e705c121SKalle Valo #include <linux/mm.h> /* for page_address */
70e705c121SKalle Valo #include <linux/lockdep.h>
7139bdb17eSSharon Dvir #include <linux/kernel.h>
72e705c121SKalle Valo 
73e705c121SKalle Valo #include "iwl-debug.h"
74e705c121SKalle Valo #include "iwl-config.h"
75e705c121SKalle Valo #include "iwl-fw.h"
76e705c121SKalle Valo #include "iwl-op-mode.h"
77e705c121SKalle Valo 
78e705c121SKalle Valo /**
79e705c121SKalle Valo  * DOC: Transport layer - what is it ?
80e705c121SKalle Valo  *
81e705c121SKalle Valo  * The transport layer is the layer that deals with the HW directly. It provides
82e705c121SKalle Valo  * an abstraction of the underlying HW to the upper layer. The transport layer
83e705c121SKalle Valo  * doesn't provide any policy, algorithm or anything of this kind, but only
84e705c121SKalle Valo  * mechanisms to make the HW do something. It is not completely stateless but
85e705c121SKalle Valo  * close to it.
86e705c121SKalle Valo  * We will have an implementation for each different supported bus.
87e705c121SKalle Valo  */
88e705c121SKalle Valo 
89e705c121SKalle Valo /**
90e705c121SKalle Valo  * DOC: Life cycle of the transport layer
91e705c121SKalle Valo  *
92e705c121SKalle Valo  * The transport layer has a very precise life cycle.
93e705c121SKalle Valo  *
94e705c121SKalle Valo  *	1) A helper function is called during the module initialization and
95e705c121SKalle Valo  *	   registers the bus driver's ops with the transport's alloc function.
96e705c121SKalle Valo  *	2) Bus's probe calls to the transport layer's allocation functions.
97e705c121SKalle Valo  *	   Of course this function is bus specific.
98e705c121SKalle Valo  *	3) This allocation functions will spawn the upper layer which will
99e705c121SKalle Valo  *	   register mac80211.
100e705c121SKalle Valo  *
101e705c121SKalle Valo  *	4) At some point (i.e. mac80211's start call), the op_mode will call
102e705c121SKalle Valo  *	   the following sequence:
103e705c121SKalle Valo  *	   start_hw
104e705c121SKalle Valo  *	   start_fw
105e705c121SKalle Valo  *
106e705c121SKalle Valo  *	5) Then when finished (or reset):
107e705c121SKalle Valo  *	   stop_device
108e705c121SKalle Valo  *
109e705c121SKalle Valo  *	6) Eventually, the free function will be called.
110e705c121SKalle Valo  */
111e705c121SKalle Valo 
112e705c121SKalle Valo /**
113e705c121SKalle Valo  * DOC: Host command section
114e705c121SKalle Valo  *
115e705c121SKalle Valo  * A host command is a command issued by the upper layer to the fw. There are
116e705c121SKalle Valo  * several versions of fw that have several APIs. The transport layer is
117e705c121SKalle Valo  * completely agnostic to these differences.
118e705c121SKalle Valo  * The transport does provide helper functionality (i.e. SYNC / ASYNC mode),
119e705c121SKalle Valo  */
120e705c121SKalle Valo #define SEQ_TO_QUEUE(s)	(((s) >> 8) & 0x1f)
121e705c121SKalle Valo #define QUEUE_TO_SEQ(q)	(((q) & 0x1f) << 8)
122e705c121SKalle Valo #define SEQ_TO_INDEX(s)	((s) & 0xff)
123e705c121SKalle Valo #define INDEX_TO_SEQ(i)	((i) & 0xff)
124e705c121SKalle Valo #define SEQ_RX_FRAME	cpu_to_le16(0x8000)
125e705c121SKalle Valo 
126e705c121SKalle Valo /*
127e705c121SKalle Valo  * those functions retrieve specific information from
128e705c121SKalle Valo  * the id field in the iwl_host_cmd struct which contains
129e705c121SKalle Valo  * the command id, the group id and the version of the command
130e705c121SKalle Valo  * and vice versa
131e705c121SKalle Valo */
132e705c121SKalle Valo static inline u8 iwl_cmd_opcode(u32 cmdid)
133e705c121SKalle Valo {
134e705c121SKalle Valo 	return cmdid & 0xFF;
135e705c121SKalle Valo }
136e705c121SKalle Valo 
137e705c121SKalle Valo static inline u8 iwl_cmd_groupid(u32 cmdid)
138e705c121SKalle Valo {
139e705c121SKalle Valo 	return ((cmdid & 0xFF00) >> 8);
140e705c121SKalle Valo }
141e705c121SKalle Valo 
142e705c121SKalle Valo static inline u8 iwl_cmd_version(u32 cmdid)
143e705c121SKalle Valo {
144e705c121SKalle Valo 	return ((cmdid & 0xFF0000) >> 16);
145e705c121SKalle Valo }
146e705c121SKalle Valo 
147e705c121SKalle Valo static inline u32 iwl_cmd_id(u8 opcode, u8 groupid, u8 version)
148e705c121SKalle Valo {
149e705c121SKalle Valo 	return opcode + (groupid << 8) + (version << 16);
150e705c121SKalle Valo }
151e705c121SKalle Valo 
152e705c121SKalle Valo /* make u16 wide id out of u8 group and opcode */
153e705c121SKalle Valo #define WIDE_ID(grp, opcode) ((grp << 8) | opcode)
154e705c121SKalle Valo 
155e705c121SKalle Valo /* due to the conversion, this group is special; new groups
156e705c121SKalle Valo  * should be defined in the appropriate fw-api header files
157e705c121SKalle Valo  */
158e705c121SKalle Valo #define IWL_ALWAYS_LONG_GROUP	1
159e705c121SKalle Valo 
160e705c121SKalle Valo /**
161e705c121SKalle Valo  * struct iwl_cmd_header
162e705c121SKalle Valo  *
163e705c121SKalle Valo  * This header format appears in the beginning of each command sent from the
164e705c121SKalle Valo  * driver, and each response/notification received from uCode.
165e705c121SKalle Valo  */
166e705c121SKalle Valo struct iwl_cmd_header {
167e705c121SKalle Valo 	u8 cmd;		/* Command ID:  REPLY_RXON, etc. */
168e705c121SKalle Valo 	u8 group_id;
169e705c121SKalle Valo 	/*
170e705c121SKalle Valo 	 * The driver sets up the sequence number to values of its choosing.
171e705c121SKalle Valo 	 * uCode does not use this value, but passes it back to the driver
172e705c121SKalle Valo 	 * when sending the response to each driver-originated command, so
173e705c121SKalle Valo 	 * the driver can match the response to the command.  Since the values
174e705c121SKalle Valo 	 * don't get used by uCode, the driver may set up an arbitrary format.
175e705c121SKalle Valo 	 *
176e705c121SKalle Valo 	 * There is one exception:  uCode sets bit 15 when it originates
177e705c121SKalle Valo 	 * the response/notification, i.e. when the response/notification
178e705c121SKalle Valo 	 * is not a direct response to a command sent by the driver.  For
179e705c121SKalle Valo 	 * example, uCode issues REPLY_RX when it sends a received frame
180e705c121SKalle Valo 	 * to the driver; it is not a direct response to any driver command.
181e705c121SKalle Valo 	 *
182e705c121SKalle Valo 	 * The Linux driver uses the following format:
183e705c121SKalle Valo 	 *
184e705c121SKalle Valo 	 *  0:7		tfd index - position within TX queue
185e705c121SKalle Valo 	 *  8:12	TX queue id
186e705c121SKalle Valo 	 *  13:14	reserved
187e705c121SKalle Valo 	 *  15		unsolicited RX or uCode-originated notification
188e705c121SKalle Valo 	 */
189e705c121SKalle Valo 	__le16 sequence;
190e705c121SKalle Valo } __packed;
191e705c121SKalle Valo 
192e705c121SKalle Valo /**
193e705c121SKalle Valo  * struct iwl_cmd_header_wide
194e705c121SKalle Valo  *
195e705c121SKalle Valo  * This header format appears in the beginning of each command sent from the
196e705c121SKalle Valo  * driver, and each response/notification received from uCode.
197e705c121SKalle Valo  * this is the wide version that contains more information about the command
198e705c121SKalle Valo  * like length, version and command type
199e705c121SKalle Valo  */
200e705c121SKalle Valo struct iwl_cmd_header_wide {
201e705c121SKalle Valo 	u8 cmd;
202e705c121SKalle Valo 	u8 group_id;
203e705c121SKalle Valo 	__le16 sequence;
204e705c121SKalle Valo 	__le16 length;
205e705c121SKalle Valo 	u8 reserved;
206e705c121SKalle Valo 	u8 version;
207e705c121SKalle Valo } __packed;
208e705c121SKalle Valo 
209e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK		0x00003FFF	/* bits 0-13 */
210e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID		0x55550000
211e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN		0x40
212e705c121SKalle Valo 
213e705c121SKalle Valo struct iwl_rx_packet {
214e705c121SKalle Valo 	/*
215e705c121SKalle Valo 	 * The first 4 bytes of the RX frame header contain both the RX frame
216e705c121SKalle Valo 	 * size and some flags.
217e705c121SKalle Valo 	 * Bit fields:
218e705c121SKalle Valo 	 * 31:    flag flush RB request
219e705c121SKalle Valo 	 * 30:    flag ignore TC (terminal counter) request
220e705c121SKalle Valo 	 * 29:    flag fast IRQ request
221e705c121SKalle Valo 	 * 28-14: Reserved
222e705c121SKalle Valo 	 * 13-00: RX frame size
223e705c121SKalle Valo 	 */
224e705c121SKalle Valo 	__le32 len_n_flags;
225e705c121SKalle Valo 	struct iwl_cmd_header hdr;
226e705c121SKalle Valo 	u8 data[];
227e705c121SKalle Valo } __packed;
228e705c121SKalle Valo 
229e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
230e705c121SKalle Valo {
231e705c121SKalle Valo 	return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
232e705c121SKalle Valo }
233e705c121SKalle Valo 
234e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
235e705c121SKalle Valo {
236e705c121SKalle Valo 	return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
237e705c121SKalle Valo }
238e705c121SKalle Valo 
239e705c121SKalle Valo /**
240e705c121SKalle Valo  * enum CMD_MODE - how to send the host commands ?
241e705c121SKalle Valo  *
242e705c121SKalle Valo  * @CMD_ASYNC: Return right away and don't wait for the response
243e705c121SKalle Valo  * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
244e705c121SKalle Valo  *	the response. The caller needs to call iwl_free_resp when done.
245e705c121SKalle Valo  * @CMD_HIGH_PRIO: The command is high priority - it goes to the front of the
246e705c121SKalle Valo  *	command queue, but after other high priority commands. Valid only
247e705c121SKalle Valo  *	with CMD_ASYNC.
248e705c121SKalle Valo  * @CMD_SEND_IN_IDLE: The command should be sent even when the trans is idle.
249e705c121SKalle Valo  * @CMD_MAKE_TRANS_IDLE: The command response should mark the trans as idle.
250e705c121SKalle Valo  * @CMD_WAKE_UP_TRANS: The command response should wake up the trans
251e705c121SKalle Valo  *	(i.e. mark it as non-idle).
252dcbb4746SEmmanuel Grumbach  * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
253dcbb4746SEmmanuel Grumbach  *	called after this command completes. Valid only with CMD_ASYNC.
254e705c121SKalle Valo  * @CMD_TB_BITMAP_POS: Position of the first bit for the TB bitmap. We need to
255e705c121SKalle Valo  *	check that we leave enough room for the TBs bitmap which needs 20 bits.
256e705c121SKalle Valo  */
257e705c121SKalle Valo enum CMD_MODE {
258e705c121SKalle Valo 	CMD_ASYNC		= BIT(0),
259e705c121SKalle Valo 	CMD_WANT_SKB		= BIT(1),
260e705c121SKalle Valo 	CMD_SEND_IN_RFKILL	= BIT(2),
261e705c121SKalle Valo 	CMD_HIGH_PRIO		= BIT(3),
262e705c121SKalle Valo 	CMD_SEND_IN_IDLE	= BIT(4),
263e705c121SKalle Valo 	CMD_MAKE_TRANS_IDLE	= BIT(5),
264e705c121SKalle Valo 	CMD_WAKE_UP_TRANS	= BIT(6),
265dcbb4746SEmmanuel Grumbach 	CMD_WANT_ASYNC_CALLBACK	= BIT(7),
266e705c121SKalle Valo 
267e705c121SKalle Valo 	CMD_TB_BITMAP_POS	= 11,
268e705c121SKalle Valo };
269e705c121SKalle Valo 
270e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320
271e705c121SKalle Valo 
272e705c121SKalle Valo /**
273e705c121SKalle Valo  * struct iwl_device_cmd
274e705c121SKalle Valo  *
275e705c121SKalle Valo  * For allocation of the command and tx queues, this establishes the overall
276e705c121SKalle Valo  * size of the largest command we send to uCode, except for commands that
277e705c121SKalle Valo  * aren't fully copied and use other TFD space.
278e705c121SKalle Valo  */
279e705c121SKalle Valo struct iwl_device_cmd {
280e705c121SKalle Valo 	union {
281e705c121SKalle Valo 		struct {
282e705c121SKalle Valo 			struct iwl_cmd_header hdr;	/* uCode API */
283e705c121SKalle Valo 			u8 payload[DEF_CMD_PAYLOAD_SIZE];
284e705c121SKalle Valo 		};
285e705c121SKalle Valo 		struct {
286e705c121SKalle Valo 			struct iwl_cmd_header_wide hdr_wide;
287e705c121SKalle Valo 			u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
288e705c121SKalle Valo 					sizeof(struct iwl_cmd_header_wide) +
289e705c121SKalle Valo 					sizeof(struct iwl_cmd_header)];
290e705c121SKalle Valo 		};
291e705c121SKalle Valo 	};
292e705c121SKalle Valo } __packed;
293e705c121SKalle Valo 
294e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
295e705c121SKalle Valo 
296e705c121SKalle Valo /*
297e705c121SKalle Valo  * number of transfer buffers (fragments) per transmit frame descriptor;
298e705c121SKalle Valo  * this is just the driver's idea, the hardware supports 20
299e705c121SKalle Valo  */
300e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD	2
301e705c121SKalle Valo 
302e705c121SKalle Valo /**
303e705c121SKalle Valo  * struct iwl_hcmd_dataflag - flag for each one of the chunks of the command
304e705c121SKalle Valo  *
305e705c121SKalle Valo  * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
306e705c121SKalle Valo  *	ring. The transport layer doesn't map the command's buffer to DMA, but
307e705c121SKalle Valo  *	rather copies it to a previously allocated DMA buffer. This flag tells
308e705c121SKalle Valo  *	the transport layer not to copy the command, but to map the existing
309e705c121SKalle Valo  *	buffer (that is passed in) instead. This saves the memcpy and allows
310e705c121SKalle Valo  *	commands that are bigger than the fixed buffer to be submitted.
311e705c121SKalle Valo  *	Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
312e705c121SKalle Valo  * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
313e705c121SKalle Valo  *	chunk internally and free it again after the command completes. This
314e705c121SKalle Valo  *	can (currently) be used only once per command.
315e705c121SKalle Valo  *	Note that a TFD entry after a DUP one cannot be a normal copied one.
316e705c121SKalle Valo  */
317e705c121SKalle Valo enum iwl_hcmd_dataflag {
318e705c121SKalle Valo 	IWL_HCMD_DFL_NOCOPY	= BIT(0),
319e705c121SKalle Valo 	IWL_HCMD_DFL_DUP	= BIT(1),
320e705c121SKalle Valo };
321e705c121SKalle Valo 
322e705c121SKalle Valo /**
323e705c121SKalle Valo  * struct iwl_host_cmd - Host command to the uCode
324e705c121SKalle Valo  *
325e705c121SKalle Valo  * @data: array of chunks that composes the data of the host command
326e705c121SKalle Valo  * @resp_pkt: response packet, if %CMD_WANT_SKB was set
327e705c121SKalle Valo  * @_rx_page_order: (internally used to free response packet)
328e705c121SKalle Valo  * @_rx_page_addr: (internally used to free response packet)
329e705c121SKalle Valo  * @flags: can be CMD_*
330e705c121SKalle Valo  * @len: array of the lengths of the chunks in data
331e705c121SKalle Valo  * @dataflags: IWL_HCMD_DFL_*
332e705c121SKalle Valo  * @id: command id of the host command, for wide commands encoding the
333e705c121SKalle Valo  *	version and group as well
334e705c121SKalle Valo  */
335e705c121SKalle Valo struct iwl_host_cmd {
336e705c121SKalle Valo 	const void *data[IWL_MAX_CMD_TBS_PER_TFD];
337e705c121SKalle Valo 	struct iwl_rx_packet *resp_pkt;
338e705c121SKalle Valo 	unsigned long _rx_page_addr;
339e705c121SKalle Valo 	u32 _rx_page_order;
340e705c121SKalle Valo 
341e705c121SKalle Valo 	u32 flags;
342e705c121SKalle Valo 	u32 id;
343e705c121SKalle Valo 	u16 len[IWL_MAX_CMD_TBS_PER_TFD];
344e705c121SKalle Valo 	u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
345e705c121SKalle Valo };
346e705c121SKalle Valo 
347e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
348e705c121SKalle Valo {
349e705c121SKalle Valo 	free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
350e705c121SKalle Valo }
351e705c121SKalle Valo 
352e705c121SKalle Valo struct iwl_rx_cmd_buffer {
353e705c121SKalle Valo 	struct page *_page;
354e705c121SKalle Valo 	int _offset;
355e705c121SKalle Valo 	bool _page_stolen;
356e705c121SKalle Valo 	u32 _rx_page_order;
357e705c121SKalle Valo 	unsigned int truesize;
358e705c121SKalle Valo };
359e705c121SKalle Valo 
360e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
361e705c121SKalle Valo {
362e705c121SKalle Valo 	return (void *)((unsigned long)page_address(r->_page) + r->_offset);
363e705c121SKalle Valo }
364e705c121SKalle Valo 
365e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
366e705c121SKalle Valo {
367e705c121SKalle Valo 	return r->_offset;
368e705c121SKalle Valo }
369e705c121SKalle Valo 
370e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
371e705c121SKalle Valo {
372e705c121SKalle Valo 	r->_page_stolen = true;
373e705c121SKalle Valo 	get_page(r->_page);
374e705c121SKalle Valo 	return r->_page;
375e705c121SKalle Valo }
376e705c121SKalle Valo 
377e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
378e705c121SKalle Valo {
379e705c121SKalle Valo 	__free_pages(r->_page, r->_rx_page_order);
380e705c121SKalle Valo }
381e705c121SKalle Valo 
382e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS	6
383e705c121SKalle Valo 
384e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
385e705c121SKalle Valo 
386e705c121SKalle Valo /*
387e705c121SKalle Valo  * Maximum number of HW queues the transport layer
388e705c121SKalle Valo  * currently supports
389e705c121SKalle Valo  */
390e705c121SKalle Valo #define IWL_MAX_HW_QUEUES		32
391e705c121SKalle Valo #define IWL_MAX_TID_COUNT	8
392e705c121SKalle Valo #define IWL_FRAME_LIMIT	64
393e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES	16
394e705c121SKalle Valo 
395e705c121SKalle Valo /**
396e705c121SKalle Valo  * enum iwl_wowlan_status - WoWLAN image/device status
397e705c121SKalle Valo  * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
398e705c121SKalle Valo  * @IWL_D3_STATUS_RESET: device was reset while suspended
399e705c121SKalle Valo  */
400e705c121SKalle Valo enum iwl_d3_status {
401e705c121SKalle Valo 	IWL_D3_STATUS_ALIVE,
402e705c121SKalle Valo 	IWL_D3_STATUS_RESET,
403e705c121SKalle Valo };
404e705c121SKalle Valo 
405e705c121SKalle Valo /**
406e705c121SKalle Valo  * enum iwl_trans_status: transport status flags
407e705c121SKalle Valo  * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
408e705c121SKalle Valo  * @STATUS_DEVICE_ENABLED: APM is enabled
409e705c121SKalle Valo  * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
410e705c121SKalle Valo  * @STATUS_INT_ENABLED: interrupts are enabled
411e705c121SKalle Valo  * @STATUS_RFKILL: the HW RFkill switch is in KILL position
412e705c121SKalle Valo  * @STATUS_FW_ERROR: the fw is in error state
413e705c121SKalle Valo  * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
414e705c121SKalle Valo  *	are sent
415e705c121SKalle Valo  * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
416e705c121SKalle Valo  * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
417e705c121SKalle Valo  */
418e705c121SKalle Valo enum iwl_trans_status {
419e705c121SKalle Valo 	STATUS_SYNC_HCMD_ACTIVE,
420e705c121SKalle Valo 	STATUS_DEVICE_ENABLED,
421e705c121SKalle Valo 	STATUS_TPOWER_PMI,
422e705c121SKalle Valo 	STATUS_INT_ENABLED,
423e705c121SKalle Valo 	STATUS_RFKILL,
424e705c121SKalle Valo 	STATUS_FW_ERROR,
425e705c121SKalle Valo 	STATUS_TRANS_GOING_IDLE,
426e705c121SKalle Valo 	STATUS_TRANS_IDLE,
427e705c121SKalle Valo 	STATUS_TRANS_DEAD,
428e705c121SKalle Valo };
429e705c121SKalle Valo 
4306c4fbcbcSEmmanuel Grumbach static inline int
4316c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
4326c4fbcbcSEmmanuel Grumbach {
4336c4fbcbcSEmmanuel Grumbach 	switch (rb_size) {
4346c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_4K:
4356c4fbcbcSEmmanuel Grumbach 		return get_order(4 * 1024);
4366c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_8K:
4376c4fbcbcSEmmanuel Grumbach 		return get_order(8 * 1024);
4386c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_12K:
4396c4fbcbcSEmmanuel Grumbach 		return get_order(12 * 1024);
4406c4fbcbcSEmmanuel Grumbach 	default:
4416c4fbcbcSEmmanuel Grumbach 		WARN_ON(1);
4426c4fbcbcSEmmanuel Grumbach 		return -1;
4436c4fbcbcSEmmanuel Grumbach 	}
4446c4fbcbcSEmmanuel Grumbach }
4456c4fbcbcSEmmanuel Grumbach 
44639bdb17eSSharon Dvir struct iwl_hcmd_names {
44739bdb17eSSharon Dvir 	u8 cmd_id;
44839bdb17eSSharon Dvir 	const char *const cmd_name;
44939bdb17eSSharon Dvir };
45039bdb17eSSharon Dvir 
45139bdb17eSSharon Dvir #define HCMD_NAME(x)	\
45239bdb17eSSharon Dvir 	{ .cmd_id = x, .cmd_name = #x }
45339bdb17eSSharon Dvir 
45439bdb17eSSharon Dvir struct iwl_hcmd_arr {
45539bdb17eSSharon Dvir 	const struct iwl_hcmd_names *arr;
45639bdb17eSSharon Dvir 	int size;
45739bdb17eSSharon Dvir };
45839bdb17eSSharon Dvir 
45939bdb17eSSharon Dvir #define HCMD_ARR(x)	\
46039bdb17eSSharon Dvir 	{ .arr = x, .size = ARRAY_SIZE(x) }
46139bdb17eSSharon Dvir 
462e705c121SKalle Valo /**
463e705c121SKalle Valo  * struct iwl_trans_config - transport configuration
464e705c121SKalle Valo  *
465e705c121SKalle Valo  * @op_mode: pointer to the upper layer.
466e705c121SKalle Valo  * @cmd_queue: the index of the command queue.
467e705c121SKalle Valo  *	Must be set before start_fw.
468e705c121SKalle Valo  * @cmd_fifo: the fifo for host commands
469e705c121SKalle Valo  * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
470e705c121SKalle Valo  * @no_reclaim_cmds: Some devices erroneously don't set the
471e705c121SKalle Valo  *	SEQ_RX_FRAME bit on some notifications, this is the
472e705c121SKalle Valo  *	list of such notifications to filter. Max length is
473e705c121SKalle Valo  *	%MAX_NO_RECLAIM_CMDS.
474e705c121SKalle Valo  * @n_no_reclaim_cmds: # of commands in list
4756c4fbcbcSEmmanuel Grumbach  * @rx_buf_size: RX buffer size needed for A-MSDUs
476e705c121SKalle Valo  *	if unset 4k will be the RX buffer size
477e705c121SKalle Valo  * @bc_table_dword: set to true if the BC table expects the byte count to be
478e705c121SKalle Valo  *	in DWORD (as opposed to bytes)
479e705c121SKalle Valo  * @scd_set_active: should the transport configure the SCD for HCMD queue
480e705c121SKalle Valo  * @wide_cmd_header: firmware supports wide host command header
48139bdb17eSSharon Dvir  * @command_groups: array of command groups, each member is an array of the
48239bdb17eSSharon Dvir  *	commands in the group; for debugging only
48339bdb17eSSharon Dvir  * @command_groups_size: number of command groups, to avoid illegal access
484e705c121SKalle Valo  * @sdio_adma_addr: the default address to set for the ADMA in SDIO mode until
485e705c121SKalle Valo  *	we get the ALIVE from the uCode
486e705c121SKalle Valo  */
487e705c121SKalle Valo struct iwl_trans_config {
488e705c121SKalle Valo 	struct iwl_op_mode *op_mode;
489e705c121SKalle Valo 
490e705c121SKalle Valo 	u8 cmd_queue;
491e705c121SKalle Valo 	u8 cmd_fifo;
492e705c121SKalle Valo 	unsigned int cmd_q_wdg_timeout;
493e705c121SKalle Valo 	const u8 *no_reclaim_cmds;
494e705c121SKalle Valo 	unsigned int n_no_reclaim_cmds;
495e705c121SKalle Valo 
4966c4fbcbcSEmmanuel Grumbach 	enum iwl_amsdu_size rx_buf_size;
497e705c121SKalle Valo 	bool bc_table_dword;
498e705c121SKalle Valo 	bool scd_set_active;
499e705c121SKalle Valo 	bool wide_cmd_header;
50039bdb17eSSharon Dvir 	const struct iwl_hcmd_arr *command_groups;
50139bdb17eSSharon Dvir 	int command_groups_size;
502e705c121SKalle Valo 
503e705c121SKalle Valo 	u32 sdio_adma_addr;
504e705c121SKalle Valo };
505e705c121SKalle Valo 
506e705c121SKalle Valo struct iwl_trans_dump_data {
507e705c121SKalle Valo 	u32 len;
508e705c121SKalle Valo 	u8 data[];
509e705c121SKalle Valo };
510e705c121SKalle Valo 
511e705c121SKalle Valo struct iwl_trans;
512e705c121SKalle Valo 
513e705c121SKalle Valo struct iwl_trans_txq_scd_cfg {
514e705c121SKalle Valo 	u8 fifo;
515e705c121SKalle Valo 	s8 sta_id;
516e705c121SKalle Valo 	u8 tid;
517e705c121SKalle Valo 	bool aggregate;
518e705c121SKalle Valo 	int frame_limit;
519e705c121SKalle Valo };
520e705c121SKalle Valo 
521e705c121SKalle Valo /**
522e705c121SKalle Valo  * struct iwl_trans_ops - transport specific operations
523e705c121SKalle Valo  *
524e705c121SKalle Valo  * All the handlers MUST be implemented
525e705c121SKalle Valo  *
526e705c121SKalle Valo  * @start_hw: starts the HW. If low_power is true, the NIC needs to be taken
527e705c121SKalle Valo  *	out of a low power state. From that point on, the HW can send
528e705c121SKalle Valo  *	interrupts. May sleep.
529e705c121SKalle Valo  * @op_mode_leave: Turn off the HW RF kill indication if on
530e705c121SKalle Valo  *	May sleep
531e705c121SKalle Valo  * @start_fw: allocates and inits all the resources for the transport
532e705c121SKalle Valo  *	layer. Also kick a fw image.
533e705c121SKalle Valo  *	May sleep
534e705c121SKalle Valo  * @fw_alive: called when the fw sends alive notification. If the fw provides
535e705c121SKalle Valo  *	the SCD base address in SRAM, then provide it here, or 0 otherwise.
536e705c121SKalle Valo  *	May sleep
537e705c121SKalle Valo  * @stop_device: stops the whole device (embedded CPU put to reset) and stops
538e705c121SKalle Valo  *	the HW. If low_power is true, the NIC will be put in low power state.
539e705c121SKalle Valo  *	From that point on, the HW will be stopped but will still issue an
540e705c121SKalle Valo  *	interrupt if the HW RF kill switch is triggered.
541e705c121SKalle Valo  *	This callback must do the right thing and not crash even if %start_hw()
542e705c121SKalle Valo  *	was called but not &start_fw(). May sleep.
543e705c121SKalle Valo  * @d3_suspend: put the device into the correct mode for WoWLAN during
544e705c121SKalle Valo  *	suspend. This is optional, if not implemented WoWLAN will not be
545e705c121SKalle Valo  *	supported. This callback may sleep.
546e705c121SKalle Valo  * @d3_resume: resume the device after WoWLAN, enabling the opmode to
547e705c121SKalle Valo  *	talk to the WoWLAN image to get its status. This is optional, if not
548e705c121SKalle Valo  *	implemented WoWLAN will not be supported. This callback may sleep.
549e705c121SKalle Valo  * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
550e705c121SKalle Valo  *	If RFkill is asserted in the middle of a SYNC host command, it must
551e705c121SKalle Valo  *	return -ERFKILL straight away.
552e705c121SKalle Valo  *	May sleep only if CMD_ASYNC is not set
553e705c121SKalle Valo  * @tx: send an skb
554e705c121SKalle Valo  *	Must be atomic
555e705c121SKalle Valo  * @reclaim: free packet until ssn. Returns a list of freed packets.
556e705c121SKalle Valo  *	Must be atomic
557e705c121SKalle Valo  * @txq_enable: setup a queue. To setup an AC queue, use the
558e705c121SKalle Valo  *	iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
559e705c121SKalle Valo  *	this one. The op_mode must not configure the HCMD queue. The scheduler
560e705c121SKalle Valo  *	configuration may be %NULL, in which case the hardware will not be
561e705c121SKalle Valo  *	configured. May sleep.
562e705c121SKalle Valo  * @txq_disable: de-configure a Tx queue to send AMPDUs
563e705c121SKalle Valo  *	Must be atomic
564e705c121SKalle Valo  * @wait_tx_queue_empty: wait until tx queues are empty. May sleep.
565e705c121SKalle Valo  * @freeze_txq_timer: prevents the timer of the queue from firing until the
566e705c121SKalle Valo  *	queue is set to awake. Must be atomic.
5670cd58eaaSEmmanuel Grumbach  * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
5680cd58eaaSEmmanuel Grumbach  *	that the transport needs to refcount the calls since this function
5690cd58eaaSEmmanuel Grumbach  *	will be called several times with block = true, and then the queues
5700cd58eaaSEmmanuel Grumbach  *	need to be unblocked only after the same number of calls with
5710cd58eaaSEmmanuel Grumbach  *	block = false.
572e705c121SKalle Valo  * @write8: write a u8 to a register at offset ofs from the BAR
573e705c121SKalle Valo  * @write32: write a u32 to a register at offset ofs from the BAR
574e705c121SKalle Valo  * @read32: read a u32 register at offset ofs from the BAR
575e705c121SKalle Valo  * @read_prph: read a DWORD from a periphery register
576e705c121SKalle Valo  * @write_prph: write a DWORD to a periphery register
577e705c121SKalle Valo  * @read_mem: read device's SRAM in DWORD
578e705c121SKalle Valo  * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
579e705c121SKalle Valo  *	will be zeroed.
580e705c121SKalle Valo  * @configure: configure parameters required by the transport layer from
581e705c121SKalle Valo  *	the op_mode. May be called several times before start_fw, can't be
582e705c121SKalle Valo  *	called after that.
583e705c121SKalle Valo  * @set_pmi: set the power pmi state
584e705c121SKalle Valo  * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
585e705c121SKalle Valo  *	Sleeping is not allowed between grab_nic_access and
586e705c121SKalle Valo  *	release_nic_access.
587e705c121SKalle Valo  * @release_nic_access: let the NIC go to sleep. The "flags" parameter
588e705c121SKalle Valo  *	must be the same one that was sent before to the grab_nic_access.
589e705c121SKalle Valo  * @set_bits_mask - set SRAM register according to value and mask.
590e705c121SKalle Valo  * @ref: grab a reference to the transport/FW layers, disallowing
591e705c121SKalle Valo  *	certain low power states
592e705c121SKalle Valo  * @unref: release a reference previously taken with @ref. Note that
593e705c121SKalle Valo  *	initially the reference count is 1, making an initial @unref
594e705c121SKalle Valo  *	necessary to allow low power states.
595e705c121SKalle Valo  * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
596e705c121SKalle Valo  *	TX'ed commands and similar. The buffer will be vfree'd by the caller.
597e705c121SKalle Valo  *	Note that the transport must fill in the proper file headers.
598e705c121SKalle Valo  */
599e705c121SKalle Valo struct iwl_trans_ops {
600e705c121SKalle Valo 
601e705c121SKalle Valo 	int (*start_hw)(struct iwl_trans *iwl_trans, bool low_power);
602e705c121SKalle Valo 	void (*op_mode_leave)(struct iwl_trans *iwl_trans);
603e705c121SKalle Valo 	int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
604e705c121SKalle Valo 			bool run_in_rfkill);
605e705c121SKalle Valo 	int (*update_sf)(struct iwl_trans *trans,
606e705c121SKalle Valo 			 struct iwl_sf_region *st_fwrd_space);
607e705c121SKalle Valo 	void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
608e705c121SKalle Valo 	void (*stop_device)(struct iwl_trans *trans, bool low_power);
609e705c121SKalle Valo 
610e705c121SKalle Valo 	void (*d3_suspend)(struct iwl_trans *trans, bool test);
611e705c121SKalle Valo 	int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
612e705c121SKalle Valo 			 bool test);
613e705c121SKalle Valo 
614e705c121SKalle Valo 	int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
615e705c121SKalle Valo 
616e705c121SKalle Valo 	int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
617e705c121SKalle Valo 		  struct iwl_device_cmd *dev_cmd, int queue);
618e705c121SKalle Valo 	void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
619e705c121SKalle Valo 			struct sk_buff_head *skbs);
620e705c121SKalle Valo 
621e705c121SKalle Valo 	void (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
622e705c121SKalle Valo 			   const struct iwl_trans_txq_scd_cfg *cfg,
623e705c121SKalle Valo 			   unsigned int queue_wdg_timeout);
624e705c121SKalle Valo 	void (*txq_disable)(struct iwl_trans *trans, int queue,
625e705c121SKalle Valo 			    bool configure_scd);
626e705c121SKalle Valo 
627e705c121SKalle Valo 	int (*wait_tx_queue_empty)(struct iwl_trans *trans, u32 txq_bm);
628e705c121SKalle Valo 	void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
629e705c121SKalle Valo 				 bool freeze);
6300cd58eaaSEmmanuel Grumbach 	void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
631e705c121SKalle Valo 
632e705c121SKalle Valo 	void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
633e705c121SKalle Valo 	void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
634e705c121SKalle Valo 	u32 (*read32)(struct iwl_trans *trans, u32 ofs);
635e705c121SKalle Valo 	u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
636e705c121SKalle Valo 	void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
637e705c121SKalle Valo 	int (*read_mem)(struct iwl_trans *trans, u32 addr,
638e705c121SKalle Valo 			void *buf, int dwords);
639e705c121SKalle Valo 	int (*write_mem)(struct iwl_trans *trans, u32 addr,
640e705c121SKalle Valo 			 const void *buf, int dwords);
641e705c121SKalle Valo 	void (*configure)(struct iwl_trans *trans,
642e705c121SKalle Valo 			  const struct iwl_trans_config *trans_cfg);
643e705c121SKalle Valo 	void (*set_pmi)(struct iwl_trans *trans, bool state);
644e705c121SKalle Valo 	bool (*grab_nic_access)(struct iwl_trans *trans, bool silent,
645e705c121SKalle Valo 				unsigned long *flags);
646e705c121SKalle Valo 	void (*release_nic_access)(struct iwl_trans *trans,
647e705c121SKalle Valo 				   unsigned long *flags);
648e705c121SKalle Valo 	void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
649e705c121SKalle Valo 			      u32 value);
650e705c121SKalle Valo 	void (*ref)(struct iwl_trans *trans);
651e705c121SKalle Valo 	void (*unref)(struct iwl_trans *trans);
652e705c121SKalle Valo 	int  (*suspend)(struct iwl_trans *trans);
653e705c121SKalle Valo 	void (*resume)(struct iwl_trans *trans);
654e705c121SKalle Valo 
655e705c121SKalle Valo 	struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
656e705c121SKalle Valo 						 struct iwl_fw_dbg_trigger_tlv
657e705c121SKalle Valo 						 *trigger);
658e705c121SKalle Valo };
659e705c121SKalle Valo 
660e705c121SKalle Valo /**
661e705c121SKalle Valo  * enum iwl_trans_state - state of the transport layer
662e705c121SKalle Valo  *
663e705c121SKalle Valo  * @IWL_TRANS_NO_FW: no fw has sent an alive response
664e705c121SKalle Valo  * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response
665e705c121SKalle Valo  */
666e705c121SKalle Valo enum iwl_trans_state {
667e705c121SKalle Valo 	IWL_TRANS_NO_FW = 0,
668e705c121SKalle Valo 	IWL_TRANS_FW_ALIVE	= 1,
669e705c121SKalle Valo };
670e705c121SKalle Valo 
671e705c121SKalle Valo /**
672b7282643SLuca Coelho  * DOC: Platform power management
673e705c121SKalle Valo  *
674b7282643SLuca Coelho  * There are two types of platform power management: system-wide
675b7282643SLuca Coelho  * (WoWLAN) and runtime.
676b7282643SLuca Coelho  *
677b7282643SLuca Coelho  * In system-wide power management the entire platform goes into a low
678b7282643SLuca Coelho  * power state (e.g. idle or suspend to RAM) at the same time and the
679b7282643SLuca Coelho  * device is configured as a wakeup source for the entire platform.
680b7282643SLuca Coelho  * This is usually triggered by userspace activity (e.g. the user
681b7282643SLuca Coelho  * presses the suspend button or a power management daemon decides to
682b7282643SLuca Coelho  * put the platform in low power mode).  The device's behavior in this
683b7282643SLuca Coelho  * mode is dictated by the wake-on-WLAN configuration.
684b7282643SLuca Coelho  *
685b7282643SLuca Coelho  * In runtime power management, only the devices which are themselves
686b7282643SLuca Coelho  * idle enter a low power state.  This is done at runtime, which means
687b7282643SLuca Coelho  * that the entire system is still running normally.  This mode is
688b7282643SLuca Coelho  * usually triggered automatically by the device driver and requires
689b7282643SLuca Coelho  * the ability to enter and exit the low power modes in a very short
690b7282643SLuca Coelho  * time, so there is not much impact in usability.
691b7282643SLuca Coelho  *
692b7282643SLuca Coelho  * The terms used for the device's behavior are as follows:
693b7282643SLuca Coelho  *
694b7282643SLuca Coelho  *	- D0: the device is fully powered and the host is awake;
695b7282643SLuca Coelho  *	- D3: the device is in low power mode and only reacts to
696b7282643SLuca Coelho  *		specific events (e.g. magic-packet received or scan
697b7282643SLuca Coelho  *		results found);
698b7282643SLuca Coelho  *	- D0I3: the device is in low power mode and reacts to any
699b7282643SLuca Coelho  *		activity (e.g. RX);
700b7282643SLuca Coelho  *
701b7282643SLuca Coelho  * These terms reflect the power modes in the firmware and are not to
702b7282643SLuca Coelho  * be confused with the physical device power state.  The NIC can be
703b7282643SLuca Coelho  * in D0I3 mode even if, for instance, the PCI device is in D3 state.
704e705c121SKalle Valo  */
705b7282643SLuca Coelho 
706b7282643SLuca Coelho /**
707b7282643SLuca Coelho  * enum iwl_plat_pm_mode - platform power management mode
708b7282643SLuca Coelho  *
709b7282643SLuca Coelho  * This enumeration describes the device's platform power management
710b7282643SLuca Coelho  * behavior when in idle mode (i.e. runtime power management) or when
711b7282643SLuca Coelho  * in system-wide suspend (i.e WoWLAN).
712b7282643SLuca Coelho  *
713b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
714b7282643SLuca Coelho  *	device.  At runtime, this means that nothing happens and the
715b7282643SLuca Coelho  *	device always remains in active.  In system-wide suspend mode,
716b7282643SLuca Coelho  *	it means that the all connections will be closed automatically
717b7282643SLuca Coelho  *	by mac80211 before the platform is suspended.
718b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
719b7282643SLuca Coelho  *	For runtime power management, this mode is not officially
720b7282643SLuca Coelho  *	supported.
721b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_D0I3: the device goes into D0I3 mode.
722b7282643SLuca Coelho  */
723b7282643SLuca Coelho enum iwl_plat_pm_mode {
724b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_DISABLED,
725b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_D3,
726b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_D0I3,
727e705c121SKalle Valo };
728e705c121SKalle Valo 
729e705c121SKalle Valo /**
730e705c121SKalle Valo  * struct iwl_trans - transport common data
731e705c121SKalle Valo  *
732e705c121SKalle Valo  * @ops - pointer to iwl_trans_ops
733e705c121SKalle Valo  * @op_mode - pointer to the op_mode
734e705c121SKalle Valo  * @cfg - pointer to the configuration
735e705c121SKalle Valo  * @status: a bit-mask of transport status flags
736e705c121SKalle Valo  * @dev - pointer to struct device * that represents the device
737e705c121SKalle Valo  * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
738e705c121SKalle Valo  *	0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
739e705c121SKalle Valo  * @hw_id: a u32 with the ID of the device / sub-device.
740e705c121SKalle Valo  *	Set during transport allocation.
741e705c121SKalle Valo  * @hw_id_str: a string with info about HW ID. Set during transport allocation.
742e705c121SKalle Valo  * @pm_support: set to true in start_hw if link pm is supported
743e705c121SKalle Valo  * @ltr_enabled: set to true if the LTR is enabled
744e705c121SKalle Valo  * @num_rx_queues: number of RX queues allocated by the transport;
745e705c121SKalle Valo  *	the transport must set this before calling iwl_drv_start()
746e705c121SKalle Valo  * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
747e705c121SKalle Valo  *	The user should use iwl_trans_{alloc,free}_tx_cmd.
748e705c121SKalle Valo  * @dev_cmd_headroom: room needed for the transport's private use before the
749e705c121SKalle Valo  *	device_cmd for Tx - for internal use only
750e705c121SKalle Valo  *	The user should use iwl_trans_{alloc,free}_tx_cmd.
751e705c121SKalle Valo  * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
752e705c121SKalle Valo  *	starting the firmware, used for tracing
753e705c121SKalle Valo  * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
754e705c121SKalle Valo  *	start of the 802.11 header in the @rx_mpdu_cmd
755e705c121SKalle Valo  * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
756e705c121SKalle Valo  * @dbg_dest_tlv: points to the destination TLV for debug
757e705c121SKalle Valo  * @dbg_conf_tlv: array of pointers to configuration TLVs for debug
758e705c121SKalle Valo  * @dbg_trigger_tlv: array of pointers to triggers TLVs for debug
759e705c121SKalle Valo  * @dbg_dest_reg_num: num of reg_ops in %dbg_dest_tlv
760e705c121SKalle Valo  * @paging_req_addr: The location were the FW will upload / download the pages
761e705c121SKalle Valo  *	from. The address is set by the opmode
762e705c121SKalle Valo  * @paging_db: Pointer to the opmode paging data base, the pointer is set by
763e705c121SKalle Valo  *	the opmode.
764e705c121SKalle Valo  * @paging_download_buf: Buffer used for copying all of the pages before
765e705c121SKalle Valo  *	downloading them to the FW. The buffer is allocated in the opmode
766b7282643SLuca Coelho  * @system_pm_mode: the system-wide power management mode in use.
767b7282643SLuca Coelho  *	This mode is set dynamically, depending on the WoWLAN values
768b7282643SLuca Coelho  *	configured from the userspace at runtime.
769b7282643SLuca Coelho  * @runtime_pm_mode: the runtime power management mode in use.  This
770b7282643SLuca Coelho  *	mode is set during the initialization phase and is not
771b7282643SLuca Coelho  *	supposed to change during runtime.
772e705c121SKalle Valo  */
773e705c121SKalle Valo struct iwl_trans {
774e705c121SKalle Valo 	const struct iwl_trans_ops *ops;
775e705c121SKalle Valo 	struct iwl_op_mode *op_mode;
776e705c121SKalle Valo 	const struct iwl_cfg *cfg;
777e705c121SKalle Valo 	enum iwl_trans_state state;
778e705c121SKalle Valo 	unsigned long status;
779e705c121SKalle Valo 
780e705c121SKalle Valo 	struct device *dev;
781e705c121SKalle Valo 	u32 max_skb_frags;
782e705c121SKalle Valo 	u32 hw_rev;
783e705c121SKalle Valo 	u32 hw_id;
784e705c121SKalle Valo 	char hw_id_str[52];
785e705c121SKalle Valo 
786e705c121SKalle Valo 	u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
787e705c121SKalle Valo 
788e705c121SKalle Valo 	bool pm_support;
789e705c121SKalle Valo 	bool ltr_enabled;
790e705c121SKalle Valo 
79139bdb17eSSharon Dvir 	const struct iwl_hcmd_arr *command_groups;
79239bdb17eSSharon Dvir 	int command_groups_size;
79339bdb17eSSharon Dvir 
794e705c121SKalle Valo 	u8 num_rx_queues;
795e705c121SKalle Valo 
796e705c121SKalle Valo 	/* The following fields are internal only */
797e705c121SKalle Valo 	struct kmem_cache *dev_cmd_pool;
798e705c121SKalle Valo 	size_t dev_cmd_headroom;
799e705c121SKalle Valo 	char dev_cmd_pool_name[50];
800e705c121SKalle Valo 
801e705c121SKalle Valo 	struct dentry *dbgfs_dir;
802e705c121SKalle Valo 
803e705c121SKalle Valo #ifdef CONFIG_LOCKDEP
804e705c121SKalle Valo 	struct lockdep_map sync_cmd_lockdep_map;
805e705c121SKalle Valo #endif
806e705c121SKalle Valo 
807e705c121SKalle Valo 	u64 dflt_pwr_limit;
808e705c121SKalle Valo 
809e705c121SKalle Valo 	const struct iwl_fw_dbg_dest_tlv *dbg_dest_tlv;
810e705c121SKalle Valo 	const struct iwl_fw_dbg_conf_tlv *dbg_conf_tlv[FW_DBG_CONF_MAX];
811e705c121SKalle Valo 	struct iwl_fw_dbg_trigger_tlv * const *dbg_trigger_tlv;
812e705c121SKalle Valo 	u8 dbg_dest_reg_num;
813e705c121SKalle Valo 
814e705c121SKalle Valo 	/*
815e705c121SKalle Valo 	 * Paging parameters - All of the parameters should be set by the
816e705c121SKalle Valo 	 * opmode when paging is enabled
817e705c121SKalle Valo 	 */
818e705c121SKalle Valo 	u32 paging_req_addr;
819e705c121SKalle Valo 	struct iwl_fw_paging *paging_db;
820e705c121SKalle Valo 	void *paging_download_buf;
821e705c121SKalle Valo 
822b7282643SLuca Coelho 	enum iwl_plat_pm_mode system_pm_mode;
823b7282643SLuca Coelho 	enum iwl_plat_pm_mode runtime_pm_mode;
824e705c121SKalle Valo 
825e705c121SKalle Valo 	/* pointer to trans specific struct */
826e705c121SKalle Valo 	/*Ensure that this pointer will always be aligned to sizeof pointer */
827e705c121SKalle Valo 	char trans_specific[0] __aligned(sizeof(void *));
828e705c121SKalle Valo };
829e705c121SKalle Valo 
83039bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
83139bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
83239bdb17eSSharon Dvir 
833e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans,
834e705c121SKalle Valo 				       const struct iwl_trans_config *trans_cfg)
835e705c121SKalle Valo {
836e705c121SKalle Valo 	trans->op_mode = trans_cfg->op_mode;
837e705c121SKalle Valo 
838e705c121SKalle Valo 	trans->ops->configure(trans, trans_cfg);
83939bdb17eSSharon Dvir 	WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
840e705c121SKalle Valo }
841e705c121SKalle Valo 
842e705c121SKalle Valo static inline int _iwl_trans_start_hw(struct iwl_trans *trans, bool low_power)
843e705c121SKalle Valo {
844e705c121SKalle Valo 	might_sleep();
845e705c121SKalle Valo 
846e705c121SKalle Valo 	return trans->ops->start_hw(trans, low_power);
847e705c121SKalle Valo }
848e705c121SKalle Valo 
849e705c121SKalle Valo static inline int iwl_trans_start_hw(struct iwl_trans *trans)
850e705c121SKalle Valo {
851e705c121SKalle Valo 	return trans->ops->start_hw(trans, true);
852e705c121SKalle Valo }
853e705c121SKalle Valo 
854e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
855e705c121SKalle Valo {
856e705c121SKalle Valo 	might_sleep();
857e705c121SKalle Valo 
858e705c121SKalle Valo 	if (trans->ops->op_mode_leave)
859e705c121SKalle Valo 		trans->ops->op_mode_leave(trans);
860e705c121SKalle Valo 
861e705c121SKalle Valo 	trans->op_mode = NULL;
862e705c121SKalle Valo 
863e705c121SKalle Valo 	trans->state = IWL_TRANS_NO_FW;
864e705c121SKalle Valo }
865e705c121SKalle Valo 
866e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
867e705c121SKalle Valo {
868e705c121SKalle Valo 	might_sleep();
869e705c121SKalle Valo 
870e705c121SKalle Valo 	trans->state = IWL_TRANS_FW_ALIVE;
871e705c121SKalle Valo 
872e705c121SKalle Valo 	trans->ops->fw_alive(trans, scd_addr);
873e705c121SKalle Valo }
874e705c121SKalle Valo 
875e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans,
876e705c121SKalle Valo 				     const struct fw_img *fw,
877e705c121SKalle Valo 				     bool run_in_rfkill)
878e705c121SKalle Valo {
879e705c121SKalle Valo 	might_sleep();
880e705c121SKalle Valo 
881e705c121SKalle Valo 	WARN_ON_ONCE(!trans->rx_mpdu_cmd);
882e705c121SKalle Valo 
883e705c121SKalle Valo 	clear_bit(STATUS_FW_ERROR, &trans->status);
884e705c121SKalle Valo 	return trans->ops->start_fw(trans, fw, run_in_rfkill);
885e705c121SKalle Valo }
886e705c121SKalle Valo 
887e705c121SKalle Valo static inline int iwl_trans_update_sf(struct iwl_trans *trans,
888e705c121SKalle Valo 				      struct iwl_sf_region *st_fwrd_space)
889e705c121SKalle Valo {
890e705c121SKalle Valo 	might_sleep();
891e705c121SKalle Valo 
892e705c121SKalle Valo 	if (trans->ops->update_sf)
893e705c121SKalle Valo 		return trans->ops->update_sf(trans, st_fwrd_space);
894e705c121SKalle Valo 
895e705c121SKalle Valo 	return 0;
896e705c121SKalle Valo }
897e705c121SKalle Valo 
898e705c121SKalle Valo static inline void _iwl_trans_stop_device(struct iwl_trans *trans,
899e705c121SKalle Valo 					  bool low_power)
900e705c121SKalle Valo {
901e705c121SKalle Valo 	might_sleep();
902e705c121SKalle Valo 
903e705c121SKalle Valo 	trans->ops->stop_device(trans, low_power);
904e705c121SKalle Valo 
905e705c121SKalle Valo 	trans->state = IWL_TRANS_NO_FW;
906e705c121SKalle Valo }
907e705c121SKalle Valo 
908e705c121SKalle Valo static inline void iwl_trans_stop_device(struct iwl_trans *trans)
909e705c121SKalle Valo {
910e705c121SKalle Valo 	_iwl_trans_stop_device(trans, true);
911e705c121SKalle Valo }
912e705c121SKalle Valo 
913e705c121SKalle Valo static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test)
914e705c121SKalle Valo {
915e705c121SKalle Valo 	might_sleep();
916e705c121SKalle Valo 	if (trans->ops->d3_suspend)
917e705c121SKalle Valo 		trans->ops->d3_suspend(trans, test);
918e705c121SKalle Valo }
919e705c121SKalle Valo 
920e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
921e705c121SKalle Valo 				      enum iwl_d3_status *status,
922e705c121SKalle Valo 				      bool test)
923e705c121SKalle Valo {
924e705c121SKalle Valo 	might_sleep();
925e705c121SKalle Valo 	if (!trans->ops->d3_resume)
926e705c121SKalle Valo 		return 0;
927e705c121SKalle Valo 
928e705c121SKalle Valo 	return trans->ops->d3_resume(trans, status, test);
929e705c121SKalle Valo }
930e705c121SKalle Valo 
931e705c121SKalle Valo static inline void iwl_trans_ref(struct iwl_trans *trans)
932e705c121SKalle Valo {
933e705c121SKalle Valo 	if (trans->ops->ref)
934e705c121SKalle Valo 		trans->ops->ref(trans);
935e705c121SKalle Valo }
936e705c121SKalle Valo 
937e705c121SKalle Valo static inline void iwl_trans_unref(struct iwl_trans *trans)
938e705c121SKalle Valo {
939e705c121SKalle Valo 	if (trans->ops->unref)
940e705c121SKalle Valo 		trans->ops->unref(trans);
941e705c121SKalle Valo }
942e705c121SKalle Valo 
943e705c121SKalle Valo static inline int iwl_trans_suspend(struct iwl_trans *trans)
944e705c121SKalle Valo {
945e705c121SKalle Valo 	if (!trans->ops->suspend)
946e705c121SKalle Valo 		return 0;
947e705c121SKalle Valo 
948e705c121SKalle Valo 	return trans->ops->suspend(trans);
949e705c121SKalle Valo }
950e705c121SKalle Valo 
951e705c121SKalle Valo static inline void iwl_trans_resume(struct iwl_trans *trans)
952e705c121SKalle Valo {
953e705c121SKalle Valo 	if (trans->ops->resume)
954e705c121SKalle Valo 		trans->ops->resume(trans);
955e705c121SKalle Valo }
956e705c121SKalle Valo 
957e705c121SKalle Valo static inline struct iwl_trans_dump_data *
958e705c121SKalle Valo iwl_trans_dump_data(struct iwl_trans *trans,
959e705c121SKalle Valo 		    struct iwl_fw_dbg_trigger_tlv *trigger)
960e705c121SKalle Valo {
961e705c121SKalle Valo 	if (!trans->ops->dump_data)
962e705c121SKalle Valo 		return NULL;
963e705c121SKalle Valo 	return trans->ops->dump_data(trans, trigger);
964e705c121SKalle Valo }
965e705c121SKalle Valo 
966e705c121SKalle Valo static inline struct iwl_device_cmd *
967e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
968e705c121SKalle Valo {
969e705c121SKalle Valo 	u8 *dev_cmd_ptr = kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC);
970e705c121SKalle Valo 
971e705c121SKalle Valo 	if (unlikely(dev_cmd_ptr == NULL))
972e705c121SKalle Valo 		return NULL;
973e705c121SKalle Valo 
974e705c121SKalle Valo 	return (struct iwl_device_cmd *)
975e705c121SKalle Valo 			(dev_cmd_ptr + trans->dev_cmd_headroom);
976e705c121SKalle Valo }
977e705c121SKalle Valo 
97892fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
97992fe8343SEmmanuel Grumbach 
980e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
981e705c121SKalle Valo 					 struct iwl_device_cmd *dev_cmd)
982e705c121SKalle Valo {
983e705c121SKalle Valo 	u8 *dev_cmd_ptr = (u8 *)dev_cmd - trans->dev_cmd_headroom;
984e705c121SKalle Valo 
985e705c121SKalle Valo 	kmem_cache_free(trans->dev_cmd_pool, dev_cmd_ptr);
986e705c121SKalle Valo }
987e705c121SKalle Valo 
988e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
989e705c121SKalle Valo 			       struct iwl_device_cmd *dev_cmd, int queue)
990e705c121SKalle Valo {
991e705c121SKalle Valo 	if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
992e705c121SKalle Valo 		return -EIO;
993e705c121SKalle Valo 
994e705c121SKalle Valo 	if (unlikely(trans->state != IWL_TRANS_FW_ALIVE))
995e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
996e705c121SKalle Valo 
997e705c121SKalle Valo 	return trans->ops->tx(trans, skb, dev_cmd, queue);
998e705c121SKalle Valo }
999e705c121SKalle Valo 
1000e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
1001e705c121SKalle Valo 				     int ssn, struct sk_buff_head *skbs)
1002e705c121SKalle Valo {
1003e705c121SKalle Valo 	if (unlikely(trans->state != IWL_TRANS_FW_ALIVE))
1004e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1005e705c121SKalle Valo 
1006e705c121SKalle Valo 	trans->ops->reclaim(trans, queue, ssn, skbs);
1007e705c121SKalle Valo }
1008e705c121SKalle Valo 
1009e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
1010e705c121SKalle Valo 					 bool configure_scd)
1011e705c121SKalle Valo {
1012e705c121SKalle Valo 	trans->ops->txq_disable(trans, queue, configure_scd);
1013e705c121SKalle Valo }
1014e705c121SKalle Valo 
1015e705c121SKalle Valo static inline void
1016e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
1017e705c121SKalle Valo 			 const struct iwl_trans_txq_scd_cfg *cfg,
1018e705c121SKalle Valo 			 unsigned int queue_wdg_timeout)
1019e705c121SKalle Valo {
1020e705c121SKalle Valo 	might_sleep();
1021e705c121SKalle Valo 
1022e705c121SKalle Valo 	if (unlikely((trans->state != IWL_TRANS_FW_ALIVE)))
1023e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1024e705c121SKalle Valo 
1025e705c121SKalle Valo 	trans->ops->txq_enable(trans, queue, ssn, cfg, queue_wdg_timeout);
1026e705c121SKalle Valo }
1027e705c121SKalle Valo 
1028e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1029e705c121SKalle Valo 					int fifo, int sta_id, int tid,
1030e705c121SKalle Valo 					int frame_limit, u16 ssn,
1031e705c121SKalle Valo 					unsigned int queue_wdg_timeout)
1032e705c121SKalle Valo {
1033e705c121SKalle Valo 	struct iwl_trans_txq_scd_cfg cfg = {
1034e705c121SKalle Valo 		.fifo = fifo,
1035e705c121SKalle Valo 		.sta_id = sta_id,
1036e705c121SKalle Valo 		.tid = tid,
1037e705c121SKalle Valo 		.frame_limit = frame_limit,
1038e705c121SKalle Valo 		.aggregate = sta_id >= 0,
1039e705c121SKalle Valo 	};
1040e705c121SKalle Valo 
1041e705c121SKalle Valo 	iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1042e705c121SKalle Valo }
1043e705c121SKalle Valo 
1044e705c121SKalle Valo static inline
1045e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1046e705c121SKalle Valo 			     unsigned int queue_wdg_timeout)
1047e705c121SKalle Valo {
1048e705c121SKalle Valo 	struct iwl_trans_txq_scd_cfg cfg = {
1049e705c121SKalle Valo 		.fifo = fifo,
1050e705c121SKalle Valo 		.sta_id = -1,
1051e705c121SKalle Valo 		.tid = IWL_MAX_TID_COUNT,
1052e705c121SKalle Valo 		.frame_limit = IWL_FRAME_LIMIT,
1053e705c121SKalle Valo 		.aggregate = false,
1054e705c121SKalle Valo 	};
1055e705c121SKalle Valo 
1056e705c121SKalle Valo 	iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1057e705c121SKalle Valo }
1058e705c121SKalle Valo 
1059e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1060e705c121SKalle Valo 					      unsigned long txqs,
1061e705c121SKalle Valo 					      bool freeze)
1062e705c121SKalle Valo {
1063e705c121SKalle Valo 	if (unlikely(trans->state != IWL_TRANS_FW_ALIVE))
1064e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1065e705c121SKalle Valo 
1066e705c121SKalle Valo 	if (trans->ops->freeze_txq_timer)
1067e705c121SKalle Valo 		trans->ops->freeze_txq_timer(trans, txqs, freeze);
1068e705c121SKalle Valo }
1069e705c121SKalle Valo 
10700cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
10710cd58eaaSEmmanuel Grumbach 					    bool block)
10720cd58eaaSEmmanuel Grumbach {
10730cd58eaaSEmmanuel Grumbach 	if (unlikely(trans->state != IWL_TRANS_FW_ALIVE))
10740cd58eaaSEmmanuel Grumbach 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
10750cd58eaaSEmmanuel Grumbach 
10760cd58eaaSEmmanuel Grumbach 	if (trans->ops->block_txq_ptrs)
10770cd58eaaSEmmanuel Grumbach 		trans->ops->block_txq_ptrs(trans, block);
10780cd58eaaSEmmanuel Grumbach }
10790cd58eaaSEmmanuel Grumbach 
1080e705c121SKalle Valo static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans,
1081e705c121SKalle Valo 						u32 txqs)
1082e705c121SKalle Valo {
1083e705c121SKalle Valo 	if (unlikely(trans->state != IWL_TRANS_FW_ALIVE))
1084e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1085e705c121SKalle Valo 
1086e705c121SKalle Valo 	return trans->ops->wait_tx_queue_empty(trans, txqs);
1087e705c121SKalle Valo }
1088e705c121SKalle Valo 
1089e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1090e705c121SKalle Valo {
1091e705c121SKalle Valo 	trans->ops->write8(trans, ofs, val);
1092e705c121SKalle Valo }
1093e705c121SKalle Valo 
1094e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1095e705c121SKalle Valo {
1096e705c121SKalle Valo 	trans->ops->write32(trans, ofs, val);
1097e705c121SKalle Valo }
1098e705c121SKalle Valo 
1099e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1100e705c121SKalle Valo {
1101e705c121SKalle Valo 	return trans->ops->read32(trans, ofs);
1102e705c121SKalle Valo }
1103e705c121SKalle Valo 
1104e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1105e705c121SKalle Valo {
1106e705c121SKalle Valo 	return trans->ops->read_prph(trans, ofs);
1107e705c121SKalle Valo }
1108e705c121SKalle Valo 
1109e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1110e705c121SKalle Valo 					u32 val)
1111e705c121SKalle Valo {
1112e705c121SKalle Valo 	return trans->ops->write_prph(trans, ofs, val);
1113e705c121SKalle Valo }
1114e705c121SKalle Valo 
1115e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1116e705c121SKalle Valo 				     void *buf, int dwords)
1117e705c121SKalle Valo {
1118e705c121SKalle Valo 	return trans->ops->read_mem(trans, addr, buf, dwords);
1119e705c121SKalle Valo }
1120e705c121SKalle Valo 
1121e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize)		      \
1122e705c121SKalle Valo 	do {								      \
1123e705c121SKalle Valo 		if (__builtin_constant_p(bufsize))			      \
1124e705c121SKalle Valo 			BUILD_BUG_ON((bufsize) % sizeof(u32));		      \
1125e705c121SKalle Valo 		iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1126e705c121SKalle Valo 	} while (0)
1127e705c121SKalle Valo 
1128e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1129e705c121SKalle Valo {
1130e705c121SKalle Valo 	u32 value;
1131e705c121SKalle Valo 
1132e705c121SKalle Valo 	if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1133e705c121SKalle Valo 		return 0xa5a5a5a5;
1134e705c121SKalle Valo 
1135e705c121SKalle Valo 	return value;
1136e705c121SKalle Valo }
1137e705c121SKalle Valo 
1138e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1139e705c121SKalle Valo 				      const void *buf, int dwords)
1140e705c121SKalle Valo {
1141e705c121SKalle Valo 	return trans->ops->write_mem(trans, addr, buf, dwords);
1142e705c121SKalle Valo }
1143e705c121SKalle Valo 
1144e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1145e705c121SKalle Valo 					u32 val)
1146e705c121SKalle Valo {
1147e705c121SKalle Valo 	return iwl_trans_write_mem(trans, addr, &val, 1);
1148e705c121SKalle Valo }
1149e705c121SKalle Valo 
1150e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1151e705c121SKalle Valo {
1152e705c121SKalle Valo 	if (trans->ops->set_pmi)
1153e705c121SKalle Valo 		trans->ops->set_pmi(trans, state);
1154e705c121SKalle Valo }
1155e705c121SKalle Valo 
1156e705c121SKalle Valo static inline void
1157e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1158e705c121SKalle Valo {
1159e705c121SKalle Valo 	trans->ops->set_bits_mask(trans, reg, mask, value);
1160e705c121SKalle Valo }
1161e705c121SKalle Valo 
1162e705c121SKalle Valo #define iwl_trans_grab_nic_access(trans, silent, flags)	\
1163e705c121SKalle Valo 	__cond_lock(nic_access,				\
1164e705c121SKalle Valo 		    likely((trans)->ops->grab_nic_access(trans, silent, flags)))
1165e705c121SKalle Valo 
1166e705c121SKalle Valo static inline void __releases(nic_access)
1167e705c121SKalle Valo iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
1168e705c121SKalle Valo {
1169e705c121SKalle Valo 	trans->ops->release_nic_access(trans, flags);
1170e705c121SKalle Valo 	__release(nic_access);
1171e705c121SKalle Valo }
1172e705c121SKalle Valo 
1173e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans)
1174e705c121SKalle Valo {
1175e705c121SKalle Valo 	if (WARN_ON_ONCE(!trans->op_mode))
1176e705c121SKalle Valo 		return;
1177e705c121SKalle Valo 
1178e705c121SKalle Valo 	/* prevent double restarts due to the same erroneous FW */
1179e705c121SKalle Valo 	if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status))
1180e705c121SKalle Valo 		iwl_op_mode_nic_error(trans->op_mode);
1181e705c121SKalle Valo }
1182e705c121SKalle Valo 
1183e705c121SKalle Valo /*****************************************************
1184e705c121SKalle Valo  * transport helper functions
1185e705c121SKalle Valo  *****************************************************/
1186e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1187e705c121SKalle Valo 				  struct device *dev,
1188e705c121SKalle Valo 				  const struct iwl_cfg *cfg,
1189e705c121SKalle Valo 				  const struct iwl_trans_ops *ops,
1190e705c121SKalle Valo 				  size_t dev_cmd_headroom);
1191e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans);
1192e705c121SKalle Valo 
1193e705c121SKalle Valo /*****************************************************
1194e705c121SKalle Valo * driver (transport) register/unregister functions
1195e705c121SKalle Valo ******************************************************/
1196e705c121SKalle Valo int __must_check iwl_pci_register_driver(void);
1197e705c121SKalle Valo void iwl_pci_unregister_driver(void);
1198e705c121SKalle Valo 
1199e705c121SKalle Valo #endif /* __iwl_trans_h__ */
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