1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 106b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 336b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #ifndef __iwl_trans_h__ 65e705c121SKalle Valo #define __iwl_trans_h__ 66e705c121SKalle Valo 67e705c121SKalle Valo #include <linux/ieee80211.h> 68e705c121SKalle Valo #include <linux/mm.h> /* for page_address */ 69e705c121SKalle Valo #include <linux/lockdep.h> 7039bdb17eSSharon Dvir #include <linux/kernel.h> 71e705c121SKalle Valo 72e705c121SKalle Valo #include "iwl-debug.h" 73e705c121SKalle Valo #include "iwl-config.h" 74d962f9b1SJohannes Berg #include "fw/img.h" 75e705c121SKalle Valo #include "iwl-op-mode.h" 76d172a5efSJohannes Berg #include "fw/api/cmdhdr.h" 77d172a5efSJohannes Berg #include "fw/api/txq.h" 78f14cda6fSSara Sharon #include "fw/api/dbg-tlv.h" 79f14cda6fSSara Sharon #include "iwl-dbg-tlv.h" 80e705c121SKalle Valo 81e705c121SKalle Valo /** 82e705c121SKalle Valo * DOC: Transport layer - what is it ? 83e705c121SKalle Valo * 84e705c121SKalle Valo * The transport layer is the layer that deals with the HW directly. It provides 85e705c121SKalle Valo * an abstraction of the underlying HW to the upper layer. The transport layer 86e705c121SKalle Valo * doesn't provide any policy, algorithm or anything of this kind, but only 87e705c121SKalle Valo * mechanisms to make the HW do something. It is not completely stateless but 88e705c121SKalle Valo * close to it. 89e705c121SKalle Valo * We will have an implementation for each different supported bus. 90e705c121SKalle Valo */ 91e705c121SKalle Valo 92e705c121SKalle Valo /** 93e705c121SKalle Valo * DOC: Life cycle of the transport layer 94e705c121SKalle Valo * 95e705c121SKalle Valo * The transport layer has a very precise life cycle. 96e705c121SKalle Valo * 97e705c121SKalle Valo * 1) A helper function is called during the module initialization and 98e705c121SKalle Valo * registers the bus driver's ops with the transport's alloc function. 99e705c121SKalle Valo * 2) Bus's probe calls to the transport layer's allocation functions. 100e705c121SKalle Valo * Of course this function is bus specific. 101e705c121SKalle Valo * 3) This allocation functions will spawn the upper layer which will 102e705c121SKalle Valo * register mac80211. 103e705c121SKalle Valo * 104e705c121SKalle Valo * 4) At some point (i.e. mac80211's start call), the op_mode will call 105e705c121SKalle Valo * the following sequence: 106e705c121SKalle Valo * start_hw 107e705c121SKalle Valo * start_fw 108e705c121SKalle Valo * 109e705c121SKalle Valo * 5) Then when finished (or reset): 110e705c121SKalle Valo * stop_device 111e705c121SKalle Valo * 112e705c121SKalle Valo * 6) Eventually, the free function will be called. 113e705c121SKalle Valo */ 114e705c121SKalle Valo 115e701da0cSLuca Coelho #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 116e701da0cSLuca Coelho 117e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 118e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID 0x55550000 119e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN 0x40 120fbe41127SSara Sharon #define FH_RSCSR_RPA_EN BIT(25) 1219d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN BIT(26) 122ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS 16 123ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK 0x3F0000 124e705c121SKalle Valo 125e705c121SKalle Valo struct iwl_rx_packet { 126e705c121SKalle Valo /* 127e705c121SKalle Valo * The first 4 bytes of the RX frame header contain both the RX frame 128e705c121SKalle Valo * size and some flags. 129e705c121SKalle Valo * Bit fields: 130e705c121SKalle Valo * 31: flag flush RB request 131e705c121SKalle Valo * 30: flag ignore TC (terminal counter) request 132e705c121SKalle Valo * 29: flag fast IRQ request 1339d0fc5a5SDavid Spinadel * 28-27: Reserved 1349d0fc5a5SDavid Spinadel * 26: RADA enabled 135fbe41127SSara Sharon * 25: Offload enabled 136ab2e696bSSara Sharon * 24: RPF enabled 137ab2e696bSSara Sharon * 23: RSS enabled 138ab2e696bSSara Sharon * 22: Checksum enabled 139ab2e696bSSara Sharon * 21-16: RX queue 140ab2e696bSSara Sharon * 15-14: Reserved 141e705c121SKalle Valo * 13-00: RX frame size 142e705c121SKalle Valo */ 143e705c121SKalle Valo __le32 len_n_flags; 144e705c121SKalle Valo struct iwl_cmd_header hdr; 145e705c121SKalle Valo u8 data[]; 146e705c121SKalle Valo } __packed; 147e705c121SKalle Valo 148e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 149e705c121SKalle Valo { 150e705c121SKalle Valo return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 151e705c121SKalle Valo } 152e705c121SKalle Valo 153e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 154e705c121SKalle Valo { 155e705c121SKalle Valo return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 156e705c121SKalle Valo } 157e705c121SKalle Valo 158e705c121SKalle Valo /** 159e705c121SKalle Valo * enum CMD_MODE - how to send the host commands ? 160e705c121SKalle Valo * 161e705c121SKalle Valo * @CMD_ASYNC: Return right away and don't wait for the response 162e705c121SKalle Valo * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 163e705c121SKalle Valo * the response. The caller needs to call iwl_free_resp when done. 164dcbb4746SEmmanuel Grumbach * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 165dcbb4746SEmmanuel Grumbach * called after this command completes. Valid only with CMD_ASYNC. 166e705c121SKalle Valo */ 167e705c121SKalle Valo enum CMD_MODE { 168e705c121SKalle Valo CMD_ASYNC = BIT(0), 169e705c121SKalle Valo CMD_WANT_SKB = BIT(1), 170e705c121SKalle Valo CMD_SEND_IN_RFKILL = BIT(2), 171043fa901SEmmanuel Grumbach CMD_WANT_ASYNC_CALLBACK = BIT(3), 172e705c121SKalle Valo }; 173e705c121SKalle Valo 174e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320 175e705c121SKalle Valo 176e705c121SKalle Valo /** 177e705c121SKalle Valo * struct iwl_device_cmd 178e705c121SKalle Valo * 179e705c121SKalle Valo * For allocation of the command and tx queues, this establishes the overall 180e705c121SKalle Valo * size of the largest command we send to uCode, except for commands that 181e705c121SKalle Valo * aren't fully copied and use other TFD space. 182e705c121SKalle Valo */ 183e705c121SKalle Valo struct iwl_device_cmd { 184e705c121SKalle Valo union { 185e705c121SKalle Valo struct { 186e705c121SKalle Valo struct iwl_cmd_header hdr; /* uCode API */ 187e705c121SKalle Valo u8 payload[DEF_CMD_PAYLOAD_SIZE]; 188e705c121SKalle Valo }; 189e705c121SKalle Valo struct { 190e705c121SKalle Valo struct iwl_cmd_header_wide hdr_wide; 191e705c121SKalle Valo u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 192e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide) + 193e705c121SKalle Valo sizeof(struct iwl_cmd_header)]; 194e705c121SKalle Valo }; 195e705c121SKalle Valo }; 196e705c121SKalle Valo } __packed; 197e705c121SKalle Valo 198a89c72ffSJohannes Berg /** 199a89c72ffSJohannes Berg * struct iwl_device_tx_cmd - buffer for TX command 200a89c72ffSJohannes Berg * @hdr: the header 201a89c72ffSJohannes Berg * @payload: the payload placeholder 202a89c72ffSJohannes Berg * 203a89c72ffSJohannes Berg * The actual structure is sized dynamically according to need. 204a89c72ffSJohannes Berg */ 205a89c72ffSJohannes Berg struct iwl_device_tx_cmd { 206a89c72ffSJohannes Berg struct iwl_cmd_header hdr; 207a89c72ffSJohannes Berg u8 payload[]; 208a89c72ffSJohannes Berg } __packed; 209a89c72ffSJohannes Berg 210e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 211e705c121SKalle Valo 212e705c121SKalle Valo /* 213e705c121SKalle Valo * number of transfer buffers (fragments) per transmit frame descriptor; 214e705c121SKalle Valo * this is just the driver's idea, the hardware supports 20 215e705c121SKalle Valo */ 216e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD 2 217e705c121SKalle Valo 218885375d0SMordechay Goodstein /* We need 2 entries for the TX command and header, and another one might 219885375d0SMordechay Goodstein * be needed for potential data in the SKB's head. The remaining ones can 220885375d0SMordechay Goodstein * be used for frags. 221885375d0SMordechay Goodstein */ 222885375d0SMordechay Goodstein #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 223885375d0SMordechay Goodstein 224e705c121SKalle Valo /** 225b8aed81cSJohannes Berg * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 226e705c121SKalle Valo * 227e705c121SKalle Valo * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 228e705c121SKalle Valo * ring. The transport layer doesn't map the command's buffer to DMA, but 229e705c121SKalle Valo * rather copies it to a previously allocated DMA buffer. This flag tells 230e705c121SKalle Valo * the transport layer not to copy the command, but to map the existing 231e705c121SKalle Valo * buffer (that is passed in) instead. This saves the memcpy and allows 232e705c121SKalle Valo * commands that are bigger than the fixed buffer to be submitted. 233e705c121SKalle Valo * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 234e705c121SKalle Valo * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 235e705c121SKalle Valo * chunk internally and free it again after the command completes. This 236e705c121SKalle Valo * can (currently) be used only once per command. 237e705c121SKalle Valo * Note that a TFD entry after a DUP one cannot be a normal copied one. 238e705c121SKalle Valo */ 239e705c121SKalle Valo enum iwl_hcmd_dataflag { 240e705c121SKalle Valo IWL_HCMD_DFL_NOCOPY = BIT(0), 241e705c121SKalle Valo IWL_HCMD_DFL_DUP = BIT(1), 242e705c121SKalle Valo }; 243e705c121SKalle Valo 24422463857SShahar S Matityahu enum iwl_error_event_table_status { 24522463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 24622463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 24722463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 24822463857SShahar S Matityahu }; 24922463857SShahar S Matityahu 250e705c121SKalle Valo /** 251e705c121SKalle Valo * struct iwl_host_cmd - Host command to the uCode 252e705c121SKalle Valo * 253e705c121SKalle Valo * @data: array of chunks that composes the data of the host command 254e705c121SKalle Valo * @resp_pkt: response packet, if %CMD_WANT_SKB was set 255e705c121SKalle Valo * @_rx_page_order: (internally used to free response packet) 256e705c121SKalle Valo * @_rx_page_addr: (internally used to free response packet) 257e705c121SKalle Valo * @flags: can be CMD_* 258e705c121SKalle Valo * @len: array of the lengths of the chunks in data 259e705c121SKalle Valo * @dataflags: IWL_HCMD_DFL_* 260e705c121SKalle Valo * @id: command id of the host command, for wide commands encoding the 261e705c121SKalle Valo * version and group as well 262e705c121SKalle Valo */ 263e705c121SKalle Valo struct iwl_host_cmd { 264e705c121SKalle Valo const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 265e705c121SKalle Valo struct iwl_rx_packet *resp_pkt; 266e705c121SKalle Valo unsigned long _rx_page_addr; 267e705c121SKalle Valo u32 _rx_page_order; 268e705c121SKalle Valo 269e705c121SKalle Valo u32 flags; 270e705c121SKalle Valo u32 id; 271e705c121SKalle Valo u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 272e705c121SKalle Valo u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 273e705c121SKalle Valo }; 274e705c121SKalle Valo 275e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 276e705c121SKalle Valo { 277e705c121SKalle Valo free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 278e705c121SKalle Valo } 279e705c121SKalle Valo 280e705c121SKalle Valo struct iwl_rx_cmd_buffer { 281e705c121SKalle Valo struct page *_page; 282e705c121SKalle Valo int _offset; 283e705c121SKalle Valo bool _page_stolen; 284e705c121SKalle Valo u32 _rx_page_order; 285e705c121SKalle Valo unsigned int truesize; 286e705c121SKalle Valo }; 287e705c121SKalle Valo 288e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 289e705c121SKalle Valo { 290e705c121SKalle Valo return (void *)((unsigned long)page_address(r->_page) + r->_offset); 291e705c121SKalle Valo } 292e705c121SKalle Valo 293e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 294e705c121SKalle Valo { 295e705c121SKalle Valo return r->_offset; 296e705c121SKalle Valo } 297e705c121SKalle Valo 298e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 299e705c121SKalle Valo { 300e705c121SKalle Valo r->_page_stolen = true; 301e705c121SKalle Valo get_page(r->_page); 302e705c121SKalle Valo return r->_page; 303e705c121SKalle Valo } 304e705c121SKalle Valo 305e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 306e705c121SKalle Valo { 307e705c121SKalle Valo __free_pages(r->_page, r->_rx_page_order); 308e705c121SKalle Valo } 309e705c121SKalle Valo 310e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS 6 311e705c121SKalle Valo 312e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 313e705c121SKalle Valo 314e705c121SKalle Valo /* 315e705c121SKalle Valo * Maximum number of HW queues the transport layer 316e705c121SKalle Valo * currently supports 317e705c121SKalle Valo */ 318e705c121SKalle Valo #define IWL_MAX_HW_QUEUES 32 319e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES 512 320e982bc2cSSara Sharon 321e705c121SKalle Valo #define IWL_MAX_TID_COUNT 8 322c65f4e03SSara Sharon #define IWL_MGMT_TID 15 323e705c121SKalle Valo #define IWL_FRAME_LIMIT 64 324e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES 16 3250cd38f4dSMordechay Goodstein #define IWL_9000_MAX_RX_HW_QUEUES 6 326e705c121SKalle Valo 327e705c121SKalle Valo /** 328e705c121SKalle Valo * enum iwl_wowlan_status - WoWLAN image/device status 329e705c121SKalle Valo * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 330e705c121SKalle Valo * @IWL_D3_STATUS_RESET: device was reset while suspended 331e705c121SKalle Valo */ 332e705c121SKalle Valo enum iwl_d3_status { 333e705c121SKalle Valo IWL_D3_STATUS_ALIVE, 334e705c121SKalle Valo IWL_D3_STATUS_RESET, 335e705c121SKalle Valo }; 336e705c121SKalle Valo 337e705c121SKalle Valo /** 338e705c121SKalle Valo * enum iwl_trans_status: transport status flags 339e705c121SKalle Valo * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 340e705c121SKalle Valo * @STATUS_DEVICE_ENABLED: APM is enabled 341e705c121SKalle Valo * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 342e705c121SKalle Valo * @STATUS_INT_ENABLED: interrupts are enabled 343326477e4SJohannes Berg * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 344326477e4SJohannes Berg * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 345e705c121SKalle Valo * @STATUS_FW_ERROR: the fw is in error state 346e705c121SKalle Valo * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 347e705c121SKalle Valo * are sent 348e705c121SKalle Valo * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 349e705c121SKalle Valo * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 350e705c121SKalle Valo */ 351e705c121SKalle Valo enum iwl_trans_status { 352e705c121SKalle Valo STATUS_SYNC_HCMD_ACTIVE, 353e705c121SKalle Valo STATUS_DEVICE_ENABLED, 354e705c121SKalle Valo STATUS_TPOWER_PMI, 355e705c121SKalle Valo STATUS_INT_ENABLED, 356326477e4SJohannes Berg STATUS_RFKILL_HW, 357326477e4SJohannes Berg STATUS_RFKILL_OPMODE, 358e705c121SKalle Valo STATUS_FW_ERROR, 359e705c121SKalle Valo STATUS_TRANS_GOING_IDLE, 360e705c121SKalle Valo STATUS_TRANS_IDLE, 361e705c121SKalle Valo STATUS_TRANS_DEAD, 362e705c121SKalle Valo }; 363e705c121SKalle Valo 3646c4fbcbcSEmmanuel Grumbach static inline int 3656c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 3666c4fbcbcSEmmanuel Grumbach { 3676c4fbcbcSEmmanuel Grumbach switch (rb_size) { 3681a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 3691a4968d1SGolan Ben Ami return get_order(2 * 1024); 3706c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 3716c4fbcbcSEmmanuel Grumbach return get_order(4 * 1024); 3726c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 3736c4fbcbcSEmmanuel Grumbach return get_order(8 * 1024); 3746c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 3756c4fbcbcSEmmanuel Grumbach return get_order(12 * 1024); 3766c4fbcbcSEmmanuel Grumbach default: 3776c4fbcbcSEmmanuel Grumbach WARN_ON(1); 3786c4fbcbcSEmmanuel Grumbach return -1; 3796c4fbcbcSEmmanuel Grumbach } 3806c4fbcbcSEmmanuel Grumbach } 3816c4fbcbcSEmmanuel Grumbach 38280084e35SJohannes Berg static inline int 38380084e35SJohannes Berg iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 38480084e35SJohannes Berg { 38580084e35SJohannes Berg switch (rb_size) { 38680084e35SJohannes Berg case IWL_AMSDU_2K: 38780084e35SJohannes Berg return 2 * 1024; 38880084e35SJohannes Berg case IWL_AMSDU_4K: 38980084e35SJohannes Berg return 4 * 1024; 39080084e35SJohannes Berg case IWL_AMSDU_8K: 39180084e35SJohannes Berg return 8 * 1024; 39280084e35SJohannes Berg case IWL_AMSDU_12K: 39380084e35SJohannes Berg return 12 * 1024; 39480084e35SJohannes Berg default: 39580084e35SJohannes Berg WARN_ON(1); 39680084e35SJohannes Berg return 0; 39780084e35SJohannes Berg } 39880084e35SJohannes Berg } 39980084e35SJohannes Berg 40039bdb17eSSharon Dvir struct iwl_hcmd_names { 40139bdb17eSSharon Dvir u8 cmd_id; 40239bdb17eSSharon Dvir const char *const cmd_name; 40339bdb17eSSharon Dvir }; 40439bdb17eSSharon Dvir 40539bdb17eSSharon Dvir #define HCMD_NAME(x) \ 40639bdb17eSSharon Dvir { .cmd_id = x, .cmd_name = #x } 40739bdb17eSSharon Dvir 40839bdb17eSSharon Dvir struct iwl_hcmd_arr { 40939bdb17eSSharon Dvir const struct iwl_hcmd_names *arr; 41039bdb17eSSharon Dvir int size; 41139bdb17eSSharon Dvir }; 41239bdb17eSSharon Dvir 41339bdb17eSSharon Dvir #define HCMD_ARR(x) \ 41439bdb17eSSharon Dvir { .arr = x, .size = ARRAY_SIZE(x) } 41539bdb17eSSharon Dvir 416e705c121SKalle Valo /** 417e705c121SKalle Valo * struct iwl_trans_config - transport configuration 418e705c121SKalle Valo * 419e705c121SKalle Valo * @op_mode: pointer to the upper layer. 420e705c121SKalle Valo * @cmd_queue: the index of the command queue. 421e705c121SKalle Valo * Must be set before start_fw. 422e705c121SKalle Valo * @cmd_fifo: the fifo for host commands 423e705c121SKalle Valo * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 424e705c121SKalle Valo * @no_reclaim_cmds: Some devices erroneously don't set the 425e705c121SKalle Valo * SEQ_RX_FRAME bit on some notifications, this is the 426e705c121SKalle Valo * list of such notifications to filter. Max length is 427e705c121SKalle Valo * %MAX_NO_RECLAIM_CMDS. 428e705c121SKalle Valo * @n_no_reclaim_cmds: # of commands in list 4296c4fbcbcSEmmanuel Grumbach * @rx_buf_size: RX buffer size needed for A-MSDUs 430e705c121SKalle Valo * if unset 4k will be the RX buffer size 431e705c121SKalle Valo * @bc_table_dword: set to true if the BC table expects the byte count to be 432e705c121SKalle Valo * in DWORD (as opposed to bytes) 433e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 43441837ca9SEmmanuel Grumbach * @sw_csum_tx: transport should compute the TCP checksum 43539bdb17eSSharon Dvir * @command_groups: array of command groups, each member is an array of the 43639bdb17eSSharon Dvir * commands in the group; for debugging only 43739bdb17eSSharon Dvir * @command_groups_size: number of command groups, to avoid illegal access 43821cb3222SJohannes Berg * @cb_data_offs: offset inside skb->cb to store transport data at, must have 43921cb3222SJohannes Berg * space for at least two pointers 440e705c121SKalle Valo */ 441e705c121SKalle Valo struct iwl_trans_config { 442e705c121SKalle Valo struct iwl_op_mode *op_mode; 443e705c121SKalle Valo 444e705c121SKalle Valo u8 cmd_queue; 445e705c121SKalle Valo u8 cmd_fifo; 446e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 447e705c121SKalle Valo const u8 *no_reclaim_cmds; 448e705c121SKalle Valo unsigned int n_no_reclaim_cmds; 449e705c121SKalle Valo 4506c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 451e705c121SKalle Valo bool bc_table_dword; 452e705c121SKalle Valo bool scd_set_active; 45341837ca9SEmmanuel Grumbach bool sw_csum_tx; 45439bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 45539bdb17eSSharon Dvir int command_groups_size; 456e705c121SKalle Valo 45721cb3222SJohannes Berg u8 cb_data_offs; 458e705c121SKalle Valo }; 459e705c121SKalle Valo 460e705c121SKalle Valo struct iwl_trans_dump_data { 461e705c121SKalle Valo u32 len; 462e705c121SKalle Valo u8 data[]; 463e705c121SKalle Valo }; 464e705c121SKalle Valo 465e705c121SKalle Valo struct iwl_trans; 466e705c121SKalle Valo 467e705c121SKalle Valo struct iwl_trans_txq_scd_cfg { 468e705c121SKalle Valo u8 fifo; 4692a2e9d10SLiad Kaufman u8 sta_id; 470e705c121SKalle Valo u8 tid; 471e705c121SKalle Valo bool aggregate; 472e705c121SKalle Valo int frame_limit; 473e705c121SKalle Valo }; 474e705c121SKalle Valo 4756b35ff91SSara Sharon /** 47692536c96SSara Sharon * struct iwl_trans_rxq_dma_data - RX queue DMA data 47792536c96SSara Sharon * @fr_bd_cb: DMA address of free BD cyclic buffer 47892536c96SSara Sharon * @fr_bd_wid: Initial write index of the free BD cyclic buffer 47992536c96SSara Sharon * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 48092536c96SSara Sharon * @ur_bd_cb: DMA address of used BD cyclic buffer 48192536c96SSara Sharon */ 48292536c96SSara Sharon struct iwl_trans_rxq_dma_data { 48392536c96SSara Sharon u64 fr_bd_cb; 48492536c96SSara Sharon u32 fr_bd_wid; 48592536c96SSara Sharon u64 urbd_stts_wrptr; 48692536c96SSara Sharon u64 ur_bd_cb; 48792536c96SSara Sharon }; 48892536c96SSara Sharon 48992536c96SSara Sharon /** 490e705c121SKalle Valo * struct iwl_trans_ops - transport specific operations 491e705c121SKalle Valo * 492e705c121SKalle Valo * All the handlers MUST be implemented 493e705c121SKalle Valo * 494bab3cb92SEmmanuel Grumbach * @start_hw: starts the HW. From that point on, the HW can send interrupts. 495bab3cb92SEmmanuel Grumbach * May sleep. 496e705c121SKalle Valo * @op_mode_leave: Turn off the HW RF kill indication if on 497e705c121SKalle Valo * May sleep 498e705c121SKalle Valo * @start_fw: allocates and inits all the resources for the transport 499e705c121SKalle Valo * layer. Also kick a fw image. 500e705c121SKalle Valo * May sleep 501e705c121SKalle Valo * @fw_alive: called when the fw sends alive notification. If the fw provides 502e705c121SKalle Valo * the SCD base address in SRAM, then provide it here, or 0 otherwise. 503e705c121SKalle Valo * May sleep 504e705c121SKalle Valo * @stop_device: stops the whole device (embedded CPU put to reset) and stops 505bab3cb92SEmmanuel Grumbach * the HW. From that point on, the HW will be stopped but will still issue 506bab3cb92SEmmanuel Grumbach * an interrupt if the HW RF kill switch is triggered. 507e705c121SKalle Valo * This callback must do the right thing and not crash even if %start_hw() 508e705c121SKalle Valo * was called but not &start_fw(). May sleep. 509e705c121SKalle Valo * @d3_suspend: put the device into the correct mode for WoWLAN during 510e705c121SKalle Valo * suspend. This is optional, if not implemented WoWLAN will not be 511e705c121SKalle Valo * supported. This callback may sleep. 512e705c121SKalle Valo * @d3_resume: resume the device after WoWLAN, enabling the opmode to 513e705c121SKalle Valo * talk to the WoWLAN image to get its status. This is optional, if not 514e705c121SKalle Valo * implemented WoWLAN will not be supported. This callback may sleep. 515e705c121SKalle Valo * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 516e705c121SKalle Valo * If RFkill is asserted in the middle of a SYNC host command, it must 517e705c121SKalle Valo * return -ERFKILL straight away. 518e705c121SKalle Valo * May sleep only if CMD_ASYNC is not set 5193f73b8caSEmmanuel Grumbach * @tx: send an skb. The transport relies on the op_mode to zero the 5206eb5e529SEmmanuel Grumbach * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 5216eb5e529SEmmanuel Grumbach * the CSUM will be taken care of (TCP CSUM and IP header in case of 5226eb5e529SEmmanuel Grumbach * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 5236eb5e529SEmmanuel Grumbach * header if it is IPv4. 524e705c121SKalle Valo * Must be atomic 525e705c121SKalle Valo * @reclaim: free packet until ssn. Returns a list of freed packets. 526e705c121SKalle Valo * Must be atomic 527e705c121SKalle Valo * @txq_enable: setup a queue. To setup an AC queue, use the 528e705c121SKalle Valo * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 529e705c121SKalle Valo * this one. The op_mode must not configure the HCMD queue. The scheduler 530e705c121SKalle Valo * configuration may be %NULL, in which case the hardware will not be 531dcfbd67bSEmmanuel Grumbach * configured. If true is returned, the operation mode needs to increment 532dcfbd67bSEmmanuel Grumbach * the sequence number of the packets routed to this queue because of a 533dcfbd67bSEmmanuel Grumbach * hardware scheduler bug. May sleep. 534e705c121SKalle Valo * @txq_disable: de-configure a Tx queue to send AMPDUs 535e705c121SKalle Valo * Must be atomic 53642db09c1SLiad Kaufman * @txq_set_shared_mode: change Tx queue shared/unshared marking 537d6d517b7SSara Sharon * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 538d6d517b7SSara Sharon * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 539e705c121SKalle Valo * @freeze_txq_timer: prevents the timer of the queue from firing until the 540e705c121SKalle Valo * queue is set to awake. Must be atomic. 5410cd58eaaSEmmanuel Grumbach * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 5420cd58eaaSEmmanuel Grumbach * that the transport needs to refcount the calls since this function 5430cd58eaaSEmmanuel Grumbach * will be called several times with block = true, and then the queues 5440cd58eaaSEmmanuel Grumbach * need to be unblocked only after the same number of calls with 5450cd58eaaSEmmanuel Grumbach * block = false. 546e705c121SKalle Valo * @write8: write a u8 to a register at offset ofs from the BAR 547e705c121SKalle Valo * @write32: write a u32 to a register at offset ofs from the BAR 548e705c121SKalle Valo * @read32: read a u32 register at offset ofs from the BAR 549e705c121SKalle Valo * @read_prph: read a DWORD from a periphery register 550e705c121SKalle Valo * @write_prph: write a DWORD to a periphery register 551e705c121SKalle Valo * @read_mem: read device's SRAM in DWORD 552e705c121SKalle Valo * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 553e705c121SKalle Valo * will be zeroed. 554f696a7eeSLuca Coelho * @read_config32: read a u32 value from the device's config space at 555f696a7eeSLuca Coelho * the given offset. 556e705c121SKalle Valo * @configure: configure parameters required by the transport layer from 557e705c121SKalle Valo * the op_mode. May be called several times before start_fw, can't be 558e705c121SKalle Valo * called after that. 559e705c121SKalle Valo * @set_pmi: set the power pmi state 560e705c121SKalle Valo * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 561e705c121SKalle Valo * Sleeping is not allowed between grab_nic_access and 562e705c121SKalle Valo * release_nic_access. 563e705c121SKalle Valo * @release_nic_access: let the NIC go to sleep. The "flags" parameter 564e705c121SKalle Valo * must be the same one that was sent before to the grab_nic_access. 565e705c121SKalle Valo * @set_bits_mask - set SRAM register according to value and mask. 566e705c121SKalle Valo * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 567e705c121SKalle Valo * TX'ed commands and similar. The buffer will be vfree'd by the caller. 568e705c121SKalle Valo * Note that the transport must fill in the proper file headers. 569f7805b33SLior Cohen * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 570f7805b33SLior Cohen * of the trans debugfs 571a182dfabSLuca Coelho * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the 572a182dfabSLuca Coelho * context info. 573e705c121SKalle Valo */ 574e705c121SKalle Valo struct iwl_trans_ops { 575e705c121SKalle Valo 576bab3cb92SEmmanuel Grumbach int (*start_hw)(struct iwl_trans *iwl_trans); 577e705c121SKalle Valo void (*op_mode_leave)(struct iwl_trans *iwl_trans); 578e705c121SKalle Valo int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 579e705c121SKalle Valo bool run_in_rfkill); 580e705c121SKalle Valo void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 581bab3cb92SEmmanuel Grumbach void (*stop_device)(struct iwl_trans *trans); 582e705c121SKalle Valo 583e5f3f215SHaim Dreyfuss int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 584e705c121SKalle Valo int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 58523ae6128SMatti Gottlieb bool test, bool reset); 586e705c121SKalle Valo 587e705c121SKalle Valo int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 588e705c121SKalle Valo 589e705c121SKalle Valo int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 590a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue); 591e705c121SKalle Valo void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 592e705c121SKalle Valo struct sk_buff_head *skbs); 593e705c121SKalle Valo 594ba7136f3SAlex Malamud void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 595ba7136f3SAlex Malamud 596dcfbd67bSEmmanuel Grumbach bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 597e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 598e705c121SKalle Valo unsigned int queue_wdg_timeout); 599e705c121SKalle Valo void (*txq_disable)(struct iwl_trans *trans, int queue, 600e705c121SKalle Valo bool configure_scd); 6012f7a3863SLuca Coelho /* 22000 functions */ 6026b35ff91SSara Sharon int (*txq_alloc)(struct iwl_trans *trans, 6031169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 6045369774cSSara Sharon int cmd_id, int size, 6056b35ff91SSara Sharon unsigned int queue_wdg_timeout); 6066b35ff91SSara Sharon void (*txq_free)(struct iwl_trans *trans, int queue); 60792536c96SSara Sharon int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 60892536c96SSara Sharon struct iwl_trans_rxq_dma_data *data); 609e705c121SKalle Valo 61042db09c1SLiad Kaufman void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 61142db09c1SLiad Kaufman bool shared); 61242db09c1SLiad Kaufman 613a1a57877SSara Sharon int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 614d6d517b7SSara Sharon int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 615e705c121SKalle Valo void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 616e705c121SKalle Valo bool freeze); 6170cd58eaaSEmmanuel Grumbach void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 618e705c121SKalle Valo 619e705c121SKalle Valo void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 620e705c121SKalle Valo void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 621e705c121SKalle Valo u32 (*read32)(struct iwl_trans *trans, u32 ofs); 622e705c121SKalle Valo u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 623e705c121SKalle Valo void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 624e705c121SKalle Valo int (*read_mem)(struct iwl_trans *trans, u32 addr, 625e705c121SKalle Valo void *buf, int dwords); 626e705c121SKalle Valo int (*write_mem)(struct iwl_trans *trans, u32 addr, 627e705c121SKalle Valo const void *buf, int dwords); 628f696a7eeSLuca Coelho int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 629e705c121SKalle Valo void (*configure)(struct iwl_trans *trans, 630e705c121SKalle Valo const struct iwl_trans_config *trans_cfg); 631e705c121SKalle Valo void (*set_pmi)(struct iwl_trans *trans, bool state); 632870c2a11SGolan Ben Ami void (*sw_reset)(struct iwl_trans *trans); 63323ba9340SEmmanuel Grumbach bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags); 634e705c121SKalle Valo void (*release_nic_access)(struct iwl_trans *trans, 635e705c121SKalle Valo unsigned long *flags); 636e705c121SKalle Valo void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 637e705c121SKalle Valo u32 value); 638e705c121SKalle Valo int (*suspend)(struct iwl_trans *trans); 639e705c121SKalle Valo void (*resume)(struct iwl_trans *trans); 640e705c121SKalle Valo 641e705c121SKalle Valo struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 64279f033f6SSara Sharon u32 dump_mask); 643f7805b33SLior Cohen void (*debugfs_cleanup)(struct iwl_trans *trans); 644d1967ce6SShahar S Matityahu void (*sync_nmi)(struct iwl_trans *trans); 645a182dfabSLuca Coelho int (*set_pnvm)(struct iwl_trans *trans, const void *data, u32 len); 646e705c121SKalle Valo }; 647e705c121SKalle Valo 648e705c121SKalle Valo /** 649e705c121SKalle Valo * enum iwl_trans_state - state of the transport layer 650e705c121SKalle Valo * 651e705c121SKalle Valo * @IWL_TRANS_NO_FW: no fw has sent an alive response 652e705c121SKalle Valo * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response 653e705c121SKalle Valo */ 654e705c121SKalle Valo enum iwl_trans_state { 655e705c121SKalle Valo IWL_TRANS_NO_FW = 0, 656e705c121SKalle Valo IWL_TRANS_FW_ALIVE = 1, 657e705c121SKalle Valo }; 658e705c121SKalle Valo 659e705c121SKalle Valo /** 660b7282643SLuca Coelho * DOC: Platform power management 661e705c121SKalle Valo * 662b7282643SLuca Coelho * In system-wide power management the entire platform goes into a low 663b7282643SLuca Coelho * power state (e.g. idle or suspend to RAM) at the same time and the 664b7282643SLuca Coelho * device is configured as a wakeup source for the entire platform. 665b7282643SLuca Coelho * This is usually triggered by userspace activity (e.g. the user 666b7282643SLuca Coelho * presses the suspend button or a power management daemon decides to 667b7282643SLuca Coelho * put the platform in low power mode). The device's behavior in this 668b7282643SLuca Coelho * mode is dictated by the wake-on-WLAN configuration. 669b7282643SLuca Coelho * 670b7282643SLuca Coelho * The terms used for the device's behavior are as follows: 671b7282643SLuca Coelho * 672b7282643SLuca Coelho * - D0: the device is fully powered and the host is awake; 673b7282643SLuca Coelho * - D3: the device is in low power mode and only reacts to 674b7282643SLuca Coelho * specific events (e.g. magic-packet received or scan 675b7282643SLuca Coelho * results found); 676b7282643SLuca Coelho * 677b7282643SLuca Coelho * These terms reflect the power modes in the firmware and are not to 678f60e2750SEmmanuel Grumbach * be confused with the physical device power state. 679e705c121SKalle Valo */ 680b7282643SLuca Coelho 681b7282643SLuca Coelho /** 682b7282643SLuca Coelho * enum iwl_plat_pm_mode - platform power management mode 683b7282643SLuca Coelho * 684b7282643SLuca Coelho * This enumeration describes the device's platform power management 685f60e2750SEmmanuel Grumbach * behavior when in system-wide suspend (i.e WoWLAN). 686b7282643SLuca Coelho * 687b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 688f60e2750SEmmanuel Grumbach * device. In system-wide suspend mode, it means that the all 689f60e2750SEmmanuel Grumbach * connections will be closed automatically by mac80211 before 690f60e2750SEmmanuel Grumbach * the platform is suspended. 691b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 692b7282643SLuca Coelho */ 693b7282643SLuca Coelho enum iwl_plat_pm_mode { 694b7282643SLuca Coelho IWL_PLAT_PM_MODE_DISABLED, 695b7282643SLuca Coelho IWL_PLAT_PM_MODE_D3, 696e705c121SKalle Valo }; 697e705c121SKalle Valo 698341bd290SShahar S Matityahu /** 699341bd290SShahar S Matityahu * enum iwl_ini_cfg_state 700341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 701341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 702341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 703341bd290SShahar S Matityahu * are corrupted. The rest of the debug TLVs will still be used 704341bd290SShahar S Matityahu */ 705341bd290SShahar S Matityahu enum iwl_ini_cfg_state { 706341bd290SShahar S Matityahu IWL_INI_CFG_STATE_NOT_LOADED, 707341bd290SShahar S Matityahu IWL_INI_CFG_STATE_LOADED, 708341bd290SShahar S Matityahu IWL_INI_CFG_STATE_CORRUPTED, 709341bd290SShahar S Matityahu }; 710341bd290SShahar S Matityahu 711b8a7547dSShahar S Matityahu /* Max time to wait for nmi interrupt */ 712b8a7547dSShahar S Matityahu #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 713b8a7547dSShahar S Matityahu 71488964b2eSSara Sharon /** 71588964b2eSSara Sharon * struct iwl_dram_data 71688964b2eSSara Sharon * @physical: page phy pointer 71788964b2eSSara Sharon * @block: pointer to the allocated block/page 71888964b2eSSara Sharon * @size: size of the block/page 71988964b2eSSara Sharon */ 72088964b2eSSara Sharon struct iwl_dram_data { 72188964b2eSSara Sharon dma_addr_t physical; 72288964b2eSSara Sharon void *block; 72388964b2eSSara Sharon int size; 72488964b2eSSara Sharon }; 7254cbb8e50SLuciano Coelho 726e705c121SKalle Valo /** 727593fae3eSShahar S Matityahu * struct iwl_fw_mon - fw monitor per allocation id 728593fae3eSShahar S Matityahu * @num_frags: number of fragments 729593fae3eSShahar S Matityahu * @frags: an array of DRAM buffer fragments 730593fae3eSShahar S Matityahu */ 731593fae3eSShahar S Matityahu struct iwl_fw_mon { 732593fae3eSShahar S Matityahu u32 num_frags; 733593fae3eSShahar S Matityahu struct iwl_dram_data *frags; 734593fae3eSShahar S Matityahu }; 735593fae3eSShahar S Matityahu 736593fae3eSShahar S Matityahu /** 737505a00c0SShahar S Matityahu * struct iwl_self_init_dram - dram data used by self init process 738505a00c0SShahar S Matityahu * @fw: lmac and umac dram data 739505a00c0SShahar S Matityahu * @fw_cnt: total number of items in array 740505a00c0SShahar S Matityahu * @paging: paging dram data 741505a00c0SShahar S Matityahu * @paging_cnt: total number of items in array 742505a00c0SShahar S Matityahu */ 743505a00c0SShahar S Matityahu struct iwl_self_init_dram { 744505a00c0SShahar S Matityahu struct iwl_dram_data *fw; 745505a00c0SShahar S Matityahu int fw_cnt; 746505a00c0SShahar S Matityahu struct iwl_dram_data *paging; 747505a00c0SShahar S Matityahu int paging_cnt; 748505a00c0SShahar S Matityahu }; 749505a00c0SShahar S Matityahu 750505a00c0SShahar S Matityahu /** 75191c28b83SShahar S Matityahu * struct iwl_trans_debug - transport debug related data 75291c28b83SShahar S Matityahu * 75391c28b83SShahar S Matityahu * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 75491c28b83SShahar S Matityahu * @rec_on: true iff there is a fw debug recording currently active 75591c28b83SShahar S Matityahu * @dest_tlv: points to the destination TLV for debug 75691c28b83SShahar S Matityahu * @conf_tlv: array of pointers to configuration TLVs for debug 75791c28b83SShahar S Matityahu * @trigger_tlv: array of pointers to triggers TLVs for debug 75891c28b83SShahar S Matityahu * @lmac_error_event_table: addrs of lmacs error tables 75991c28b83SShahar S Matityahu * @umac_error_event_table: addr of umac error table 76091c28b83SShahar S Matityahu * @error_event_table_tlv_status: bitmap that indicates what error table 76191c28b83SShahar S Matityahu * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 762341bd290SShahar S Matityahu * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 763341bd290SShahar S Matityahu * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 764593fae3eSShahar S Matityahu * @fw_mon_cfg: debug buffer allocation configuration 765593fae3eSShahar S Matityahu * @fw_mon_ini: DRAM buffer fragments per allocation id 76669f0e505SShahar S Matityahu * @fw_mon: DRAM buffer for firmware monitor 76791c28b83SShahar S Matityahu * @hw_error: equals true if hw error interrupt was received from the FW 768029c25f3SShahar S Matityahu * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 7693b589d56SShahar S Matityahu * @active_regions: active regions 770677d25b2SShahar S Matityahu * @debug_info_tlv_list: list of debug info TLVs 771a9248de4SShahar S Matityahu * @time_point: array of debug time points 77260e8abd9SShahar S Matityahu * @periodic_trig_list: periodic triggers list 773cf29c5b6SShahar S Matityahu * @domains_bitmap: bitmap of active domains other than 774cf29c5b6SShahar S Matityahu * &IWL_FW_INI_DOMAIN_ALWAYS_ON 77591c28b83SShahar S Matityahu */ 77691c28b83SShahar S Matityahu struct iwl_trans_debug { 77791c28b83SShahar S Matityahu u8 n_dest_reg; 77891c28b83SShahar S Matityahu bool rec_on; 77991c28b83SShahar S Matityahu 78091c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 78191c28b83SShahar S Matityahu const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 78291c28b83SShahar S Matityahu struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 78391c28b83SShahar S Matityahu 78491c28b83SShahar S Matityahu u32 lmac_error_event_table[2]; 78591c28b83SShahar S Matityahu u32 umac_error_event_table; 78691c28b83SShahar S Matityahu unsigned int error_event_table_tlv_status; 78791c28b83SShahar S Matityahu 788341bd290SShahar S Matityahu enum iwl_ini_cfg_state internal_ini_cfg; 789341bd290SShahar S Matityahu enum iwl_ini_cfg_state external_ini_cfg; 79091c28b83SShahar S Matityahu 791593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 792593fae3eSShahar S Matityahu struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 793593fae3eSShahar S Matityahu 79469f0e505SShahar S Matityahu struct iwl_dram_data fw_mon; 79591c28b83SShahar S Matityahu 79691c28b83SShahar S Matityahu bool hw_error; 797029c25f3SShahar S Matityahu enum iwl_fw_ini_buffer_location ini_dest; 7983b589d56SShahar S Matityahu 7993b589d56SShahar S Matityahu struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 800677d25b2SShahar S Matityahu struct list_head debug_info_tlv_list; 801a9248de4SShahar S Matityahu struct iwl_dbg_tlv_time_point_data 802a9248de4SShahar S Matityahu time_point[IWL_FW_INI_TIME_POINT_NUM]; 80360e8abd9SShahar S Matityahu struct list_head periodic_trig_list; 804cf29c5b6SShahar S Matityahu 805cf29c5b6SShahar S Matityahu u32 domains_bitmap; 80691c28b83SShahar S Matityahu }; 80791c28b83SShahar S Matityahu 8084807e736SMordechay Goodstein struct iwl_dma_ptr { 8094807e736SMordechay Goodstein dma_addr_t dma; 8104807e736SMordechay Goodstein void *addr; 8114807e736SMordechay Goodstein size_t size; 8124807e736SMordechay Goodstein }; 8134807e736SMordechay Goodstein 8144807e736SMordechay Goodstein struct iwl_cmd_meta { 8154807e736SMordechay Goodstein /* only for SYNC commands, iff the reply skb is wanted */ 8164807e736SMordechay Goodstein struct iwl_host_cmd *source; 8174807e736SMordechay Goodstein u32 flags; 8184807e736SMordechay Goodstein u32 tbs; 8194807e736SMordechay Goodstein }; 8204807e736SMordechay Goodstein 8214807e736SMordechay Goodstein /* 8224807e736SMordechay Goodstein * The FH will write back to the first TB only, so we need to copy some data 8234807e736SMordechay Goodstein * into the buffer regardless of whether it should be mapped or not. 8244807e736SMordechay Goodstein * This indicates how big the first TB must be to include the scratch buffer 8254807e736SMordechay Goodstein * and the assigned PN. 8264807e736SMordechay Goodstein * Since PN location is 8 bytes at offset 12, it's 20 now. 8274807e736SMordechay Goodstein * If we make it bigger then allocations will be bigger and copy slower, so 8284807e736SMordechay Goodstein * that's probably not useful. 8294807e736SMordechay Goodstein */ 8304807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE 20 8314807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 8324807e736SMordechay Goodstein 8334807e736SMordechay Goodstein struct iwl_pcie_txq_entry { 8344807e736SMordechay Goodstein void *cmd; 8354807e736SMordechay Goodstein struct sk_buff *skb; 8364807e736SMordechay Goodstein /* buffer to free after command completes */ 8374807e736SMordechay Goodstein const void *free_buf; 8384807e736SMordechay Goodstein struct iwl_cmd_meta meta; 8394807e736SMordechay Goodstein }; 8404807e736SMordechay Goodstein 8414807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf { 8424807e736SMordechay Goodstein u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 8434807e736SMordechay Goodstein }; 8444807e736SMordechay Goodstein 8454807e736SMordechay Goodstein /** 8464807e736SMordechay Goodstein * struct iwl_txq - Tx Queue for DMA 8474807e736SMordechay Goodstein * @q: generic Rx/Tx queue descriptor 8484807e736SMordechay Goodstein * @tfds: transmit frame descriptors (DMA memory) 8494807e736SMordechay Goodstein * @first_tb_bufs: start of command headers, including scratch buffers, for 8504807e736SMordechay Goodstein * the writeback -- this is DMA memory and an array holding one buffer 8514807e736SMordechay Goodstein * for each command on the queue 8524807e736SMordechay Goodstein * @first_tb_dma: DMA address for the first_tb_bufs start 8534807e736SMordechay Goodstein * @entries: transmit entries (driver state) 8544807e736SMordechay Goodstein * @lock: queue lock 8554807e736SMordechay Goodstein * @stuck_timer: timer that fires if queue gets stuck 8564807e736SMordechay Goodstein * @trans: pointer back to transport (for timer) 8574807e736SMordechay Goodstein * @need_update: indicates need to update read/write index 8584807e736SMordechay Goodstein * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 8594807e736SMordechay Goodstein * @wd_timeout: queue watchdog timeout (jiffies) - per queue 8604807e736SMordechay Goodstein * @frozen: tx stuck queue timer is frozen 8614807e736SMordechay Goodstein * @frozen_expiry_remainder: remember how long until the timer fires 8624807e736SMordechay Goodstein * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 8634807e736SMordechay Goodstein * @write_ptr: 1-st empty entry (index) host_w 8644807e736SMordechay Goodstein * @read_ptr: last used entry (index) host_r 8654807e736SMordechay Goodstein * @dma_addr: physical addr for BD's 8664807e736SMordechay Goodstein * @n_window: safe queue window 8674807e736SMordechay Goodstein * @id: queue id 8684807e736SMordechay Goodstein * @low_mark: low watermark, resume queue if free space more than this 8694807e736SMordechay Goodstein * @high_mark: high watermark, stop queue if free space less than this 8704807e736SMordechay Goodstein * 8714807e736SMordechay Goodstein * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 8724807e736SMordechay Goodstein * descriptors) and required locking structures. 8734807e736SMordechay Goodstein * 8744807e736SMordechay Goodstein * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 8754807e736SMordechay Goodstein * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 8764807e736SMordechay Goodstein * there might be HW changes in the future). For the normal TX 8774807e736SMordechay Goodstein * queues, n_window, which is the size of the software queue data 8784807e736SMordechay Goodstein * is also 256; however, for the command queue, n_window is only 8794807e736SMordechay Goodstein * 32 since we don't need so many commands pending. Since the HW 8804807e736SMordechay Goodstein * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 8814807e736SMordechay Goodstein * This means that we end up with the following: 8824807e736SMordechay Goodstein * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 8834807e736SMordechay Goodstein * SW entries: | 0 | ... | 31 | 8844807e736SMordechay Goodstein * where N is a number between 0 and 7. This means that the SW 8854807e736SMordechay Goodstein * data is a window overlayed over the HW queue. 8864807e736SMordechay Goodstein */ 8874807e736SMordechay Goodstein struct iwl_txq { 8884807e736SMordechay Goodstein void *tfds; 8894807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf *first_tb_bufs; 8904807e736SMordechay Goodstein dma_addr_t first_tb_dma; 8914807e736SMordechay Goodstein struct iwl_pcie_txq_entry *entries; 8924807e736SMordechay Goodstein /* lock for syncing changes on the queue */ 8934807e736SMordechay Goodstein spinlock_t lock; 8944807e736SMordechay Goodstein unsigned long frozen_expiry_remainder; 8954807e736SMordechay Goodstein struct timer_list stuck_timer; 8964807e736SMordechay Goodstein struct iwl_trans *trans; 8974807e736SMordechay Goodstein bool need_update; 8984807e736SMordechay Goodstein bool frozen; 8994807e736SMordechay Goodstein bool ampdu; 9004807e736SMordechay Goodstein int block; 9014807e736SMordechay Goodstein unsigned long wd_timeout; 9024807e736SMordechay Goodstein struct sk_buff_head overflow_q; 9034807e736SMordechay Goodstein struct iwl_dma_ptr bc_tbl; 9044807e736SMordechay Goodstein 9054807e736SMordechay Goodstein int write_ptr; 9064807e736SMordechay Goodstein int read_ptr; 9074807e736SMordechay Goodstein dma_addr_t dma_addr; 9084807e736SMordechay Goodstein int n_window; 9094807e736SMordechay Goodstein u32 id; 9104807e736SMordechay Goodstein int low_mark; 9114807e736SMordechay Goodstein int high_mark; 9124807e736SMordechay Goodstein 9134807e736SMordechay Goodstein bool overflow_tx; 9144807e736SMordechay Goodstein }; 9154f4822b7SMordechay Goodstein 9164f4822b7SMordechay Goodstein /** 9174f4822b7SMordechay Goodstein * struct iwl_trans_txqs - transport tx queues data 9184f4822b7SMordechay Goodstein * 9198e3b79f8SMordechay Goodstein * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 92022852fadSMordechay Goodstein * @page_offs: offset from skb->cb to mac header page pointer 92122852fadSMordechay Goodstein * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 9224f4822b7SMordechay Goodstein * @queue_used - bit mask of used queues 9234f4822b7SMordechay Goodstein * @queue_stopped - bit mask of stopped queues 9240179bfffSMordechay Goodstein * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 9254f4822b7SMordechay Goodstein */ 9264f4822b7SMordechay Goodstein struct iwl_trans_txqs { 9274f4822b7SMordechay Goodstein unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 9284f4822b7SMordechay Goodstein unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 9294f4822b7SMordechay Goodstein struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 930a26014e2SMordechay Goodstein struct dma_pool *bc_pool; 931a26014e2SMordechay Goodstein size_t bc_tbl_size; 9328e3b79f8SMordechay Goodstein bool bc_table_dword; 93322852fadSMordechay Goodstein u8 page_offs; 93422852fadSMordechay Goodstein u8 dev_cmd_offs; 9350cd1ad2dSMordechay Goodstein struct __percpu iwl_tso_hdr_page * tso_hdr_page; 9368e3b79f8SMordechay Goodstein 9374f4822b7SMordechay Goodstein struct { 9384f4822b7SMordechay Goodstein u8 fifo; 9394f4822b7SMordechay Goodstein u8 q_id; 9404f4822b7SMordechay Goodstein unsigned int wdg_timeout; 9414f4822b7SMordechay Goodstein } cmd; 9424f4822b7SMordechay Goodstein 943885375d0SMordechay Goodstein struct { 944885375d0SMordechay Goodstein u8 max_tbs; 945885375d0SMordechay Goodstein u16 size; 946885375d0SMordechay Goodstein u8 addr_size; 947885375d0SMordechay Goodstein } tfd; 9480179bfffSMordechay Goodstein 9490179bfffSMordechay Goodstein struct iwl_dma_ptr scd_bc_tbls; 9504f4822b7SMordechay Goodstein }; 9514f4822b7SMordechay Goodstein 95291c28b83SShahar S Matityahu /** 953e705c121SKalle Valo * struct iwl_trans - transport common data 954e705c121SKalle Valo * 955e705c121SKalle Valo * @ops - pointer to iwl_trans_ops 956e705c121SKalle Valo * @op_mode - pointer to the op_mode 957286ca8ebSLuca Coelho * @trans_cfg: the trans-specific configuration part 958e705c121SKalle Valo * @cfg - pointer to the configuration 9596f482e37SSara Sharon * @drv - pointer to iwl_drv 960e705c121SKalle Valo * @status: a bit-mask of transport status flags 961e705c121SKalle Valo * @dev - pointer to struct device * that represents the device 962e705c121SKalle Valo * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 963e705c121SKalle Valo * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 9641afb0ae4SHaim Dreyfuss * @hw_rf_id a u32 with the device RF ID 965e705c121SKalle Valo * @hw_id: a u32 with the ID of the device / sub-device. 966e705c121SKalle Valo * Set during transport allocation. 967e705c121SKalle Valo * @hw_id_str: a string with info about HW ID. Set during transport allocation. 968e705c121SKalle Valo * @pm_support: set to true in start_hw if link pm is supported 969e705c121SKalle Valo * @ltr_enabled: set to true if the LTR is enabled 970e705c121SKalle Valo * @num_rx_queues: number of RX queues allocated by the transport; 971e705c121SKalle Valo * the transport must set this before calling iwl_drv_start() 972132db31cSGolan Ben-Ami * @iml_len: the length of the image loader 973132db31cSGolan Ben-Ami * @iml: a pointer to the image loader itself 974e705c121SKalle Valo * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 975e705c121SKalle Valo * The user should use iwl_trans_{alloc,free}_tx_cmd. 976e705c121SKalle Valo * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 977e705c121SKalle Valo * starting the firmware, used for tracing 978e705c121SKalle Valo * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 979e705c121SKalle Valo * start of the 802.11 header in the @rx_mpdu_cmd 980e705c121SKalle Valo * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 981b7282643SLuca Coelho * @system_pm_mode: the system-wide power management mode in use. 982b7282643SLuca Coelho * This mode is set dynamically, depending on the WoWLAN values 983b7282643SLuca Coelho * configured from the userspace at runtime. 9844f4822b7SMordechay Goodstein * @iwl_trans_txqs: transport tx queues data. 985e705c121SKalle Valo */ 986e705c121SKalle Valo struct iwl_trans { 987e705c121SKalle Valo const struct iwl_trans_ops *ops; 988e705c121SKalle Valo struct iwl_op_mode *op_mode; 989286ca8ebSLuca Coelho const struct iwl_cfg_trans_params *trans_cfg; 990e705c121SKalle Valo const struct iwl_cfg *cfg; 9916f482e37SSara Sharon struct iwl_drv *drv; 992e705c121SKalle Valo enum iwl_trans_state state; 993e705c121SKalle Valo unsigned long status; 994e705c121SKalle Valo 995e705c121SKalle Valo struct device *dev; 996e705c121SKalle Valo u32 max_skb_frags; 997e705c121SKalle Valo u32 hw_rev; 9981afb0ae4SHaim Dreyfuss u32 hw_rf_id; 999e705c121SKalle Valo u32 hw_id; 1000e705c121SKalle Valo char hw_id_str[52]; 100190824f2fSLuca Coelho u32 sku_id[3]; 1002e705c121SKalle Valo 1003e705c121SKalle Valo u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 1004e705c121SKalle Valo 1005e705c121SKalle Valo bool pm_support; 1006e705c121SKalle Valo bool ltr_enabled; 1007e705c121SKalle Valo 100839bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 100939bdb17eSSharon Dvir int command_groups_size; 101039bdb17eSSharon Dvir 1011e705c121SKalle Valo u8 num_rx_queues; 1012e705c121SKalle Valo 1013132db31cSGolan Ben-Ami size_t iml_len; 1014132db31cSGolan Ben-Ami u8 *iml; 1015132db31cSGolan Ben-Ami 1016e705c121SKalle Valo /* The following fields are internal only */ 1017e705c121SKalle Valo struct kmem_cache *dev_cmd_pool; 1018e705c121SKalle Valo char dev_cmd_pool_name[50]; 1019e705c121SKalle Valo 1020e705c121SKalle Valo struct dentry *dbgfs_dir; 1021e705c121SKalle Valo 1022e705c121SKalle Valo #ifdef CONFIG_LOCKDEP 1023e705c121SKalle Valo struct lockdep_map sync_cmd_lockdep_map; 1024e705c121SKalle Valo #endif 1025e705c121SKalle Valo 102691c28b83SShahar S Matityahu struct iwl_trans_debug dbg; 1027505a00c0SShahar S Matityahu struct iwl_self_init_dram init_dram; 1028e705c121SKalle Valo 1029b7282643SLuca Coelho enum iwl_plat_pm_mode system_pm_mode; 1030700b3799SShahar S Matityahu 10310b295a1eSLuca Coelho const char *name; 10324f4822b7SMordechay Goodstein struct iwl_trans_txqs txqs; 10330b295a1eSLuca Coelho 1034e705c121SKalle Valo /* pointer to trans specific struct */ 1035e705c121SKalle Valo /*Ensure that this pointer will always be aligned to sizeof pointer */ 103645c21a0eSGustavo A. R. Silva char trans_specific[] __aligned(sizeof(void *)); 1037e705c121SKalle Valo }; 1038e705c121SKalle Valo 103939bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 104039bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 104139bdb17eSSharon Dvir 1042e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans, 1043e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1044e705c121SKalle Valo { 1045e705c121SKalle Valo trans->op_mode = trans_cfg->op_mode; 1046e705c121SKalle Valo 1047e705c121SKalle Valo trans->ops->configure(trans, trans_cfg); 104839bdb17eSSharon Dvir WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1049e705c121SKalle Valo } 1050e705c121SKalle Valo 1051bab3cb92SEmmanuel Grumbach static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1052e705c121SKalle Valo { 1053e705c121SKalle Valo might_sleep(); 1054e705c121SKalle Valo 1055bab3cb92SEmmanuel Grumbach return trans->ops->start_hw(trans); 1056e705c121SKalle Valo } 1057e705c121SKalle Valo 1058e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1059e705c121SKalle Valo { 1060e705c121SKalle Valo might_sleep(); 1061e705c121SKalle Valo 1062e705c121SKalle Valo if (trans->ops->op_mode_leave) 1063e705c121SKalle Valo trans->ops->op_mode_leave(trans); 1064e705c121SKalle Valo 1065e705c121SKalle Valo trans->op_mode = NULL; 1066e705c121SKalle Valo 1067e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1068e705c121SKalle Valo } 1069e705c121SKalle Valo 1070e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1071e705c121SKalle Valo { 1072e705c121SKalle Valo might_sleep(); 1073e705c121SKalle Valo 1074e705c121SKalle Valo trans->state = IWL_TRANS_FW_ALIVE; 1075e705c121SKalle Valo 1076e705c121SKalle Valo trans->ops->fw_alive(trans, scd_addr); 1077e705c121SKalle Valo } 1078e705c121SKalle Valo 1079e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1080e705c121SKalle Valo const struct fw_img *fw, 1081e705c121SKalle Valo bool run_in_rfkill) 1082e705c121SKalle Valo { 1083e705c121SKalle Valo might_sleep(); 1084e705c121SKalle Valo 1085e705c121SKalle Valo WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1086e705c121SKalle Valo 1087e705c121SKalle Valo clear_bit(STATUS_FW_ERROR, &trans->status); 1088e705c121SKalle Valo return trans->ops->start_fw(trans, fw, run_in_rfkill); 1089e705c121SKalle Valo } 1090e705c121SKalle Valo 1091bab3cb92SEmmanuel Grumbach static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1092e705c121SKalle Valo { 1093e705c121SKalle Valo might_sleep(); 1094e705c121SKalle Valo 1095bab3cb92SEmmanuel Grumbach trans->ops->stop_device(trans); 1096e705c121SKalle Valo 1097e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1098e705c121SKalle Valo } 1099e705c121SKalle Valo 1100e5f3f215SHaim Dreyfuss static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 110123ae6128SMatti Gottlieb bool reset) 1102e705c121SKalle Valo { 1103e705c121SKalle Valo might_sleep(); 1104e5f3f215SHaim Dreyfuss if (!trans->ops->d3_suspend) 1105e5f3f215SHaim Dreyfuss return 0; 1106e5f3f215SHaim Dreyfuss 1107e5f3f215SHaim Dreyfuss return trans->ops->d3_suspend(trans, test, reset); 1108e705c121SKalle Valo } 1109e705c121SKalle Valo 1110e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1111e705c121SKalle Valo enum iwl_d3_status *status, 111223ae6128SMatti Gottlieb bool test, bool reset) 1113e705c121SKalle Valo { 1114e705c121SKalle Valo might_sleep(); 1115e705c121SKalle Valo if (!trans->ops->d3_resume) 1116e705c121SKalle Valo return 0; 1117e705c121SKalle Valo 111823ae6128SMatti Gottlieb return trans->ops->d3_resume(trans, status, test, reset); 1119e705c121SKalle Valo } 1120e705c121SKalle Valo 1121e705c121SKalle Valo static inline int iwl_trans_suspend(struct iwl_trans *trans) 1122e705c121SKalle Valo { 1123e705c121SKalle Valo if (!trans->ops->suspend) 1124e705c121SKalle Valo return 0; 1125e705c121SKalle Valo 1126e705c121SKalle Valo return trans->ops->suspend(trans); 1127e705c121SKalle Valo } 1128e705c121SKalle Valo 1129e705c121SKalle Valo static inline void iwl_trans_resume(struct iwl_trans *trans) 1130e705c121SKalle Valo { 1131e705c121SKalle Valo if (trans->ops->resume) 1132e705c121SKalle Valo trans->ops->resume(trans); 1133e705c121SKalle Valo } 1134e705c121SKalle Valo 1135e705c121SKalle Valo static inline struct iwl_trans_dump_data * 113679f033f6SSara Sharon iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask) 1137e705c121SKalle Valo { 1138e705c121SKalle Valo if (!trans->ops->dump_data) 1139e705c121SKalle Valo return NULL; 114079f033f6SSara Sharon return trans->ops->dump_data(trans, dump_mask); 1141e705c121SKalle Valo } 1142e705c121SKalle Valo 1143a89c72ffSJohannes Berg static inline struct iwl_device_tx_cmd * 1144e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1145e705c121SKalle Valo { 1146a89c72ffSJohannes Berg return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1147e705c121SKalle Valo } 1148e705c121SKalle Valo 114992fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 115092fe8343SEmmanuel Grumbach 1151e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1152a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd) 1153e705c121SKalle Valo { 11541ea423b0SLuca Coelho kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1155e705c121SKalle Valo } 1156e705c121SKalle Valo 1157e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1158a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue) 1159e705c121SKalle Valo { 1160e705c121SKalle Valo if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1161e705c121SKalle Valo return -EIO; 1162e705c121SKalle Valo 1163e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1164e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1165e5d15cb5SEliad Peller return -EIO; 1166e5d15cb5SEliad Peller } 1167e705c121SKalle Valo 1168e705c121SKalle Valo return trans->ops->tx(trans, skb, dev_cmd, queue); 1169e705c121SKalle Valo } 1170e705c121SKalle Valo 1171e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1172e705c121SKalle Valo int ssn, struct sk_buff_head *skbs) 1173e705c121SKalle Valo { 1174e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1175e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1176e5d15cb5SEliad Peller return; 1177e5d15cb5SEliad Peller } 1178e705c121SKalle Valo 1179e705c121SKalle Valo trans->ops->reclaim(trans, queue, ssn, skbs); 1180e705c121SKalle Valo } 1181e705c121SKalle Valo 1182ba7136f3SAlex Malamud static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1183ba7136f3SAlex Malamud int ptr) 1184ba7136f3SAlex Malamud { 1185ba7136f3SAlex Malamud if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1186ba7136f3SAlex Malamud IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1187ba7136f3SAlex Malamud return; 1188ba7136f3SAlex Malamud } 1189ba7136f3SAlex Malamud 1190ba7136f3SAlex Malamud trans->ops->set_q_ptrs(trans, queue, ptr); 1191ba7136f3SAlex Malamud } 1192ba7136f3SAlex Malamud 1193e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1194e705c121SKalle Valo bool configure_scd) 1195e705c121SKalle Valo { 1196e705c121SKalle Valo trans->ops->txq_disable(trans, queue, configure_scd); 1197e705c121SKalle Valo } 1198e705c121SKalle Valo 1199dcfbd67bSEmmanuel Grumbach static inline bool 1200e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1201e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1202e705c121SKalle Valo unsigned int queue_wdg_timeout) 1203e705c121SKalle Valo { 1204e705c121SKalle Valo might_sleep(); 1205e705c121SKalle Valo 1206e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1207e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1208dcfbd67bSEmmanuel Grumbach return false; 1209e5d15cb5SEliad Peller } 1210e705c121SKalle Valo 1211dcfbd67bSEmmanuel Grumbach return trans->ops->txq_enable(trans, queue, ssn, 1212dcfbd67bSEmmanuel Grumbach cfg, queue_wdg_timeout); 1213e705c121SKalle Valo } 1214e705c121SKalle Valo 121592536c96SSara Sharon static inline int 121692536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 121792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 121892536c96SSara Sharon { 121992536c96SSara Sharon if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 122092536c96SSara Sharon return -ENOTSUPP; 122192536c96SSara Sharon 122292536c96SSara Sharon return trans->ops->rxq_dma_data(trans, queue, data); 122392536c96SSara Sharon } 122492536c96SSara Sharon 12256b35ff91SSara Sharon static inline void 12266b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue) 12276b35ff91SSara Sharon { 12286b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_free)) 12296b35ff91SSara Sharon return; 12306b35ff91SSara Sharon 12316b35ff91SSara Sharon trans->ops->txq_free(trans, queue); 12326b35ff91SSara Sharon } 12336b35ff91SSara Sharon 12346b35ff91SSara Sharon static inline int 12356b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans, 12361169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 12375369774cSSara Sharon int cmd_id, int size, 12385369774cSSara Sharon unsigned int wdg_timeout) 12396b35ff91SSara Sharon { 12406b35ff91SSara Sharon might_sleep(); 12416b35ff91SSara Sharon 12426b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 12436b35ff91SSara Sharon return -ENOTSUPP; 12446b35ff91SSara Sharon 12456b35ff91SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 12466b35ff91SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 12476b35ff91SSara Sharon return -EIO; 12486b35ff91SSara Sharon } 12496b35ff91SSara Sharon 12501169310fSGolan Ben Ami return trans->ops->txq_alloc(trans, flags, sta_id, tid, 12511169310fSGolan Ben Ami cmd_id, size, wdg_timeout); 12526b35ff91SSara Sharon } 12536b35ff91SSara Sharon 125442db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 125542db09c1SLiad Kaufman int queue, bool shared_mode) 125642db09c1SLiad Kaufman { 125742db09c1SLiad Kaufman if (trans->ops->txq_set_shared_mode) 125842db09c1SLiad Kaufman trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 125942db09c1SLiad Kaufman } 126042db09c1SLiad Kaufman 1261e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1262e705c121SKalle Valo int fifo, int sta_id, int tid, 1263e705c121SKalle Valo int frame_limit, u16 ssn, 1264e705c121SKalle Valo unsigned int queue_wdg_timeout) 1265e705c121SKalle Valo { 1266e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1267e705c121SKalle Valo .fifo = fifo, 1268e705c121SKalle Valo .sta_id = sta_id, 1269e705c121SKalle Valo .tid = tid, 1270e705c121SKalle Valo .frame_limit = frame_limit, 1271e705c121SKalle Valo .aggregate = sta_id >= 0, 1272e705c121SKalle Valo }; 1273e705c121SKalle Valo 1274e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1275e705c121SKalle Valo } 1276e705c121SKalle Valo 1277e705c121SKalle Valo static inline 1278e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1279e705c121SKalle Valo unsigned int queue_wdg_timeout) 1280e705c121SKalle Valo { 1281e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1282e705c121SKalle Valo .fifo = fifo, 1283e705c121SKalle Valo .sta_id = -1, 1284e705c121SKalle Valo .tid = IWL_MAX_TID_COUNT, 1285e705c121SKalle Valo .frame_limit = IWL_FRAME_LIMIT, 1286e705c121SKalle Valo .aggregate = false, 1287e705c121SKalle Valo }; 1288e705c121SKalle Valo 1289e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1290e705c121SKalle Valo } 1291e705c121SKalle Valo 1292e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1293e705c121SKalle Valo unsigned long txqs, 1294e705c121SKalle Valo bool freeze) 1295e705c121SKalle Valo { 1296e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1297e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1298e5d15cb5SEliad Peller return; 1299e5d15cb5SEliad Peller } 1300e705c121SKalle Valo 1301e705c121SKalle Valo if (trans->ops->freeze_txq_timer) 1302e705c121SKalle Valo trans->ops->freeze_txq_timer(trans, txqs, freeze); 1303e705c121SKalle Valo } 1304e705c121SKalle Valo 13050cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 13060cd58eaaSEmmanuel Grumbach bool block) 13070cd58eaaSEmmanuel Grumbach { 1308e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 13090cd58eaaSEmmanuel Grumbach IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1310e5d15cb5SEliad Peller return; 1311e5d15cb5SEliad Peller } 13120cd58eaaSEmmanuel Grumbach 13130cd58eaaSEmmanuel Grumbach if (trans->ops->block_txq_ptrs) 13140cd58eaaSEmmanuel Grumbach trans->ops->block_txq_ptrs(trans, block); 13150cd58eaaSEmmanuel Grumbach } 13160cd58eaaSEmmanuel Grumbach 1317a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1318e705c121SKalle Valo u32 txqs) 1319e705c121SKalle Valo { 1320d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1321d6d517b7SSara Sharon return -ENOTSUPP; 1322d6d517b7SSara Sharon 1323e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1324e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1325e5d15cb5SEliad Peller return -EIO; 1326e5d15cb5SEliad Peller } 1327e705c121SKalle Valo 1328a1a57877SSara Sharon return trans->ops->wait_tx_queues_empty(trans, txqs); 1329e705c121SKalle Valo } 1330e705c121SKalle Valo 1331d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1332d6d517b7SSara Sharon { 1333d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1334d6d517b7SSara Sharon return -ENOTSUPP; 1335d6d517b7SSara Sharon 1336d6d517b7SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1337d6d517b7SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1338d6d517b7SSara Sharon return -EIO; 1339d6d517b7SSara Sharon } 1340d6d517b7SSara Sharon 1341d6d517b7SSara Sharon return trans->ops->wait_txq_empty(trans, queue); 1342d6d517b7SSara Sharon } 1343d6d517b7SSara Sharon 1344e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1345e705c121SKalle Valo { 1346e705c121SKalle Valo trans->ops->write8(trans, ofs, val); 1347e705c121SKalle Valo } 1348e705c121SKalle Valo 1349e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1350e705c121SKalle Valo { 1351e705c121SKalle Valo trans->ops->write32(trans, ofs, val); 1352e705c121SKalle Valo } 1353e705c121SKalle Valo 1354e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1355e705c121SKalle Valo { 1356e705c121SKalle Valo return trans->ops->read32(trans, ofs); 1357e705c121SKalle Valo } 1358e705c121SKalle Valo 1359e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1360e705c121SKalle Valo { 1361e705c121SKalle Valo return trans->ops->read_prph(trans, ofs); 1362e705c121SKalle Valo } 1363e705c121SKalle Valo 1364e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1365e705c121SKalle Valo u32 val) 1366e705c121SKalle Valo { 1367e705c121SKalle Valo return trans->ops->write_prph(trans, ofs, val); 1368e705c121SKalle Valo } 1369e705c121SKalle Valo 1370e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1371e705c121SKalle Valo void *buf, int dwords) 1372e705c121SKalle Valo { 1373e705c121SKalle Valo return trans->ops->read_mem(trans, addr, buf, dwords); 1374e705c121SKalle Valo } 1375e705c121SKalle Valo 1376e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1377e705c121SKalle Valo do { \ 1378e705c121SKalle Valo if (__builtin_constant_p(bufsize)) \ 1379e705c121SKalle Valo BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1380e705c121SKalle Valo iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1381e705c121SKalle Valo } while (0) 1382e705c121SKalle Valo 1383e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1384e705c121SKalle Valo { 1385e705c121SKalle Valo u32 value; 1386e705c121SKalle Valo 1387e705c121SKalle Valo if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1388e705c121SKalle Valo return 0xa5a5a5a5; 1389e705c121SKalle Valo 1390e705c121SKalle Valo return value; 1391e705c121SKalle Valo } 1392e705c121SKalle Valo 1393e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1394e705c121SKalle Valo const void *buf, int dwords) 1395e705c121SKalle Valo { 1396e705c121SKalle Valo return trans->ops->write_mem(trans, addr, buf, dwords); 1397e705c121SKalle Valo } 1398e705c121SKalle Valo 1399e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1400e705c121SKalle Valo u32 val) 1401e705c121SKalle Valo { 1402e705c121SKalle Valo return iwl_trans_write_mem(trans, addr, &val, 1); 1403e705c121SKalle Valo } 1404e705c121SKalle Valo 1405e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1406e705c121SKalle Valo { 1407e705c121SKalle Valo if (trans->ops->set_pmi) 1408e705c121SKalle Valo trans->ops->set_pmi(trans, state); 1409e705c121SKalle Valo } 1410e705c121SKalle Valo 1411870c2a11SGolan Ben Ami static inline void iwl_trans_sw_reset(struct iwl_trans *trans) 1412870c2a11SGolan Ben Ami { 1413870c2a11SGolan Ben Ami if (trans->ops->sw_reset) 1414870c2a11SGolan Ben Ami trans->ops->sw_reset(trans); 1415870c2a11SGolan Ben Ami } 1416870c2a11SGolan Ben Ami 1417e705c121SKalle Valo static inline void 1418e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1419e705c121SKalle Valo { 1420e705c121SKalle Valo trans->ops->set_bits_mask(trans, reg, mask, value); 1421e705c121SKalle Valo } 1422e705c121SKalle Valo 142323ba9340SEmmanuel Grumbach #define iwl_trans_grab_nic_access(trans, flags) \ 1424e705c121SKalle Valo __cond_lock(nic_access, \ 142523ba9340SEmmanuel Grumbach likely((trans)->ops->grab_nic_access(trans, flags))) 1426e705c121SKalle Valo 1427e705c121SKalle Valo static inline void __releases(nic_access) 1428e705c121SKalle Valo iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) 1429e705c121SKalle Valo { 1430e705c121SKalle Valo trans->ops->release_nic_access(trans, flags); 1431e705c121SKalle Valo __release(nic_access); 1432e705c121SKalle Valo } 1433e705c121SKalle Valo 1434e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans) 1435e705c121SKalle Valo { 1436e705c121SKalle Valo if (WARN_ON_ONCE(!trans->op_mode)) 1437e705c121SKalle Valo return; 1438e705c121SKalle Valo 1439e705c121SKalle Valo /* prevent double restarts due to the same erroneous FW */ 1440e705c121SKalle Valo if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) 1441e705c121SKalle Valo iwl_op_mode_nic_error(trans->op_mode); 1442e705c121SKalle Valo } 1443e705c121SKalle Valo 1444068893b7SShahar S Matityahu static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1445068893b7SShahar S Matityahu { 1446068893b7SShahar S Matityahu return trans->state == IWL_TRANS_FW_ALIVE; 1447068893b7SShahar S Matityahu } 1448068893b7SShahar S Matityahu 1449d1967ce6SShahar S Matityahu static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1450d1967ce6SShahar S Matityahu { 1451d1967ce6SShahar S Matityahu if (trans->ops->sync_nmi) 1452d1967ce6SShahar S Matityahu trans->ops->sync_nmi(trans); 1453d1967ce6SShahar S Matityahu } 1454d1967ce6SShahar S Matityahu 1455a182dfabSLuca Coelho static inline int iwl_trans_set_pnvm(struct iwl_trans *trans, 1456a182dfabSLuca Coelho const void *data, u32 len) 1457a182dfabSLuca Coelho { 1458a182dfabSLuca Coelho if (trans->ops->set_pnvm) 1459a182dfabSLuca Coelho return trans->ops->set_pnvm(trans, data, len); 1460a182dfabSLuca Coelho 1461a182dfabSLuca Coelho return 0; 1462a182dfabSLuca Coelho } 1463a182dfabSLuca Coelho 1464a1af4c48SShahar S Matityahu static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1465a1af4c48SShahar S Matityahu { 1466341bd290SShahar S Matityahu return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1467341bd290SShahar S Matityahu trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1468a1af4c48SShahar S Matityahu } 1469a1af4c48SShahar S Matityahu 1470e705c121SKalle Valo /***************************************************** 1471e705c121SKalle Valo * transport helper functions 1472e705c121SKalle Valo *****************************************************/ 1473e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1474e705c121SKalle Valo struct device *dev, 1475a89c72ffSJohannes Berg const struct iwl_trans_ops *ops, 1476fda1bd0dSMordechay Goodstein const struct iwl_cfg_trans_params *cfg_trans); 1477e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans); 1478e705c121SKalle Valo 1479e705c121SKalle Valo /***************************************************** 1480e705c121SKalle Valo * driver (transport) register/unregister functions 1481e705c121SKalle Valo ******************************************************/ 1482e705c121SKalle Valo int __must_check iwl_pci_register_driver(void); 1483e705c121SKalle Valo void iwl_pci_unregister_driver(void); 1484e705c121SKalle Valo 1485e705c121SKalle Valo #endif /* __iwl_trans_h__ */ 1486