18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 28e99ea8dSJohannes Berg /* 32b84e632SEmmanuel Grumbach * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #ifndef __iwl_trans_h__ 8e705c121SKalle Valo #define __iwl_trans_h__ 9e705c121SKalle Valo 10e705c121SKalle Valo #include <linux/ieee80211.h> 11e705c121SKalle Valo #include <linux/mm.h> /* for page_address */ 12e705c121SKalle Valo #include <linux/lockdep.h> 1339bdb17eSSharon Dvir #include <linux/kernel.h> 14e705c121SKalle Valo 15e705c121SKalle Valo #include "iwl-debug.h" 16e705c121SKalle Valo #include "iwl-config.h" 17d962f9b1SJohannes Berg #include "fw/img.h" 18e705c121SKalle Valo #include "iwl-op-mode.h" 1969725928SLuca Coelho #include <linux/firmware.h> 20d172a5efSJohannes Berg #include "fw/api/cmdhdr.h" 21d172a5efSJohannes Berg #include "fw/api/txq.h" 22f14cda6fSSara Sharon #include "fw/api/dbg-tlv.h" 23f14cda6fSSara Sharon #include "iwl-dbg-tlv.h" 24e705c121SKalle Valo 25e705c121SKalle Valo /** 26e705c121SKalle Valo * DOC: Transport layer - what is it ? 27e705c121SKalle Valo * 28e705c121SKalle Valo * The transport layer is the layer that deals with the HW directly. It provides 29e705c121SKalle Valo * an abstraction of the underlying HW to the upper layer. The transport layer 30e705c121SKalle Valo * doesn't provide any policy, algorithm or anything of this kind, but only 31e705c121SKalle Valo * mechanisms to make the HW do something. It is not completely stateless but 32e705c121SKalle Valo * close to it. 33e705c121SKalle Valo * We will have an implementation for each different supported bus. 34e705c121SKalle Valo */ 35e705c121SKalle Valo 36e705c121SKalle Valo /** 37e705c121SKalle Valo * DOC: Life cycle of the transport layer 38e705c121SKalle Valo * 39e705c121SKalle Valo * The transport layer has a very precise life cycle. 40e705c121SKalle Valo * 41e705c121SKalle Valo * 1) A helper function is called during the module initialization and 42e705c121SKalle Valo * registers the bus driver's ops with the transport's alloc function. 43e705c121SKalle Valo * 2) Bus's probe calls to the transport layer's allocation functions. 44e705c121SKalle Valo * Of course this function is bus specific. 45e705c121SKalle Valo * 3) This allocation functions will spawn the upper layer which will 46e705c121SKalle Valo * register mac80211. 47e705c121SKalle Valo * 48e705c121SKalle Valo * 4) At some point (i.e. mac80211's start call), the op_mode will call 49e705c121SKalle Valo * the following sequence: 50e705c121SKalle Valo * start_hw 51e705c121SKalle Valo * start_fw 52e705c121SKalle Valo * 53e705c121SKalle Valo * 5) Then when finished (or reset): 54e705c121SKalle Valo * stop_device 55e705c121SKalle Valo * 56e705c121SKalle Valo * 6) Eventually, the free function will be called. 57e705c121SKalle Valo */ 58e705c121SKalle Valo 59e701da0cSLuca Coelho #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 60e701da0cSLuca Coelho 61e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 62e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID 0x55550000 63e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN 0x40 64fbe41127SSara Sharon #define FH_RSCSR_RPA_EN BIT(25) 659d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN BIT(26) 66ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS 16 67ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK 0x3F0000 68e705c121SKalle Valo 69e705c121SKalle Valo struct iwl_rx_packet { 70e705c121SKalle Valo /* 71e705c121SKalle Valo * The first 4 bytes of the RX frame header contain both the RX frame 72e705c121SKalle Valo * size and some flags. 73e705c121SKalle Valo * Bit fields: 74e705c121SKalle Valo * 31: flag flush RB request 75e705c121SKalle Valo * 30: flag ignore TC (terminal counter) request 76e705c121SKalle Valo * 29: flag fast IRQ request 779d0fc5a5SDavid Spinadel * 28-27: Reserved 789d0fc5a5SDavid Spinadel * 26: RADA enabled 79fbe41127SSara Sharon * 25: Offload enabled 80ab2e696bSSara Sharon * 24: RPF enabled 81ab2e696bSSara Sharon * 23: RSS enabled 82ab2e696bSSara Sharon * 22: Checksum enabled 83ab2e696bSSara Sharon * 21-16: RX queue 84ab2e696bSSara Sharon * 15-14: Reserved 85e705c121SKalle Valo * 13-00: RX frame size 86e705c121SKalle Valo */ 87e705c121SKalle Valo __le32 len_n_flags; 88e705c121SKalle Valo struct iwl_cmd_header hdr; 89e705c121SKalle Valo u8 data[]; 90e705c121SKalle Valo } __packed; 91e705c121SKalle Valo 92e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 93e705c121SKalle Valo { 94e705c121SKalle Valo return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 95e705c121SKalle Valo } 96e705c121SKalle Valo 97e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 98e705c121SKalle Valo { 99e705c121SKalle Valo return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 100e705c121SKalle Valo } 101e705c121SKalle Valo 102e705c121SKalle Valo /** 103e705c121SKalle Valo * enum CMD_MODE - how to send the host commands ? 104e705c121SKalle Valo * 105e705c121SKalle Valo * @CMD_ASYNC: Return right away and don't wait for the response 106e705c121SKalle Valo * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 107e705c121SKalle Valo * the response. The caller needs to call iwl_free_resp when done. 108dcbb4746SEmmanuel Grumbach * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 109dcbb4746SEmmanuel Grumbach * called after this command completes. Valid only with CMD_ASYNC. 110708a39aaSHaim Dreyfuss * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to 111708a39aaSHaim Dreyfuss * SUSPEND and RESUME commands. We are in D3 mode when we set 112708a39aaSHaim Dreyfuss * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3. 113e705c121SKalle Valo */ 114e705c121SKalle Valo enum CMD_MODE { 115e705c121SKalle Valo CMD_ASYNC = BIT(0), 116e705c121SKalle Valo CMD_WANT_SKB = BIT(1), 117e705c121SKalle Valo CMD_SEND_IN_RFKILL = BIT(2), 118043fa901SEmmanuel Grumbach CMD_WANT_ASYNC_CALLBACK = BIT(3), 119708a39aaSHaim Dreyfuss CMD_SEND_IN_D3 = BIT(4), 120e705c121SKalle Valo }; 121e705c121SKalle Valo 122e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320 123e705c121SKalle Valo 124e705c121SKalle Valo /** 125e705c121SKalle Valo * struct iwl_device_cmd 126e705c121SKalle Valo * 127e705c121SKalle Valo * For allocation of the command and tx queues, this establishes the overall 128e705c121SKalle Valo * size of the largest command we send to uCode, except for commands that 129e705c121SKalle Valo * aren't fully copied and use other TFD space. 130e705c121SKalle Valo */ 131e705c121SKalle Valo struct iwl_device_cmd { 132e705c121SKalle Valo union { 133e705c121SKalle Valo struct { 134e705c121SKalle Valo struct iwl_cmd_header hdr; /* uCode API */ 135e705c121SKalle Valo u8 payload[DEF_CMD_PAYLOAD_SIZE]; 136e705c121SKalle Valo }; 137e705c121SKalle Valo struct { 138e705c121SKalle Valo struct iwl_cmd_header_wide hdr_wide; 139e705c121SKalle Valo u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 140e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide) + 141e705c121SKalle Valo sizeof(struct iwl_cmd_header)]; 142e705c121SKalle Valo }; 143e705c121SKalle Valo }; 144e705c121SKalle Valo } __packed; 145e705c121SKalle Valo 146a89c72ffSJohannes Berg /** 147a89c72ffSJohannes Berg * struct iwl_device_tx_cmd - buffer for TX command 148a89c72ffSJohannes Berg * @hdr: the header 149a89c72ffSJohannes Berg * @payload: the payload placeholder 150a89c72ffSJohannes Berg * 151a89c72ffSJohannes Berg * The actual structure is sized dynamically according to need. 152a89c72ffSJohannes Berg */ 153a89c72ffSJohannes Berg struct iwl_device_tx_cmd { 154a89c72ffSJohannes Berg struct iwl_cmd_header hdr; 155a89c72ffSJohannes Berg u8 payload[]; 156a89c72ffSJohannes Berg } __packed; 157a89c72ffSJohannes Berg 158e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 159e705c121SKalle Valo 160e705c121SKalle Valo /* 161e705c121SKalle Valo * number of transfer buffers (fragments) per transmit frame descriptor; 162e705c121SKalle Valo * this is just the driver's idea, the hardware supports 20 163e705c121SKalle Valo */ 164e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD 2 165e705c121SKalle Valo 166885375d0SMordechay Goodstein /* We need 2 entries for the TX command and header, and another one might 167885375d0SMordechay Goodstein * be needed for potential data in the SKB's head. The remaining ones can 168885375d0SMordechay Goodstein * be used for frags. 169885375d0SMordechay Goodstein */ 170885375d0SMordechay Goodstein #define IWL_TRANS_MAX_FRAGS(trans) ((trans)->txqs.tfd.max_tbs - 3) 171885375d0SMordechay Goodstein 172e705c121SKalle Valo /** 173b8aed81cSJohannes Berg * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 174e705c121SKalle Valo * 175e705c121SKalle Valo * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 176e705c121SKalle Valo * ring. The transport layer doesn't map the command's buffer to DMA, but 177e705c121SKalle Valo * rather copies it to a previously allocated DMA buffer. This flag tells 178e705c121SKalle Valo * the transport layer not to copy the command, but to map the existing 179e705c121SKalle Valo * buffer (that is passed in) instead. This saves the memcpy and allows 180e705c121SKalle Valo * commands that are bigger than the fixed buffer to be submitted. 181e705c121SKalle Valo * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 182e705c121SKalle Valo * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 183e705c121SKalle Valo * chunk internally and free it again after the command completes. This 184e705c121SKalle Valo * can (currently) be used only once per command. 185e705c121SKalle Valo * Note that a TFD entry after a DUP one cannot be a normal copied one. 186e705c121SKalle Valo */ 187e705c121SKalle Valo enum iwl_hcmd_dataflag { 188e705c121SKalle Valo IWL_HCMD_DFL_NOCOPY = BIT(0), 189e705c121SKalle Valo IWL_HCMD_DFL_DUP = BIT(1), 190e705c121SKalle Valo }; 191e705c121SKalle Valo 19222463857SShahar S Matityahu enum iwl_error_event_table_status { 19322463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 19422463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 19522463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 19622463857SShahar S Matityahu }; 19722463857SShahar S Matityahu 198e705c121SKalle Valo /** 199e705c121SKalle Valo * struct iwl_host_cmd - Host command to the uCode 200e705c121SKalle Valo * 201e705c121SKalle Valo * @data: array of chunks that composes the data of the host command 202e705c121SKalle Valo * @resp_pkt: response packet, if %CMD_WANT_SKB was set 203e705c121SKalle Valo * @_rx_page_order: (internally used to free response packet) 204e705c121SKalle Valo * @_rx_page_addr: (internally used to free response packet) 205e705c121SKalle Valo * @flags: can be CMD_* 206e705c121SKalle Valo * @len: array of the lengths of the chunks in data 207e705c121SKalle Valo * @dataflags: IWL_HCMD_DFL_* 208e705c121SKalle Valo * @id: command id of the host command, for wide commands encoding the 209e705c121SKalle Valo * version and group as well 210e705c121SKalle Valo */ 211e705c121SKalle Valo struct iwl_host_cmd { 212e705c121SKalle Valo const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 213e705c121SKalle Valo struct iwl_rx_packet *resp_pkt; 214e705c121SKalle Valo unsigned long _rx_page_addr; 215e705c121SKalle Valo u32 _rx_page_order; 216e705c121SKalle Valo 217e705c121SKalle Valo u32 flags; 218e705c121SKalle Valo u32 id; 219e705c121SKalle Valo u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 220e705c121SKalle Valo u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 221e705c121SKalle Valo }; 222e705c121SKalle Valo 223e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 224e705c121SKalle Valo { 225e705c121SKalle Valo free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 226e705c121SKalle Valo } 227e705c121SKalle Valo 228e705c121SKalle Valo struct iwl_rx_cmd_buffer { 229e705c121SKalle Valo struct page *_page; 230e705c121SKalle Valo int _offset; 231e705c121SKalle Valo bool _page_stolen; 232e705c121SKalle Valo u32 _rx_page_order; 233e705c121SKalle Valo unsigned int truesize; 234e705c121SKalle Valo }; 235e705c121SKalle Valo 236e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 237e705c121SKalle Valo { 238e705c121SKalle Valo return (void *)((unsigned long)page_address(r->_page) + r->_offset); 239e705c121SKalle Valo } 240e705c121SKalle Valo 241e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 242e705c121SKalle Valo { 243e705c121SKalle Valo return r->_offset; 244e705c121SKalle Valo } 245e705c121SKalle Valo 246e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 247e705c121SKalle Valo { 248e705c121SKalle Valo r->_page_stolen = true; 249e705c121SKalle Valo get_page(r->_page); 250e705c121SKalle Valo return r->_page; 251e705c121SKalle Valo } 252e705c121SKalle Valo 253e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 254e705c121SKalle Valo { 255e705c121SKalle Valo __free_pages(r->_page, r->_rx_page_order); 256e705c121SKalle Valo } 257e705c121SKalle Valo 258e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS 6 259e705c121SKalle Valo 260e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 261e705c121SKalle Valo 262e705c121SKalle Valo /* 263e705c121SKalle Valo * Maximum number of HW queues the transport layer 264e705c121SKalle Valo * currently supports 265e705c121SKalle Valo */ 266e705c121SKalle Valo #define IWL_MAX_HW_QUEUES 32 267e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES 512 268e982bc2cSSara Sharon 269e705c121SKalle Valo #define IWL_MAX_TID_COUNT 8 270c65f4e03SSara Sharon #define IWL_MGMT_TID 15 271e705c121SKalle Valo #define IWL_FRAME_LIMIT 64 272e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES 16 2730cd38f4dSMordechay Goodstein #define IWL_9000_MAX_RX_HW_QUEUES 6 274e705c121SKalle Valo 275e705c121SKalle Valo /** 276e705c121SKalle Valo * enum iwl_wowlan_status - WoWLAN image/device status 277e705c121SKalle Valo * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 278e705c121SKalle Valo * @IWL_D3_STATUS_RESET: device was reset while suspended 279e705c121SKalle Valo */ 280e705c121SKalle Valo enum iwl_d3_status { 281e705c121SKalle Valo IWL_D3_STATUS_ALIVE, 282e705c121SKalle Valo IWL_D3_STATUS_RESET, 283e705c121SKalle Valo }; 284e705c121SKalle Valo 285e705c121SKalle Valo /** 286e705c121SKalle Valo * enum iwl_trans_status: transport status flags 287e705c121SKalle Valo * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 288e705c121SKalle Valo * @STATUS_DEVICE_ENABLED: APM is enabled 289e705c121SKalle Valo * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 290e705c121SKalle Valo * @STATUS_INT_ENABLED: interrupts are enabled 291326477e4SJohannes Berg * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 292326477e4SJohannes Berg * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 293e705c121SKalle Valo * @STATUS_FW_ERROR: the fw is in error state 294e705c121SKalle Valo * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 295e705c121SKalle Valo * are sent 296e705c121SKalle Valo * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 297e705c121SKalle Valo * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 298e705c121SKalle Valo */ 299e705c121SKalle Valo enum iwl_trans_status { 300e705c121SKalle Valo STATUS_SYNC_HCMD_ACTIVE, 301e705c121SKalle Valo STATUS_DEVICE_ENABLED, 302e705c121SKalle Valo STATUS_TPOWER_PMI, 303e705c121SKalle Valo STATUS_INT_ENABLED, 304326477e4SJohannes Berg STATUS_RFKILL_HW, 305326477e4SJohannes Berg STATUS_RFKILL_OPMODE, 306e705c121SKalle Valo STATUS_FW_ERROR, 307e705c121SKalle Valo STATUS_TRANS_GOING_IDLE, 308e705c121SKalle Valo STATUS_TRANS_IDLE, 309e705c121SKalle Valo STATUS_TRANS_DEAD, 310e705c121SKalle Valo }; 311e705c121SKalle Valo 3126c4fbcbcSEmmanuel Grumbach static inline int 3136c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 3146c4fbcbcSEmmanuel Grumbach { 3156c4fbcbcSEmmanuel Grumbach switch (rb_size) { 3161a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 3171a4968d1SGolan Ben Ami return get_order(2 * 1024); 3186c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 3196c4fbcbcSEmmanuel Grumbach return get_order(4 * 1024); 3206c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 3216c4fbcbcSEmmanuel Grumbach return get_order(8 * 1024); 3226c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 3233fa965c2SJohannes Berg return get_order(16 * 1024); 3246c4fbcbcSEmmanuel Grumbach default: 3256c4fbcbcSEmmanuel Grumbach WARN_ON(1); 3266c4fbcbcSEmmanuel Grumbach return -1; 3276c4fbcbcSEmmanuel Grumbach } 3286c4fbcbcSEmmanuel Grumbach } 3296c4fbcbcSEmmanuel Grumbach 33080084e35SJohannes Berg static inline int 33180084e35SJohannes Berg iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 33280084e35SJohannes Berg { 33380084e35SJohannes Berg switch (rb_size) { 33480084e35SJohannes Berg case IWL_AMSDU_2K: 33580084e35SJohannes Berg return 2 * 1024; 33680084e35SJohannes Berg case IWL_AMSDU_4K: 33780084e35SJohannes Berg return 4 * 1024; 33880084e35SJohannes Berg case IWL_AMSDU_8K: 33980084e35SJohannes Berg return 8 * 1024; 34080084e35SJohannes Berg case IWL_AMSDU_12K: 3413fa965c2SJohannes Berg return 16 * 1024; 34280084e35SJohannes Berg default: 34380084e35SJohannes Berg WARN_ON(1); 34480084e35SJohannes Berg return 0; 34580084e35SJohannes Berg } 34680084e35SJohannes Berg } 34780084e35SJohannes Berg 34839bdb17eSSharon Dvir struct iwl_hcmd_names { 34939bdb17eSSharon Dvir u8 cmd_id; 35039bdb17eSSharon Dvir const char *const cmd_name; 35139bdb17eSSharon Dvir }; 35239bdb17eSSharon Dvir 35339bdb17eSSharon Dvir #define HCMD_NAME(x) \ 35439bdb17eSSharon Dvir { .cmd_id = x, .cmd_name = #x } 35539bdb17eSSharon Dvir 35639bdb17eSSharon Dvir struct iwl_hcmd_arr { 35739bdb17eSSharon Dvir const struct iwl_hcmd_names *arr; 35839bdb17eSSharon Dvir int size; 35939bdb17eSSharon Dvir }; 36039bdb17eSSharon Dvir 36139bdb17eSSharon Dvir #define HCMD_ARR(x) \ 36239bdb17eSSharon Dvir { .arr = x, .size = ARRAY_SIZE(x) } 36339bdb17eSSharon Dvir 364e705c121SKalle Valo /** 365e705c121SKalle Valo * struct iwl_trans_config - transport configuration 366e705c121SKalle Valo * 367e705c121SKalle Valo * @op_mode: pointer to the upper layer. 368e705c121SKalle Valo * @cmd_queue: the index of the command queue. 369e705c121SKalle Valo * Must be set before start_fw. 370e705c121SKalle Valo * @cmd_fifo: the fifo for host commands 371e705c121SKalle Valo * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 372e705c121SKalle Valo * @no_reclaim_cmds: Some devices erroneously don't set the 373e705c121SKalle Valo * SEQ_RX_FRAME bit on some notifications, this is the 374e705c121SKalle Valo * list of such notifications to filter. Max length is 375e705c121SKalle Valo * %MAX_NO_RECLAIM_CMDS. 376e705c121SKalle Valo * @n_no_reclaim_cmds: # of commands in list 3776c4fbcbcSEmmanuel Grumbach * @rx_buf_size: RX buffer size needed for A-MSDUs 378e705c121SKalle Valo * if unset 4k will be the RX buffer size 379e705c121SKalle Valo * @bc_table_dword: set to true if the BC table expects the byte count to be 380e705c121SKalle Valo * in DWORD (as opposed to bytes) 381e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 38239bdb17eSSharon Dvir * @command_groups: array of command groups, each member is an array of the 38339bdb17eSSharon Dvir * commands in the group; for debugging only 38439bdb17eSSharon Dvir * @command_groups_size: number of command groups, to avoid illegal access 38521cb3222SJohannes Berg * @cb_data_offs: offset inside skb->cb to store transport data at, must have 38621cb3222SJohannes Berg * space for at least two pointers 387906d4eb8SJohannes Berg * @fw_reset_handshake: firmware supports reset flow handshake 388e705c121SKalle Valo */ 389e705c121SKalle Valo struct iwl_trans_config { 390e705c121SKalle Valo struct iwl_op_mode *op_mode; 391e705c121SKalle Valo 392e705c121SKalle Valo u8 cmd_queue; 393e705c121SKalle Valo u8 cmd_fifo; 394e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 395e705c121SKalle Valo const u8 *no_reclaim_cmds; 396e705c121SKalle Valo unsigned int n_no_reclaim_cmds; 397e705c121SKalle Valo 3986c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 399e705c121SKalle Valo bool bc_table_dword; 400e705c121SKalle Valo bool scd_set_active; 40139bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 40239bdb17eSSharon Dvir int command_groups_size; 403e705c121SKalle Valo 40421cb3222SJohannes Berg u8 cb_data_offs; 405906d4eb8SJohannes Berg bool fw_reset_handshake; 406e705c121SKalle Valo }; 407e705c121SKalle Valo 408e705c121SKalle Valo struct iwl_trans_dump_data { 409e705c121SKalle Valo u32 len; 410e705c121SKalle Valo u8 data[]; 411e705c121SKalle Valo }; 412e705c121SKalle Valo 413e705c121SKalle Valo struct iwl_trans; 414e705c121SKalle Valo 415e705c121SKalle Valo struct iwl_trans_txq_scd_cfg { 416e705c121SKalle Valo u8 fifo; 4172a2e9d10SLiad Kaufman u8 sta_id; 418e705c121SKalle Valo u8 tid; 419e705c121SKalle Valo bool aggregate; 420e705c121SKalle Valo int frame_limit; 421e705c121SKalle Valo }; 422e705c121SKalle Valo 4236b35ff91SSara Sharon /** 42492536c96SSara Sharon * struct iwl_trans_rxq_dma_data - RX queue DMA data 42592536c96SSara Sharon * @fr_bd_cb: DMA address of free BD cyclic buffer 42692536c96SSara Sharon * @fr_bd_wid: Initial write index of the free BD cyclic buffer 42792536c96SSara Sharon * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 42892536c96SSara Sharon * @ur_bd_cb: DMA address of used BD cyclic buffer 42992536c96SSara Sharon */ 43092536c96SSara Sharon struct iwl_trans_rxq_dma_data { 43192536c96SSara Sharon u64 fr_bd_cb; 43292536c96SSara Sharon u32 fr_bd_wid; 43392536c96SSara Sharon u64 urbd_stts_wrptr; 43492536c96SSara Sharon u64 ur_bd_cb; 43592536c96SSara Sharon }; 43692536c96SSara Sharon 43792536c96SSara Sharon /** 438e705c121SKalle Valo * struct iwl_trans_ops - transport specific operations 439e705c121SKalle Valo * 440e705c121SKalle Valo * All the handlers MUST be implemented 441e705c121SKalle Valo * 442bab3cb92SEmmanuel Grumbach * @start_hw: starts the HW. From that point on, the HW can send interrupts. 443bab3cb92SEmmanuel Grumbach * May sleep. 444e705c121SKalle Valo * @op_mode_leave: Turn off the HW RF kill indication if on 445e705c121SKalle Valo * May sleep 446e705c121SKalle Valo * @start_fw: allocates and inits all the resources for the transport 447e705c121SKalle Valo * layer. Also kick a fw image. 448e705c121SKalle Valo * May sleep 449e705c121SKalle Valo * @fw_alive: called when the fw sends alive notification. If the fw provides 450e705c121SKalle Valo * the SCD base address in SRAM, then provide it here, or 0 otherwise. 451e705c121SKalle Valo * May sleep 452e705c121SKalle Valo * @stop_device: stops the whole device (embedded CPU put to reset) and stops 453bab3cb92SEmmanuel Grumbach * the HW. From that point on, the HW will be stopped but will still issue 454bab3cb92SEmmanuel Grumbach * an interrupt if the HW RF kill switch is triggered. 455e705c121SKalle Valo * This callback must do the right thing and not crash even if %start_hw() 456e705c121SKalle Valo * was called but not &start_fw(). May sleep. 457e705c121SKalle Valo * @d3_suspend: put the device into the correct mode for WoWLAN during 458e705c121SKalle Valo * suspend. This is optional, if not implemented WoWLAN will not be 459e705c121SKalle Valo * supported. This callback may sleep. 460e705c121SKalle Valo * @d3_resume: resume the device after WoWLAN, enabling the opmode to 461e705c121SKalle Valo * talk to the WoWLAN image to get its status. This is optional, if not 462e705c121SKalle Valo * implemented WoWLAN will not be supported. This callback may sleep. 463e705c121SKalle Valo * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 464e705c121SKalle Valo * If RFkill is asserted in the middle of a SYNC host command, it must 465e705c121SKalle Valo * return -ERFKILL straight away. 466e705c121SKalle Valo * May sleep only if CMD_ASYNC is not set 4673f73b8caSEmmanuel Grumbach * @tx: send an skb. The transport relies on the op_mode to zero the 4686eb5e529SEmmanuel Grumbach * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 4696eb5e529SEmmanuel Grumbach * the CSUM will be taken care of (TCP CSUM and IP header in case of 4706eb5e529SEmmanuel Grumbach * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 4716eb5e529SEmmanuel Grumbach * header if it is IPv4. 472e705c121SKalle Valo * Must be atomic 473e705c121SKalle Valo * @reclaim: free packet until ssn. Returns a list of freed packets. 474e705c121SKalle Valo * Must be atomic 475e705c121SKalle Valo * @txq_enable: setup a queue. To setup an AC queue, use the 476e705c121SKalle Valo * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 477e705c121SKalle Valo * this one. The op_mode must not configure the HCMD queue. The scheduler 478e705c121SKalle Valo * configuration may be %NULL, in which case the hardware will not be 479dcfbd67bSEmmanuel Grumbach * configured. If true is returned, the operation mode needs to increment 480dcfbd67bSEmmanuel Grumbach * the sequence number of the packets routed to this queue because of a 481dcfbd67bSEmmanuel Grumbach * hardware scheduler bug. May sleep. 482e705c121SKalle Valo * @txq_disable: de-configure a Tx queue to send AMPDUs 483e705c121SKalle Valo * Must be atomic 48442db09c1SLiad Kaufman * @txq_set_shared_mode: change Tx queue shared/unshared marking 485d6d517b7SSara Sharon * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 486d6d517b7SSara Sharon * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 487e705c121SKalle Valo * @freeze_txq_timer: prevents the timer of the queue from firing until the 488e705c121SKalle Valo * queue is set to awake. Must be atomic. 4890cd58eaaSEmmanuel Grumbach * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 4900cd58eaaSEmmanuel Grumbach * that the transport needs to refcount the calls since this function 4910cd58eaaSEmmanuel Grumbach * will be called several times with block = true, and then the queues 4920cd58eaaSEmmanuel Grumbach * need to be unblocked only after the same number of calls with 4930cd58eaaSEmmanuel Grumbach * block = false. 494e705c121SKalle Valo * @write8: write a u8 to a register at offset ofs from the BAR 495e705c121SKalle Valo * @write32: write a u32 to a register at offset ofs from the BAR 496e705c121SKalle Valo * @read32: read a u32 register at offset ofs from the BAR 497e705c121SKalle Valo * @read_prph: read a DWORD from a periphery register 498e705c121SKalle Valo * @write_prph: write a DWORD to a periphery register 499e705c121SKalle Valo * @read_mem: read device's SRAM in DWORD 500e705c121SKalle Valo * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 501e705c121SKalle Valo * will be zeroed. 502f696a7eeSLuca Coelho * @read_config32: read a u32 value from the device's config space at 503f696a7eeSLuca Coelho * the given offset. 504e705c121SKalle Valo * @configure: configure parameters required by the transport layer from 505e705c121SKalle Valo * the op_mode. May be called several times before start_fw, can't be 506e705c121SKalle Valo * called after that. 507e705c121SKalle Valo * @set_pmi: set the power pmi state 508e705c121SKalle Valo * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 509e705c121SKalle Valo * Sleeping is not allowed between grab_nic_access and 510e705c121SKalle Valo * release_nic_access. 511e705c121SKalle Valo * @release_nic_access: let the NIC go to sleep. The "flags" parameter 512e705c121SKalle Valo * must be the same one that was sent before to the grab_nic_access. 513e705c121SKalle Valo * @set_bits_mask - set SRAM register according to value and mask. 514e705c121SKalle Valo * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 515e705c121SKalle Valo * TX'ed commands and similar. The buffer will be vfree'd by the caller. 516e705c121SKalle Valo * Note that the transport must fill in the proper file headers. 517f7805b33SLior Cohen * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 518f7805b33SLior Cohen * of the trans debugfs 519a182dfabSLuca Coelho * @set_pnvm: set the pnvm data in the prph scratch buffer, inside the 520a182dfabSLuca Coelho * context info. 5213161a34dSMordechay Goodstein * @interrupts: disable/enable interrupts to transport 522e705c121SKalle Valo */ 523e705c121SKalle Valo struct iwl_trans_ops { 524e705c121SKalle Valo 525bab3cb92SEmmanuel Grumbach int (*start_hw)(struct iwl_trans *iwl_trans); 526e705c121SKalle Valo void (*op_mode_leave)(struct iwl_trans *iwl_trans); 527e705c121SKalle Valo int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 528e705c121SKalle Valo bool run_in_rfkill); 529e705c121SKalle Valo void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 530bab3cb92SEmmanuel Grumbach void (*stop_device)(struct iwl_trans *trans); 531e705c121SKalle Valo 532e5f3f215SHaim Dreyfuss int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 533e705c121SKalle Valo int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 53423ae6128SMatti Gottlieb bool test, bool reset); 535e705c121SKalle Valo 536e705c121SKalle Valo int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 537e705c121SKalle Valo 538e705c121SKalle Valo int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 539a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue); 540e705c121SKalle Valo void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 541e705c121SKalle Valo struct sk_buff_head *skbs); 542e705c121SKalle Valo 543ba7136f3SAlex Malamud void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 544ba7136f3SAlex Malamud 545dcfbd67bSEmmanuel Grumbach bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 546e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 547e705c121SKalle Valo unsigned int queue_wdg_timeout); 548e705c121SKalle Valo void (*txq_disable)(struct iwl_trans *trans, int queue, 549e705c121SKalle Valo bool configure_scd); 5502f7a3863SLuca Coelho /* 22000 functions */ 5516b35ff91SSara Sharon int (*txq_alloc)(struct iwl_trans *trans, 5521169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 5535369774cSSara Sharon int cmd_id, int size, 5546b35ff91SSara Sharon unsigned int queue_wdg_timeout); 5556b35ff91SSara Sharon void (*txq_free)(struct iwl_trans *trans, int queue); 55692536c96SSara Sharon int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 55792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data); 558e705c121SKalle Valo 55942db09c1SLiad Kaufman void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 56042db09c1SLiad Kaufman bool shared); 56142db09c1SLiad Kaufman 562a1a57877SSara Sharon int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 563d6d517b7SSara Sharon int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 564e705c121SKalle Valo void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 565e705c121SKalle Valo bool freeze); 5660cd58eaaSEmmanuel Grumbach void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 567e705c121SKalle Valo 568e705c121SKalle Valo void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 569e705c121SKalle Valo void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 570e705c121SKalle Valo u32 (*read32)(struct iwl_trans *trans, u32 ofs); 571e705c121SKalle Valo u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 572e705c121SKalle Valo void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 573e705c121SKalle Valo int (*read_mem)(struct iwl_trans *trans, u32 addr, 574e705c121SKalle Valo void *buf, int dwords); 575e705c121SKalle Valo int (*write_mem)(struct iwl_trans *trans, u32 addr, 576e705c121SKalle Valo const void *buf, int dwords); 577f696a7eeSLuca Coelho int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 578e705c121SKalle Valo void (*configure)(struct iwl_trans *trans, 579e705c121SKalle Valo const struct iwl_trans_config *trans_cfg); 580e705c121SKalle Valo void (*set_pmi)(struct iwl_trans *trans, bool state); 581870c2a11SGolan Ben Ami void (*sw_reset)(struct iwl_trans *trans); 5821ed08f6fSJohannes Berg bool (*grab_nic_access)(struct iwl_trans *trans); 5831ed08f6fSJohannes Berg void (*release_nic_access)(struct iwl_trans *trans); 584e705c121SKalle Valo void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 585e705c121SKalle Valo u32 value); 586e705c121SKalle Valo 587e705c121SKalle Valo struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 58879f033f6SSara Sharon u32 dump_mask); 589f7805b33SLior Cohen void (*debugfs_cleanup)(struct iwl_trans *trans); 590d1967ce6SShahar S Matityahu void (*sync_nmi)(struct iwl_trans *trans); 591a182dfabSLuca Coelho int (*set_pnvm)(struct iwl_trans *trans, const void *data, u32 len); 592*9dad325fSLuca Coelho int (*set_reduce_power)(struct iwl_trans *trans, 593*9dad325fSLuca Coelho const void *data, u32 len); 5943161a34dSMordechay Goodstein void (*interrupts)(struct iwl_trans *trans, bool enable); 595e705c121SKalle Valo }; 596e705c121SKalle Valo 597e705c121SKalle Valo /** 598e705c121SKalle Valo * enum iwl_trans_state - state of the transport layer 599e705c121SKalle Valo * 600b2ed841eSJohannes Berg * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 601b2ed841eSJohannes Berg * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 602b2ed841eSJohannes Berg * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 603e705c121SKalle Valo */ 604e705c121SKalle Valo enum iwl_trans_state { 605b2ed841eSJohannes Berg IWL_TRANS_NO_FW, 606b2ed841eSJohannes Berg IWL_TRANS_FW_STARTED, 607b2ed841eSJohannes Berg IWL_TRANS_FW_ALIVE, 608e705c121SKalle Valo }; 609e705c121SKalle Valo 610e705c121SKalle Valo /** 611b7282643SLuca Coelho * DOC: Platform power management 612e705c121SKalle Valo * 613b7282643SLuca Coelho * In system-wide power management the entire platform goes into a low 614b7282643SLuca Coelho * power state (e.g. idle or suspend to RAM) at the same time and the 615b7282643SLuca Coelho * device is configured as a wakeup source for the entire platform. 616b7282643SLuca Coelho * This is usually triggered by userspace activity (e.g. the user 617b7282643SLuca Coelho * presses the suspend button or a power management daemon decides to 618b7282643SLuca Coelho * put the platform in low power mode). The device's behavior in this 619b7282643SLuca Coelho * mode is dictated by the wake-on-WLAN configuration. 620b7282643SLuca Coelho * 621b7282643SLuca Coelho * The terms used for the device's behavior are as follows: 622b7282643SLuca Coelho * 623b7282643SLuca Coelho * - D0: the device is fully powered and the host is awake; 624b7282643SLuca Coelho * - D3: the device is in low power mode and only reacts to 625b7282643SLuca Coelho * specific events (e.g. magic-packet received or scan 626b7282643SLuca Coelho * results found); 627b7282643SLuca Coelho * 628b7282643SLuca Coelho * These terms reflect the power modes in the firmware and are not to 629f60e2750SEmmanuel Grumbach * be confused with the physical device power state. 630e705c121SKalle Valo */ 631b7282643SLuca Coelho 632b7282643SLuca Coelho /** 633b7282643SLuca Coelho * enum iwl_plat_pm_mode - platform power management mode 634b7282643SLuca Coelho * 635b7282643SLuca Coelho * This enumeration describes the device's platform power management 636f60e2750SEmmanuel Grumbach * behavior when in system-wide suspend (i.e WoWLAN). 637b7282643SLuca Coelho * 638b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 639f60e2750SEmmanuel Grumbach * device. In system-wide suspend mode, it means that the all 640f60e2750SEmmanuel Grumbach * connections will be closed automatically by mac80211 before 641f60e2750SEmmanuel Grumbach * the platform is suspended. 642b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 643b7282643SLuca Coelho */ 644b7282643SLuca Coelho enum iwl_plat_pm_mode { 645b7282643SLuca Coelho IWL_PLAT_PM_MODE_DISABLED, 646b7282643SLuca Coelho IWL_PLAT_PM_MODE_D3, 647e705c121SKalle Valo }; 648e705c121SKalle Valo 649341bd290SShahar S Matityahu /** 650341bd290SShahar S Matityahu * enum iwl_ini_cfg_state 651341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 652341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 653341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 654341bd290SShahar S Matityahu * are corrupted. The rest of the debug TLVs will still be used 655341bd290SShahar S Matityahu */ 656341bd290SShahar S Matityahu enum iwl_ini_cfg_state { 657341bd290SShahar S Matityahu IWL_INI_CFG_STATE_NOT_LOADED, 658341bd290SShahar S Matityahu IWL_INI_CFG_STATE_LOADED, 659341bd290SShahar S Matityahu IWL_INI_CFG_STATE_CORRUPTED, 660341bd290SShahar S Matityahu }; 661341bd290SShahar S Matityahu 662b8a7547dSShahar S Matityahu /* Max time to wait for nmi interrupt */ 663b8a7547dSShahar S Matityahu #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 664b8a7547dSShahar S Matityahu 66588964b2eSSara Sharon /** 66688964b2eSSara Sharon * struct iwl_dram_data 66788964b2eSSara Sharon * @physical: page phy pointer 66888964b2eSSara Sharon * @block: pointer to the allocated block/page 66988964b2eSSara Sharon * @size: size of the block/page 67088964b2eSSara Sharon */ 67188964b2eSSara Sharon struct iwl_dram_data { 67288964b2eSSara Sharon dma_addr_t physical; 67388964b2eSSara Sharon void *block; 67488964b2eSSara Sharon int size; 67588964b2eSSara Sharon }; 6764cbb8e50SLuciano Coelho 677e705c121SKalle Valo /** 678593fae3eSShahar S Matityahu * struct iwl_fw_mon - fw monitor per allocation id 679593fae3eSShahar S Matityahu * @num_frags: number of fragments 680593fae3eSShahar S Matityahu * @frags: an array of DRAM buffer fragments 681593fae3eSShahar S Matityahu */ 682593fae3eSShahar S Matityahu struct iwl_fw_mon { 683593fae3eSShahar S Matityahu u32 num_frags; 684593fae3eSShahar S Matityahu struct iwl_dram_data *frags; 685593fae3eSShahar S Matityahu }; 686593fae3eSShahar S Matityahu 687593fae3eSShahar S Matityahu /** 688505a00c0SShahar S Matityahu * struct iwl_self_init_dram - dram data used by self init process 689505a00c0SShahar S Matityahu * @fw: lmac and umac dram data 690505a00c0SShahar S Matityahu * @fw_cnt: total number of items in array 691505a00c0SShahar S Matityahu * @paging: paging dram data 692505a00c0SShahar S Matityahu * @paging_cnt: total number of items in array 693505a00c0SShahar S Matityahu */ 694505a00c0SShahar S Matityahu struct iwl_self_init_dram { 695505a00c0SShahar S Matityahu struct iwl_dram_data *fw; 696505a00c0SShahar S Matityahu int fw_cnt; 697505a00c0SShahar S Matityahu struct iwl_dram_data *paging; 698505a00c0SShahar S Matityahu int paging_cnt; 699505a00c0SShahar S Matityahu }; 700505a00c0SShahar S Matityahu 701505a00c0SShahar S Matityahu /** 70291c28b83SShahar S Matityahu * struct iwl_trans_debug - transport debug related data 70391c28b83SShahar S Matityahu * 70491c28b83SShahar S Matityahu * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 70591c28b83SShahar S Matityahu * @rec_on: true iff there is a fw debug recording currently active 70691c28b83SShahar S Matityahu * @dest_tlv: points to the destination TLV for debug 70791c28b83SShahar S Matityahu * @conf_tlv: array of pointers to configuration TLVs for debug 70891c28b83SShahar S Matityahu * @trigger_tlv: array of pointers to triggers TLVs for debug 70991c28b83SShahar S Matityahu * @lmac_error_event_table: addrs of lmacs error tables 71091c28b83SShahar S Matityahu * @umac_error_event_table: addr of umac error table 71191c28b83SShahar S Matityahu * @error_event_table_tlv_status: bitmap that indicates what error table 71291c28b83SShahar S Matityahu * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 713341bd290SShahar S Matityahu * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 714341bd290SShahar S Matityahu * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 715593fae3eSShahar S Matityahu * @fw_mon_cfg: debug buffer allocation configuration 716593fae3eSShahar S Matityahu * @fw_mon_ini: DRAM buffer fragments per allocation id 71769f0e505SShahar S Matityahu * @fw_mon: DRAM buffer for firmware monitor 71891c28b83SShahar S Matityahu * @hw_error: equals true if hw error interrupt was received from the FW 719029c25f3SShahar S Matityahu * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 7203b589d56SShahar S Matityahu * @active_regions: active regions 721677d25b2SShahar S Matityahu * @debug_info_tlv_list: list of debug info TLVs 722a9248de4SShahar S Matityahu * @time_point: array of debug time points 72360e8abd9SShahar S Matityahu * @periodic_trig_list: periodic triggers list 724cf29c5b6SShahar S Matityahu * @domains_bitmap: bitmap of active domains other than 725cf29c5b6SShahar S Matityahu * &IWL_FW_INI_DOMAIN_ALWAYS_ON 72691c28b83SShahar S Matityahu */ 72791c28b83SShahar S Matityahu struct iwl_trans_debug { 72891c28b83SShahar S Matityahu u8 n_dest_reg; 72991c28b83SShahar S Matityahu bool rec_on; 73091c28b83SShahar S Matityahu 73191c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 73291c28b83SShahar S Matityahu const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 73391c28b83SShahar S Matityahu struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 73491c28b83SShahar S Matityahu 73591c28b83SShahar S Matityahu u32 lmac_error_event_table[2]; 73691c28b83SShahar S Matityahu u32 umac_error_event_table; 73791c28b83SShahar S Matityahu unsigned int error_event_table_tlv_status; 73891c28b83SShahar S Matityahu 739341bd290SShahar S Matityahu enum iwl_ini_cfg_state internal_ini_cfg; 740341bd290SShahar S Matityahu enum iwl_ini_cfg_state external_ini_cfg; 74191c28b83SShahar S Matityahu 742593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 743593fae3eSShahar S Matityahu struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 744593fae3eSShahar S Matityahu 74569f0e505SShahar S Matityahu struct iwl_dram_data fw_mon; 74691c28b83SShahar S Matityahu 74791c28b83SShahar S Matityahu bool hw_error; 748029c25f3SShahar S Matityahu enum iwl_fw_ini_buffer_location ini_dest; 7493b589d56SShahar S Matityahu 750beb44c0cSMordechay Goodstein u64 unsupported_region_msk; 7513b589d56SShahar S Matityahu struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 752677d25b2SShahar S Matityahu struct list_head debug_info_tlv_list; 753a9248de4SShahar S Matityahu struct iwl_dbg_tlv_time_point_data 754a9248de4SShahar S Matityahu time_point[IWL_FW_INI_TIME_POINT_NUM]; 75560e8abd9SShahar S Matityahu struct list_head periodic_trig_list; 756cf29c5b6SShahar S Matityahu 757cf29c5b6SShahar S Matityahu u32 domains_bitmap; 75891c28b83SShahar S Matityahu }; 75991c28b83SShahar S Matityahu 7604807e736SMordechay Goodstein struct iwl_dma_ptr { 7614807e736SMordechay Goodstein dma_addr_t dma; 7624807e736SMordechay Goodstein void *addr; 7634807e736SMordechay Goodstein size_t size; 7644807e736SMordechay Goodstein }; 7654807e736SMordechay Goodstein 7664807e736SMordechay Goodstein struct iwl_cmd_meta { 7674807e736SMordechay Goodstein /* only for SYNC commands, iff the reply skb is wanted */ 7684807e736SMordechay Goodstein struct iwl_host_cmd *source; 7694807e736SMordechay Goodstein u32 flags; 7704807e736SMordechay Goodstein u32 tbs; 7714807e736SMordechay Goodstein }; 7724807e736SMordechay Goodstein 7734807e736SMordechay Goodstein /* 7744807e736SMordechay Goodstein * The FH will write back to the first TB only, so we need to copy some data 7754807e736SMordechay Goodstein * into the buffer regardless of whether it should be mapped or not. 7764807e736SMordechay Goodstein * This indicates how big the first TB must be to include the scratch buffer 7774807e736SMordechay Goodstein * and the assigned PN. 7784807e736SMordechay Goodstein * Since PN location is 8 bytes at offset 12, it's 20 now. 7794807e736SMordechay Goodstein * If we make it bigger then allocations will be bigger and copy slower, so 7804807e736SMordechay Goodstein * that's probably not useful. 7814807e736SMordechay Goodstein */ 7824807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE 20 7834807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 7844807e736SMordechay Goodstein 7854807e736SMordechay Goodstein struct iwl_pcie_txq_entry { 7864807e736SMordechay Goodstein void *cmd; 7874807e736SMordechay Goodstein struct sk_buff *skb; 7884807e736SMordechay Goodstein /* buffer to free after command completes */ 7894807e736SMordechay Goodstein const void *free_buf; 7904807e736SMordechay Goodstein struct iwl_cmd_meta meta; 7914807e736SMordechay Goodstein }; 7924807e736SMordechay Goodstein 7934807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf { 7944807e736SMordechay Goodstein u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 7954807e736SMordechay Goodstein }; 7964807e736SMordechay Goodstein 7974807e736SMordechay Goodstein /** 7984807e736SMordechay Goodstein * struct iwl_txq - Tx Queue for DMA 7994807e736SMordechay Goodstein * @q: generic Rx/Tx queue descriptor 8004807e736SMordechay Goodstein * @tfds: transmit frame descriptors (DMA memory) 8014807e736SMordechay Goodstein * @first_tb_bufs: start of command headers, including scratch buffers, for 8024807e736SMordechay Goodstein * the writeback -- this is DMA memory and an array holding one buffer 8034807e736SMordechay Goodstein * for each command on the queue 8044807e736SMordechay Goodstein * @first_tb_dma: DMA address for the first_tb_bufs start 8054807e736SMordechay Goodstein * @entries: transmit entries (driver state) 8064807e736SMordechay Goodstein * @lock: queue lock 8074807e736SMordechay Goodstein * @stuck_timer: timer that fires if queue gets stuck 8084807e736SMordechay Goodstein * @trans: pointer back to transport (for timer) 8094807e736SMordechay Goodstein * @need_update: indicates need to update read/write index 8104807e736SMordechay Goodstein * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 8114807e736SMordechay Goodstein * @wd_timeout: queue watchdog timeout (jiffies) - per queue 8124807e736SMordechay Goodstein * @frozen: tx stuck queue timer is frozen 8134807e736SMordechay Goodstein * @frozen_expiry_remainder: remember how long until the timer fires 8144807e736SMordechay Goodstein * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 8154807e736SMordechay Goodstein * @write_ptr: 1-st empty entry (index) host_w 8164807e736SMordechay Goodstein * @read_ptr: last used entry (index) host_r 8174807e736SMordechay Goodstein * @dma_addr: physical addr for BD's 8184807e736SMordechay Goodstein * @n_window: safe queue window 8194807e736SMordechay Goodstein * @id: queue id 8204807e736SMordechay Goodstein * @low_mark: low watermark, resume queue if free space more than this 8214807e736SMordechay Goodstein * @high_mark: high watermark, stop queue if free space less than this 8224807e736SMordechay Goodstein * 8234807e736SMordechay Goodstein * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 8244807e736SMordechay Goodstein * descriptors) and required locking structures. 8254807e736SMordechay Goodstein * 8264807e736SMordechay Goodstein * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 8274807e736SMordechay Goodstein * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 8284807e736SMordechay Goodstein * there might be HW changes in the future). For the normal TX 8294807e736SMordechay Goodstein * queues, n_window, which is the size of the software queue data 8304807e736SMordechay Goodstein * is also 256; however, for the command queue, n_window is only 8314807e736SMordechay Goodstein * 32 since we don't need so many commands pending. Since the HW 8324807e736SMordechay Goodstein * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 8334807e736SMordechay Goodstein * This means that we end up with the following: 8344807e736SMordechay Goodstein * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 8354807e736SMordechay Goodstein * SW entries: | 0 | ... | 31 | 8364807e736SMordechay Goodstein * where N is a number between 0 and 7. This means that the SW 8374807e736SMordechay Goodstein * data is a window overlayed over the HW queue. 8384807e736SMordechay Goodstein */ 8394807e736SMordechay Goodstein struct iwl_txq { 8404807e736SMordechay Goodstein void *tfds; 8414807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf *first_tb_bufs; 8424807e736SMordechay Goodstein dma_addr_t first_tb_dma; 8434807e736SMordechay Goodstein struct iwl_pcie_txq_entry *entries; 8444807e736SMordechay Goodstein /* lock for syncing changes on the queue */ 8454807e736SMordechay Goodstein spinlock_t lock; 8464807e736SMordechay Goodstein unsigned long frozen_expiry_remainder; 8474807e736SMordechay Goodstein struct timer_list stuck_timer; 8484807e736SMordechay Goodstein struct iwl_trans *trans; 8494807e736SMordechay Goodstein bool need_update; 8504807e736SMordechay Goodstein bool frozen; 8514807e736SMordechay Goodstein bool ampdu; 8524807e736SMordechay Goodstein int block; 8534807e736SMordechay Goodstein unsigned long wd_timeout; 8544807e736SMordechay Goodstein struct sk_buff_head overflow_q; 8554807e736SMordechay Goodstein struct iwl_dma_ptr bc_tbl; 8564807e736SMordechay Goodstein 8574807e736SMordechay Goodstein int write_ptr; 8584807e736SMordechay Goodstein int read_ptr; 8594807e736SMordechay Goodstein dma_addr_t dma_addr; 8604807e736SMordechay Goodstein int n_window; 8614807e736SMordechay Goodstein u32 id; 8624807e736SMordechay Goodstein int low_mark; 8634807e736SMordechay Goodstein int high_mark; 8644807e736SMordechay Goodstein 8654807e736SMordechay Goodstein bool overflow_tx; 8664807e736SMordechay Goodstein }; 8674f4822b7SMordechay Goodstein 8684f4822b7SMordechay Goodstein /** 8694f4822b7SMordechay Goodstein * struct iwl_trans_txqs - transport tx queues data 8704f4822b7SMordechay Goodstein * 8718e3b79f8SMordechay Goodstein * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 87222852fadSMordechay Goodstein * @page_offs: offset from skb->cb to mac header page pointer 87322852fadSMordechay Goodstein * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 8744f4822b7SMordechay Goodstein * @queue_used - bit mask of used queues 8754f4822b7SMordechay Goodstein * @queue_stopped - bit mask of stopped queues 8760179bfffSMordechay Goodstein * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 8774f4822b7SMordechay Goodstein */ 8784f4822b7SMordechay Goodstein struct iwl_trans_txqs { 8794f4822b7SMordechay Goodstein unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 8804f4822b7SMordechay Goodstein unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 8814f4822b7SMordechay Goodstein struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 882a26014e2SMordechay Goodstein struct dma_pool *bc_pool; 883a26014e2SMordechay Goodstein size_t bc_tbl_size; 8848e3b79f8SMordechay Goodstein bool bc_table_dword; 88522852fadSMordechay Goodstein u8 page_offs; 88622852fadSMordechay Goodstein u8 dev_cmd_offs; 8870cd1ad2dSMordechay Goodstein struct __percpu iwl_tso_hdr_page * tso_hdr_page; 8888e3b79f8SMordechay Goodstein 8894f4822b7SMordechay Goodstein struct { 8904f4822b7SMordechay Goodstein u8 fifo; 8914f4822b7SMordechay Goodstein u8 q_id; 8924f4822b7SMordechay Goodstein unsigned int wdg_timeout; 8934f4822b7SMordechay Goodstein } cmd; 8944f4822b7SMordechay Goodstein 895885375d0SMordechay Goodstein struct { 896885375d0SMordechay Goodstein u8 max_tbs; 897885375d0SMordechay Goodstein u16 size; 898885375d0SMordechay Goodstein u8 addr_size; 899885375d0SMordechay Goodstein } tfd; 9000179bfffSMordechay Goodstein 9010179bfffSMordechay Goodstein struct iwl_dma_ptr scd_bc_tbls; 9024f4822b7SMordechay Goodstein }; 9034f4822b7SMordechay Goodstein 90491c28b83SShahar S Matityahu /** 905e705c121SKalle Valo * struct iwl_trans - transport common data 906e705c121SKalle Valo * 907e705c121SKalle Valo * @ops - pointer to iwl_trans_ops 908e705c121SKalle Valo * @op_mode - pointer to the op_mode 909286ca8ebSLuca Coelho * @trans_cfg: the trans-specific configuration part 910e705c121SKalle Valo * @cfg - pointer to the configuration 9116f482e37SSara Sharon * @drv - pointer to iwl_drv 912e705c121SKalle Valo * @status: a bit-mask of transport status flags 913e705c121SKalle Valo * @dev - pointer to struct device * that represents the device 914e705c121SKalle Valo * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 915e705c121SKalle Valo * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 9161afb0ae4SHaim Dreyfuss * @hw_rf_id a u32 with the device RF ID 917e705c121SKalle Valo * @hw_id: a u32 with the ID of the device / sub-device. 918e705c121SKalle Valo * Set during transport allocation. 919e705c121SKalle Valo * @hw_id_str: a string with info about HW ID. Set during transport allocation. 920e705c121SKalle Valo * @pm_support: set to true in start_hw if link pm is supported 921e705c121SKalle Valo * @ltr_enabled: set to true if the LTR is enabled 922b7d96bcaSLuca Coelho * @wide_cmd_header: true when ucode supports wide command header format 92313f028b4SMordechay Goodstein * @wait_command_queue: wait queue for sync commands 924e705c121SKalle Valo * @num_rx_queues: number of RX queues allocated by the transport; 925e705c121SKalle Valo * the transport must set this before calling iwl_drv_start() 926132db31cSGolan Ben-Ami * @iml_len: the length of the image loader 927132db31cSGolan Ben-Ami * @iml: a pointer to the image loader itself 928e705c121SKalle Valo * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 929e705c121SKalle Valo * The user should use iwl_trans_{alloc,free}_tx_cmd. 930e705c121SKalle Valo * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 931e705c121SKalle Valo * starting the firmware, used for tracing 932e705c121SKalle Valo * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 933e705c121SKalle Valo * start of the 802.11 header in the @rx_mpdu_cmd 934e705c121SKalle Valo * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 935b7282643SLuca Coelho * @system_pm_mode: the system-wide power management mode in use. 936b7282643SLuca Coelho * This mode is set dynamically, depending on the WoWLAN values 937b7282643SLuca Coelho * configured from the userspace at runtime. 9384f4822b7SMordechay Goodstein * @iwl_trans_txqs: transport tx queues data. 939e705c121SKalle Valo */ 940e705c121SKalle Valo struct iwl_trans { 941e705c121SKalle Valo const struct iwl_trans_ops *ops; 942e705c121SKalle Valo struct iwl_op_mode *op_mode; 943286ca8ebSLuca Coelho const struct iwl_cfg_trans_params *trans_cfg; 944e705c121SKalle Valo const struct iwl_cfg *cfg; 9456f482e37SSara Sharon struct iwl_drv *drv; 946e705c121SKalle Valo enum iwl_trans_state state; 947e705c121SKalle Valo unsigned long status; 948e705c121SKalle Valo 949e705c121SKalle Valo struct device *dev; 950e705c121SKalle Valo u32 max_skb_frags; 951e705c121SKalle Valo u32 hw_rev; 9521afb0ae4SHaim Dreyfuss u32 hw_rf_id; 953e705c121SKalle Valo u32 hw_id; 954e705c121SKalle Valo char hw_id_str[52]; 95590824f2fSLuca Coelho u32 sku_id[3]; 956e705c121SKalle Valo 957e705c121SKalle Valo u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 958e705c121SKalle Valo 959e705c121SKalle Valo bool pm_support; 960e705c121SKalle Valo bool ltr_enabled; 96169725928SLuca Coelho u8 pnvm_loaded:1; 962*9dad325fSLuca Coelho u8 reduce_power_loaded:1; 963e705c121SKalle Valo 96439bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 96539bdb17eSSharon Dvir int command_groups_size; 966b7d96bcaSLuca Coelho bool wide_cmd_header; 96739bdb17eSSharon Dvir 96813f028b4SMordechay Goodstein wait_queue_head_t wait_command_queue; 969e705c121SKalle Valo u8 num_rx_queues; 970e705c121SKalle Valo 971132db31cSGolan Ben-Ami size_t iml_len; 972132db31cSGolan Ben-Ami u8 *iml; 973132db31cSGolan Ben-Ami 974e705c121SKalle Valo /* The following fields are internal only */ 975e705c121SKalle Valo struct kmem_cache *dev_cmd_pool; 976e705c121SKalle Valo char dev_cmd_pool_name[50]; 977e705c121SKalle Valo 978e705c121SKalle Valo struct dentry *dbgfs_dir; 979e705c121SKalle Valo 980e705c121SKalle Valo #ifdef CONFIG_LOCKDEP 981e705c121SKalle Valo struct lockdep_map sync_cmd_lockdep_map; 982e705c121SKalle Valo #endif 983e705c121SKalle Valo 98491c28b83SShahar S Matityahu struct iwl_trans_debug dbg; 985505a00c0SShahar S Matityahu struct iwl_self_init_dram init_dram; 986e705c121SKalle Valo 987b7282643SLuca Coelho enum iwl_plat_pm_mode system_pm_mode; 988700b3799SShahar S Matityahu 9890b295a1eSLuca Coelho const char *name; 9904f4822b7SMordechay Goodstein struct iwl_trans_txqs txqs; 9910b295a1eSLuca Coelho 992e705c121SKalle Valo /* pointer to trans specific struct */ 993e705c121SKalle Valo /*Ensure that this pointer will always be aligned to sizeof pointer */ 99445c21a0eSGustavo A. R. Silva char trans_specific[] __aligned(sizeof(void *)); 995e705c121SKalle Valo }; 996e705c121SKalle Valo 99739bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 99839bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 99939bdb17eSSharon Dvir 1000e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans, 1001e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1002e705c121SKalle Valo { 1003e705c121SKalle Valo trans->op_mode = trans_cfg->op_mode; 1004e705c121SKalle Valo 1005e705c121SKalle Valo trans->ops->configure(trans, trans_cfg); 100639bdb17eSSharon Dvir WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1007e705c121SKalle Valo } 1008e705c121SKalle Valo 1009bab3cb92SEmmanuel Grumbach static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1010e705c121SKalle Valo { 1011e705c121SKalle Valo might_sleep(); 1012e705c121SKalle Valo 1013bab3cb92SEmmanuel Grumbach return trans->ops->start_hw(trans); 1014e705c121SKalle Valo } 1015e705c121SKalle Valo 1016e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1017e705c121SKalle Valo { 1018e705c121SKalle Valo might_sleep(); 1019e705c121SKalle Valo 1020e705c121SKalle Valo if (trans->ops->op_mode_leave) 1021e705c121SKalle Valo trans->ops->op_mode_leave(trans); 1022e705c121SKalle Valo 1023e705c121SKalle Valo trans->op_mode = NULL; 1024e705c121SKalle Valo 1025e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1026e705c121SKalle Valo } 1027e705c121SKalle Valo 1028e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1029e705c121SKalle Valo { 1030e705c121SKalle Valo might_sleep(); 1031e705c121SKalle Valo 1032e705c121SKalle Valo trans->state = IWL_TRANS_FW_ALIVE; 1033e705c121SKalle Valo 1034e705c121SKalle Valo trans->ops->fw_alive(trans, scd_addr); 1035e705c121SKalle Valo } 1036e705c121SKalle Valo 1037e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1038e705c121SKalle Valo const struct fw_img *fw, 1039e705c121SKalle Valo bool run_in_rfkill) 1040e705c121SKalle Valo { 1041b2ed841eSJohannes Berg int ret; 1042b2ed841eSJohannes Berg 1043e705c121SKalle Valo might_sleep(); 1044e705c121SKalle Valo 1045e705c121SKalle Valo WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1046e705c121SKalle Valo 1047e705c121SKalle Valo clear_bit(STATUS_FW_ERROR, &trans->status); 1048b2ed841eSJohannes Berg ret = trans->ops->start_fw(trans, fw, run_in_rfkill); 1049b2ed841eSJohannes Berg if (ret == 0) 1050b2ed841eSJohannes Berg trans->state = IWL_TRANS_FW_STARTED; 1051b2ed841eSJohannes Berg 1052b2ed841eSJohannes Berg return ret; 1053e705c121SKalle Valo } 1054e705c121SKalle Valo 1055bab3cb92SEmmanuel Grumbach static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1056e705c121SKalle Valo { 1057e705c121SKalle Valo might_sleep(); 1058e705c121SKalle Valo 1059bab3cb92SEmmanuel Grumbach trans->ops->stop_device(trans); 1060e705c121SKalle Valo 1061e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1062e705c121SKalle Valo } 1063e705c121SKalle Valo 1064e5f3f215SHaim Dreyfuss static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 106523ae6128SMatti Gottlieb bool reset) 1066e705c121SKalle Valo { 1067e705c121SKalle Valo might_sleep(); 1068e5f3f215SHaim Dreyfuss if (!trans->ops->d3_suspend) 1069e5f3f215SHaim Dreyfuss return 0; 1070e5f3f215SHaim Dreyfuss 1071e5f3f215SHaim Dreyfuss return trans->ops->d3_suspend(trans, test, reset); 1072e705c121SKalle Valo } 1073e705c121SKalle Valo 1074e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1075e705c121SKalle Valo enum iwl_d3_status *status, 107623ae6128SMatti Gottlieb bool test, bool reset) 1077e705c121SKalle Valo { 1078e705c121SKalle Valo might_sleep(); 1079e705c121SKalle Valo if (!trans->ops->d3_resume) 1080e705c121SKalle Valo return 0; 1081e705c121SKalle Valo 108223ae6128SMatti Gottlieb return trans->ops->d3_resume(trans, status, test, reset); 1083e705c121SKalle Valo } 1084e705c121SKalle Valo 1085e705c121SKalle Valo static inline struct iwl_trans_dump_data * 108679f033f6SSara Sharon iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask) 1087e705c121SKalle Valo { 1088e705c121SKalle Valo if (!trans->ops->dump_data) 1089e705c121SKalle Valo return NULL; 109079f033f6SSara Sharon return trans->ops->dump_data(trans, dump_mask); 1091e705c121SKalle Valo } 1092e705c121SKalle Valo 1093a89c72ffSJohannes Berg static inline struct iwl_device_tx_cmd * 1094e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1095e705c121SKalle Valo { 1096a89c72ffSJohannes Berg return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1097e705c121SKalle Valo } 1098e705c121SKalle Valo 109992fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 110092fe8343SEmmanuel Grumbach 1101e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1102a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd) 1103e705c121SKalle Valo { 11041ea423b0SLuca Coelho kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1105e705c121SKalle Valo } 1106e705c121SKalle Valo 1107e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1108a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue) 1109e705c121SKalle Valo { 1110e705c121SKalle Valo if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1111e705c121SKalle Valo return -EIO; 1112e705c121SKalle Valo 1113e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1114e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1115e5d15cb5SEliad Peller return -EIO; 1116e5d15cb5SEliad Peller } 1117e705c121SKalle Valo 1118e705c121SKalle Valo return trans->ops->tx(trans, skb, dev_cmd, queue); 1119e705c121SKalle Valo } 1120e705c121SKalle Valo 1121e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1122e705c121SKalle Valo int ssn, struct sk_buff_head *skbs) 1123e705c121SKalle Valo { 1124e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1125e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1126e5d15cb5SEliad Peller return; 1127e5d15cb5SEliad Peller } 1128e705c121SKalle Valo 1129e705c121SKalle Valo trans->ops->reclaim(trans, queue, ssn, skbs); 1130e705c121SKalle Valo } 1131e705c121SKalle Valo 1132ba7136f3SAlex Malamud static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1133ba7136f3SAlex Malamud int ptr) 1134ba7136f3SAlex Malamud { 1135ba7136f3SAlex Malamud if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1136ba7136f3SAlex Malamud IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1137ba7136f3SAlex Malamud return; 1138ba7136f3SAlex Malamud } 1139ba7136f3SAlex Malamud 1140ba7136f3SAlex Malamud trans->ops->set_q_ptrs(trans, queue, ptr); 1141ba7136f3SAlex Malamud } 1142ba7136f3SAlex Malamud 1143e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1144e705c121SKalle Valo bool configure_scd) 1145e705c121SKalle Valo { 1146e705c121SKalle Valo trans->ops->txq_disable(trans, queue, configure_scd); 1147e705c121SKalle Valo } 1148e705c121SKalle Valo 1149dcfbd67bSEmmanuel Grumbach static inline bool 1150e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1151e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1152e705c121SKalle Valo unsigned int queue_wdg_timeout) 1153e705c121SKalle Valo { 1154e705c121SKalle Valo might_sleep(); 1155e705c121SKalle Valo 1156e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1157e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1158dcfbd67bSEmmanuel Grumbach return false; 1159e5d15cb5SEliad Peller } 1160e705c121SKalle Valo 1161dcfbd67bSEmmanuel Grumbach return trans->ops->txq_enable(trans, queue, ssn, 1162dcfbd67bSEmmanuel Grumbach cfg, queue_wdg_timeout); 1163e705c121SKalle Valo } 1164e705c121SKalle Valo 116592536c96SSara Sharon static inline int 116692536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 116792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 116892536c96SSara Sharon { 116992536c96SSara Sharon if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 117092536c96SSara Sharon return -ENOTSUPP; 117192536c96SSara Sharon 117292536c96SSara Sharon return trans->ops->rxq_dma_data(trans, queue, data); 117392536c96SSara Sharon } 117492536c96SSara Sharon 11756b35ff91SSara Sharon static inline void 11766b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue) 11776b35ff91SSara Sharon { 11786b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_free)) 11796b35ff91SSara Sharon return; 11806b35ff91SSara Sharon 11816b35ff91SSara Sharon trans->ops->txq_free(trans, queue); 11826b35ff91SSara Sharon } 11836b35ff91SSara Sharon 11846b35ff91SSara Sharon static inline int 11856b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans, 11861169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 11875369774cSSara Sharon int cmd_id, int size, 11885369774cSSara Sharon unsigned int wdg_timeout) 11896b35ff91SSara Sharon { 11906b35ff91SSara Sharon might_sleep(); 11916b35ff91SSara Sharon 11926b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 11936b35ff91SSara Sharon return -ENOTSUPP; 11946b35ff91SSara Sharon 11956b35ff91SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 11966b35ff91SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 11976b35ff91SSara Sharon return -EIO; 11986b35ff91SSara Sharon } 11996b35ff91SSara Sharon 12001169310fSGolan Ben Ami return trans->ops->txq_alloc(trans, flags, sta_id, tid, 12011169310fSGolan Ben Ami cmd_id, size, wdg_timeout); 12026b35ff91SSara Sharon } 12036b35ff91SSara Sharon 120442db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 120542db09c1SLiad Kaufman int queue, bool shared_mode) 120642db09c1SLiad Kaufman { 120742db09c1SLiad Kaufman if (trans->ops->txq_set_shared_mode) 120842db09c1SLiad Kaufman trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 120942db09c1SLiad Kaufman } 121042db09c1SLiad Kaufman 1211e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1212e705c121SKalle Valo int fifo, int sta_id, int tid, 1213e705c121SKalle Valo int frame_limit, u16 ssn, 1214e705c121SKalle Valo unsigned int queue_wdg_timeout) 1215e705c121SKalle Valo { 1216e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1217e705c121SKalle Valo .fifo = fifo, 1218e705c121SKalle Valo .sta_id = sta_id, 1219e705c121SKalle Valo .tid = tid, 1220e705c121SKalle Valo .frame_limit = frame_limit, 1221e705c121SKalle Valo .aggregate = sta_id >= 0, 1222e705c121SKalle Valo }; 1223e705c121SKalle Valo 1224e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1225e705c121SKalle Valo } 1226e705c121SKalle Valo 1227e705c121SKalle Valo static inline 1228e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1229e705c121SKalle Valo unsigned int queue_wdg_timeout) 1230e705c121SKalle Valo { 1231e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1232e705c121SKalle Valo .fifo = fifo, 1233e705c121SKalle Valo .sta_id = -1, 1234e705c121SKalle Valo .tid = IWL_MAX_TID_COUNT, 1235e705c121SKalle Valo .frame_limit = IWL_FRAME_LIMIT, 1236e705c121SKalle Valo .aggregate = false, 1237e705c121SKalle Valo }; 1238e705c121SKalle Valo 1239e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1240e705c121SKalle Valo } 1241e705c121SKalle Valo 1242e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1243e705c121SKalle Valo unsigned long txqs, 1244e705c121SKalle Valo bool freeze) 1245e705c121SKalle Valo { 1246e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1247e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1248e5d15cb5SEliad Peller return; 1249e5d15cb5SEliad Peller } 1250e705c121SKalle Valo 1251e705c121SKalle Valo if (trans->ops->freeze_txq_timer) 1252e705c121SKalle Valo trans->ops->freeze_txq_timer(trans, txqs, freeze); 1253e705c121SKalle Valo } 1254e705c121SKalle Valo 12550cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 12560cd58eaaSEmmanuel Grumbach bool block) 12570cd58eaaSEmmanuel Grumbach { 1258e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 12590cd58eaaSEmmanuel Grumbach IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1260e5d15cb5SEliad Peller return; 1261e5d15cb5SEliad Peller } 12620cd58eaaSEmmanuel Grumbach 12630cd58eaaSEmmanuel Grumbach if (trans->ops->block_txq_ptrs) 12640cd58eaaSEmmanuel Grumbach trans->ops->block_txq_ptrs(trans, block); 12650cd58eaaSEmmanuel Grumbach } 12660cd58eaaSEmmanuel Grumbach 1267a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1268e705c121SKalle Valo u32 txqs) 1269e705c121SKalle Valo { 1270d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1271d6d517b7SSara Sharon return -ENOTSUPP; 1272d6d517b7SSara Sharon 12732b84e632SEmmanuel Grumbach /* No need to wait if the firmware is not alive */ 12742b84e632SEmmanuel Grumbach if (trans->state != IWL_TRANS_FW_ALIVE) { 1275e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1276e5d15cb5SEliad Peller return -EIO; 1277e5d15cb5SEliad Peller } 1278e705c121SKalle Valo 1279a1a57877SSara Sharon return trans->ops->wait_tx_queues_empty(trans, txqs); 1280e705c121SKalle Valo } 1281e705c121SKalle Valo 1282d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1283d6d517b7SSara Sharon { 1284d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1285d6d517b7SSara Sharon return -ENOTSUPP; 1286d6d517b7SSara Sharon 1287d6d517b7SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1288d6d517b7SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1289d6d517b7SSara Sharon return -EIO; 1290d6d517b7SSara Sharon } 1291d6d517b7SSara Sharon 1292d6d517b7SSara Sharon return trans->ops->wait_txq_empty(trans, queue); 1293d6d517b7SSara Sharon } 1294d6d517b7SSara Sharon 1295e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1296e705c121SKalle Valo { 1297e705c121SKalle Valo trans->ops->write8(trans, ofs, val); 1298e705c121SKalle Valo } 1299e705c121SKalle Valo 1300e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1301e705c121SKalle Valo { 1302e705c121SKalle Valo trans->ops->write32(trans, ofs, val); 1303e705c121SKalle Valo } 1304e705c121SKalle Valo 1305e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1306e705c121SKalle Valo { 1307e705c121SKalle Valo return trans->ops->read32(trans, ofs); 1308e705c121SKalle Valo } 1309e705c121SKalle Valo 1310e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1311e705c121SKalle Valo { 1312e705c121SKalle Valo return trans->ops->read_prph(trans, ofs); 1313e705c121SKalle Valo } 1314e705c121SKalle Valo 1315e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1316e705c121SKalle Valo u32 val) 1317e705c121SKalle Valo { 1318e705c121SKalle Valo return trans->ops->write_prph(trans, ofs, val); 1319e705c121SKalle Valo } 1320e705c121SKalle Valo 1321e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1322e705c121SKalle Valo void *buf, int dwords) 1323e705c121SKalle Valo { 1324e705c121SKalle Valo return trans->ops->read_mem(trans, addr, buf, dwords); 1325e705c121SKalle Valo } 1326e705c121SKalle Valo 1327e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1328e705c121SKalle Valo do { \ 1329e705c121SKalle Valo if (__builtin_constant_p(bufsize)) \ 1330e705c121SKalle Valo BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1331e705c121SKalle Valo iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1332e705c121SKalle Valo } while (0) 1333e705c121SKalle Valo 1334e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1335e705c121SKalle Valo { 1336e705c121SKalle Valo u32 value; 1337e705c121SKalle Valo 1338e705c121SKalle Valo if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1339e705c121SKalle Valo return 0xa5a5a5a5; 1340e705c121SKalle Valo 1341e705c121SKalle Valo return value; 1342e705c121SKalle Valo } 1343e705c121SKalle Valo 1344e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1345e705c121SKalle Valo const void *buf, int dwords) 1346e705c121SKalle Valo { 1347e705c121SKalle Valo return trans->ops->write_mem(trans, addr, buf, dwords); 1348e705c121SKalle Valo } 1349e705c121SKalle Valo 1350e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1351e705c121SKalle Valo u32 val) 1352e705c121SKalle Valo { 1353e705c121SKalle Valo return iwl_trans_write_mem(trans, addr, &val, 1); 1354e705c121SKalle Valo } 1355e705c121SKalle Valo 1356e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1357e705c121SKalle Valo { 1358e705c121SKalle Valo if (trans->ops->set_pmi) 1359e705c121SKalle Valo trans->ops->set_pmi(trans, state); 1360e705c121SKalle Valo } 1361e705c121SKalle Valo 1362870c2a11SGolan Ben Ami static inline void iwl_trans_sw_reset(struct iwl_trans *trans) 1363870c2a11SGolan Ben Ami { 1364870c2a11SGolan Ben Ami if (trans->ops->sw_reset) 1365870c2a11SGolan Ben Ami trans->ops->sw_reset(trans); 1366870c2a11SGolan Ben Ami } 1367870c2a11SGolan Ben Ami 1368e705c121SKalle Valo static inline void 1369e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1370e705c121SKalle Valo { 1371e705c121SKalle Valo trans->ops->set_bits_mask(trans, reg, mask, value); 1372e705c121SKalle Valo } 1373e705c121SKalle Valo 13741ed08f6fSJohannes Berg #define iwl_trans_grab_nic_access(trans) \ 1375e705c121SKalle Valo __cond_lock(nic_access, \ 13761ed08f6fSJohannes Berg likely((trans)->ops->grab_nic_access(trans))) 1377e705c121SKalle Valo 1378e705c121SKalle Valo static inline void __releases(nic_access) 13791ed08f6fSJohannes Berg iwl_trans_release_nic_access(struct iwl_trans *trans) 1380e705c121SKalle Valo { 13811ed08f6fSJohannes Berg trans->ops->release_nic_access(trans); 1382e705c121SKalle Valo __release(nic_access); 1383e705c121SKalle Valo } 1384e705c121SKalle Valo 1385e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans) 1386e705c121SKalle Valo { 1387e705c121SKalle Valo if (WARN_ON_ONCE(!trans->op_mode)) 1388e705c121SKalle Valo return; 1389e705c121SKalle Valo 1390e705c121SKalle Valo /* prevent double restarts due to the same erroneous FW */ 1391152fdc0fSJohannes Berg if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1392e705c121SKalle Valo iwl_op_mode_nic_error(trans->op_mode); 1393152fdc0fSJohannes Berg trans->state = IWL_TRANS_NO_FW; 1394152fdc0fSJohannes Berg } 1395e705c121SKalle Valo } 1396e705c121SKalle Valo 1397068893b7SShahar S Matityahu static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1398068893b7SShahar S Matityahu { 1399068893b7SShahar S Matityahu return trans->state == IWL_TRANS_FW_ALIVE; 1400068893b7SShahar S Matityahu } 1401068893b7SShahar S Matityahu 1402d1967ce6SShahar S Matityahu static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1403d1967ce6SShahar S Matityahu { 1404d1967ce6SShahar S Matityahu if (trans->ops->sync_nmi) 1405d1967ce6SShahar S Matityahu trans->ops->sync_nmi(trans); 1406d1967ce6SShahar S Matityahu } 1407d1967ce6SShahar S Matityahu 14083161a34dSMordechay Goodstein void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 14093161a34dSMordechay Goodstein u32 sw_err_bit); 14103161a34dSMordechay Goodstein 1411a182dfabSLuca Coelho static inline int iwl_trans_set_pnvm(struct iwl_trans *trans, 1412a182dfabSLuca Coelho const void *data, u32 len) 1413a182dfabSLuca Coelho { 141469725928SLuca Coelho if (trans->ops->set_pnvm) { 141569725928SLuca Coelho int ret = trans->ops->set_pnvm(trans, data, len); 141669725928SLuca Coelho 141769725928SLuca Coelho if (ret) 141869725928SLuca Coelho return ret; 141969725928SLuca Coelho } 142069725928SLuca Coelho 142169725928SLuca Coelho trans->pnvm_loaded = true; 1422a182dfabSLuca Coelho 1423a182dfabSLuca Coelho return 0; 1424a182dfabSLuca Coelho } 1425a182dfabSLuca Coelho 1426*9dad325fSLuca Coelho static inline int iwl_trans_set_reduce_power(struct iwl_trans *trans, 1427*9dad325fSLuca Coelho const void *data, u32 len) 1428*9dad325fSLuca Coelho { 1429*9dad325fSLuca Coelho if (trans->ops->set_reduce_power) { 1430*9dad325fSLuca Coelho int ret = trans->ops->set_reduce_power(trans, data, len); 1431*9dad325fSLuca Coelho 1432*9dad325fSLuca Coelho if (ret) 1433*9dad325fSLuca Coelho return ret; 1434*9dad325fSLuca Coelho } 1435*9dad325fSLuca Coelho 1436*9dad325fSLuca Coelho trans->reduce_power_loaded = true; 1437*9dad325fSLuca Coelho return 0; 1438*9dad325fSLuca Coelho } 1439*9dad325fSLuca Coelho 1440a1af4c48SShahar S Matityahu static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1441a1af4c48SShahar S Matityahu { 1442341bd290SShahar S Matityahu return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1443341bd290SShahar S Matityahu trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1444a1af4c48SShahar S Matityahu } 1445a1af4c48SShahar S Matityahu 14463161a34dSMordechay Goodstein static inline void iwl_trans_interrupts(struct iwl_trans *trans, bool enable) 14473161a34dSMordechay Goodstein { 14483161a34dSMordechay Goodstein if (trans->ops->interrupts) 14493161a34dSMordechay Goodstein trans->ops->interrupts(trans, enable); 14503161a34dSMordechay Goodstein } 14513161a34dSMordechay Goodstein 1452e705c121SKalle Valo /***************************************************** 1453e705c121SKalle Valo * transport helper functions 1454e705c121SKalle Valo *****************************************************/ 1455e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1456e705c121SKalle Valo struct device *dev, 1457a89c72ffSJohannes Berg const struct iwl_trans_ops *ops, 1458fda1bd0dSMordechay Goodstein const struct iwl_cfg_trans_params *cfg_trans); 1459d12455fdSJohannes Berg int iwl_trans_init(struct iwl_trans *trans); 1460e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans); 1461e705c121SKalle Valo 1462e705c121SKalle Valo /***************************************************** 1463e705c121SKalle Valo * driver (transport) register/unregister functions 1464e705c121SKalle Valo ******************************************************/ 1465e705c121SKalle Valo int __must_check iwl_pci_register_driver(void); 1466e705c121SKalle Valo void iwl_pci_unregister_driver(void); 1467e705c121SKalle Valo 1468e705c121SKalle Valo #endif /* __iwl_trans_h__ */ 1469