1e705c121SKalle Valo /******************************************************************************
2e705c121SKalle Valo  *
3e705c121SKalle Valo  * This file is provided under a dual BSD/GPLv2 license.  When using or
4e705c121SKalle Valo  * redistributing this file, you may do so under either license.
5e705c121SKalle Valo  *
6e705c121SKalle Valo  * GPL LICENSE SUMMARY
7e705c121SKalle Valo  *
8e705c121SKalle Valo  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
106b35ff91SSara Sharon  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11e705c121SKalle Valo  *
12e705c121SKalle Valo  * This program is free software; you can redistribute it and/or modify
13e705c121SKalle Valo  * it under the terms of version 2 of the GNU General Public License as
14e705c121SKalle Valo  * published by the Free Software Foundation.
15e705c121SKalle Valo  *
16e705c121SKalle Valo  * This program is distributed in the hope that it will be useful, but
17e705c121SKalle Valo  * WITHOUT ANY WARRANTY; without even the implied warranty of
18e705c121SKalle Valo  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19e705c121SKalle Valo  * General Public License for more details.
20e705c121SKalle Valo  *
21e705c121SKalle Valo  * The full GNU General Public License is included in this distribution
22e705c121SKalle Valo  * in the file called COPYING.
23e705c121SKalle Valo  *
24e705c121SKalle Valo  * Contact Information:
25cb2f8277SEmmanuel Grumbach  *  Intel Linux Wireless <linuxwifi@intel.com>
26e705c121SKalle Valo  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27e705c121SKalle Valo  *
28e705c121SKalle Valo  * BSD LICENSE
29e705c121SKalle Valo  *
30e705c121SKalle Valo  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31e705c121SKalle Valo  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
326b35ff91SSara Sharon  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
33e705c121SKalle Valo  * All rights reserved.
34e705c121SKalle Valo  *
35e705c121SKalle Valo  * Redistribution and use in source and binary forms, with or without
36e705c121SKalle Valo  * modification, are permitted provided that the following conditions
37e705c121SKalle Valo  * are met:
38e705c121SKalle Valo  *
39e705c121SKalle Valo  *  * Redistributions of source code must retain the above copyright
40e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer.
41e705c121SKalle Valo  *  * Redistributions in binary form must reproduce the above copyright
42e705c121SKalle Valo  *    notice, this list of conditions and the following disclaimer in
43e705c121SKalle Valo  *    the documentation and/or other materials provided with the
44e705c121SKalle Valo  *    distribution.
45e705c121SKalle Valo  *  * Neither the name Intel Corporation nor the names of its
46e705c121SKalle Valo  *    contributors may be used to endorse or promote products derived
47e705c121SKalle Valo  *    from this software without specific prior written permission.
48e705c121SKalle Valo  *
49e705c121SKalle Valo  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50e705c121SKalle Valo  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51e705c121SKalle Valo  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52e705c121SKalle Valo  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53e705c121SKalle Valo  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54e705c121SKalle Valo  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55e705c121SKalle Valo  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56e705c121SKalle Valo  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57e705c121SKalle Valo  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58e705c121SKalle Valo  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59e705c121SKalle Valo  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60e705c121SKalle Valo  *
61e705c121SKalle Valo  *****************************************************************************/
62e705c121SKalle Valo #ifndef __iwl_trans_h__
63e705c121SKalle Valo #define __iwl_trans_h__
64e705c121SKalle Valo 
65e705c121SKalle Valo #include <linux/ieee80211.h>
66e705c121SKalle Valo #include <linux/mm.h> /* for page_address */
67e705c121SKalle Valo #include <linux/lockdep.h>
6839bdb17eSSharon Dvir #include <linux/kernel.h>
69e705c121SKalle Valo 
70e705c121SKalle Valo #include "iwl-debug.h"
71e705c121SKalle Valo #include "iwl-config.h"
72d962f9b1SJohannes Berg #include "fw/img.h"
73e705c121SKalle Valo #include "iwl-op-mode.h"
74d172a5efSJohannes Berg #include "fw/api/cmdhdr.h"
75d172a5efSJohannes Berg #include "fw/api/txq.h"
76e705c121SKalle Valo 
77e705c121SKalle Valo /**
78e705c121SKalle Valo  * DOC: Transport layer - what is it ?
79e705c121SKalle Valo  *
80e705c121SKalle Valo  * The transport layer is the layer that deals with the HW directly. It provides
81e705c121SKalle Valo  * an abstraction of the underlying HW to the upper layer. The transport layer
82e705c121SKalle Valo  * doesn't provide any policy, algorithm or anything of this kind, but only
83e705c121SKalle Valo  * mechanisms to make the HW do something. It is not completely stateless but
84e705c121SKalle Valo  * close to it.
85e705c121SKalle Valo  * We will have an implementation for each different supported bus.
86e705c121SKalle Valo  */
87e705c121SKalle Valo 
88e705c121SKalle Valo /**
89e705c121SKalle Valo  * DOC: Life cycle of the transport layer
90e705c121SKalle Valo  *
91e705c121SKalle Valo  * The transport layer has a very precise life cycle.
92e705c121SKalle Valo  *
93e705c121SKalle Valo  *	1) A helper function is called during the module initialization and
94e705c121SKalle Valo  *	   registers the bus driver's ops with the transport's alloc function.
95e705c121SKalle Valo  *	2) Bus's probe calls to the transport layer's allocation functions.
96e705c121SKalle Valo  *	   Of course this function is bus specific.
97e705c121SKalle Valo  *	3) This allocation functions will spawn the upper layer which will
98e705c121SKalle Valo  *	   register mac80211.
99e705c121SKalle Valo  *
100e705c121SKalle Valo  *	4) At some point (i.e. mac80211's start call), the op_mode will call
101e705c121SKalle Valo  *	   the following sequence:
102e705c121SKalle Valo  *	   start_hw
103e705c121SKalle Valo  *	   start_fw
104e705c121SKalle Valo  *
105e705c121SKalle Valo  *	5) Then when finished (or reset):
106e705c121SKalle Valo  *	   stop_device
107e705c121SKalle Valo  *
108e705c121SKalle Valo  *	6) Eventually, the free function will be called.
109e705c121SKalle Valo  */
110e705c121SKalle Valo 
111e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK		0x00003FFF	/* bits 0-13 */
112e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID		0x55550000
113e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN		0x40
114fbe41127SSara Sharon #define FH_RSCSR_RPA_EN			BIT(25)
1159d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN		BIT(26)
116ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS		16
117ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK		0x3F0000
118e705c121SKalle Valo 
119e705c121SKalle Valo struct iwl_rx_packet {
120e705c121SKalle Valo 	/*
121e705c121SKalle Valo 	 * The first 4 bytes of the RX frame header contain both the RX frame
122e705c121SKalle Valo 	 * size and some flags.
123e705c121SKalle Valo 	 * Bit fields:
124e705c121SKalle Valo 	 * 31:    flag flush RB request
125e705c121SKalle Valo 	 * 30:    flag ignore TC (terminal counter) request
126e705c121SKalle Valo 	 * 29:    flag fast IRQ request
1279d0fc5a5SDavid Spinadel 	 * 28-27: Reserved
1289d0fc5a5SDavid Spinadel 	 * 26:    RADA enabled
129fbe41127SSara Sharon 	 * 25:    Offload enabled
130ab2e696bSSara Sharon 	 * 24:    RPF enabled
131ab2e696bSSara Sharon 	 * 23:    RSS enabled
132ab2e696bSSara Sharon 	 * 22:    Checksum enabled
133ab2e696bSSara Sharon 	 * 21-16: RX queue
134ab2e696bSSara Sharon 	 * 15-14: Reserved
135e705c121SKalle Valo 	 * 13-00: RX frame size
136e705c121SKalle Valo 	 */
137e705c121SKalle Valo 	__le32 len_n_flags;
138e705c121SKalle Valo 	struct iwl_cmd_header hdr;
139e705c121SKalle Valo 	u8 data[];
140e705c121SKalle Valo } __packed;
141e705c121SKalle Valo 
142e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)
143e705c121SKalle Valo {
144e705c121SKalle Valo 	return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
145e705c121SKalle Valo }
146e705c121SKalle Valo 
147e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)
148e705c121SKalle Valo {
149e705c121SKalle Valo 	return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);
150e705c121SKalle Valo }
151e705c121SKalle Valo 
152e705c121SKalle Valo /**
153e705c121SKalle Valo  * enum CMD_MODE - how to send the host commands ?
154e705c121SKalle Valo  *
155e705c121SKalle Valo  * @CMD_ASYNC: Return right away and don't wait for the response
156e705c121SKalle Valo  * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of
157e705c121SKalle Valo  *	the response. The caller needs to call iwl_free_resp when done.
158e705c121SKalle Valo  * @CMD_HIGH_PRIO: The command is high priority - it goes to the front of the
159e705c121SKalle Valo  *	command queue, but after other high priority commands. Valid only
160e705c121SKalle Valo  *	with CMD_ASYNC.
161e705c121SKalle Valo  * @CMD_SEND_IN_IDLE: The command should be sent even when the trans is idle.
162e705c121SKalle Valo  * @CMD_MAKE_TRANS_IDLE: The command response should mark the trans as idle.
163e705c121SKalle Valo  * @CMD_WAKE_UP_TRANS: The command response should wake up the trans
164e705c121SKalle Valo  *	(i.e. mark it as non-idle).
165dcbb4746SEmmanuel Grumbach  * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be
166dcbb4746SEmmanuel Grumbach  *	called after this command completes. Valid only with CMD_ASYNC.
167e705c121SKalle Valo  */
168e705c121SKalle Valo enum CMD_MODE {
169e705c121SKalle Valo 	CMD_ASYNC		= BIT(0),
170e705c121SKalle Valo 	CMD_WANT_SKB		= BIT(1),
171e705c121SKalle Valo 	CMD_SEND_IN_RFKILL	= BIT(2),
172e705c121SKalle Valo 	CMD_HIGH_PRIO		= BIT(3),
173e705c121SKalle Valo 	CMD_SEND_IN_IDLE	= BIT(4),
174e705c121SKalle Valo 	CMD_MAKE_TRANS_IDLE	= BIT(5),
175e705c121SKalle Valo 	CMD_WAKE_UP_TRANS	= BIT(6),
176dcbb4746SEmmanuel Grumbach 	CMD_WANT_ASYNC_CALLBACK	= BIT(7),
177e705c121SKalle Valo };
178e705c121SKalle Valo 
179e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320
180e705c121SKalle Valo 
181e705c121SKalle Valo /**
182e705c121SKalle Valo  * struct iwl_device_cmd
183e705c121SKalle Valo  *
184e705c121SKalle Valo  * For allocation of the command and tx queues, this establishes the overall
185e705c121SKalle Valo  * size of the largest command we send to uCode, except for commands that
186e705c121SKalle Valo  * aren't fully copied and use other TFD space.
187e705c121SKalle Valo  */
188e705c121SKalle Valo struct iwl_device_cmd {
189e705c121SKalle Valo 	union {
190e705c121SKalle Valo 		struct {
191e705c121SKalle Valo 			struct iwl_cmd_header hdr;	/* uCode API */
192e705c121SKalle Valo 			u8 payload[DEF_CMD_PAYLOAD_SIZE];
193e705c121SKalle Valo 		};
194e705c121SKalle Valo 		struct {
195e705c121SKalle Valo 			struct iwl_cmd_header_wide hdr_wide;
196e705c121SKalle Valo 			u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -
197e705c121SKalle Valo 					sizeof(struct iwl_cmd_header_wide) +
198e705c121SKalle Valo 					sizeof(struct iwl_cmd_header)];
199e705c121SKalle Valo 		};
200e705c121SKalle Valo 	};
201e705c121SKalle Valo } __packed;
202e705c121SKalle Valo 
203e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
204e705c121SKalle Valo 
205e705c121SKalle Valo /*
206e705c121SKalle Valo  * number of transfer buffers (fragments) per transmit frame descriptor;
207e705c121SKalle Valo  * this is just the driver's idea, the hardware supports 20
208e705c121SKalle Valo  */
209e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD	2
210e705c121SKalle Valo 
211e705c121SKalle Valo /**
212b8aed81cSJohannes Berg  * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command
213e705c121SKalle Valo  *
214e705c121SKalle Valo  * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's
215e705c121SKalle Valo  *	ring. The transport layer doesn't map the command's buffer to DMA, but
216e705c121SKalle Valo  *	rather copies it to a previously allocated DMA buffer. This flag tells
217e705c121SKalle Valo  *	the transport layer not to copy the command, but to map the existing
218e705c121SKalle Valo  *	buffer (that is passed in) instead. This saves the memcpy and allows
219e705c121SKalle Valo  *	commands that are bigger than the fixed buffer to be submitted.
220e705c121SKalle Valo  *	Note that a TFD entry after a NOCOPY one cannot be a normal copied one.
221e705c121SKalle Valo  * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this
222e705c121SKalle Valo  *	chunk internally and free it again after the command completes. This
223e705c121SKalle Valo  *	can (currently) be used only once per command.
224e705c121SKalle Valo  *	Note that a TFD entry after a DUP one cannot be a normal copied one.
225e705c121SKalle Valo  */
226e705c121SKalle Valo enum iwl_hcmd_dataflag {
227e705c121SKalle Valo 	IWL_HCMD_DFL_NOCOPY	= BIT(0),
228e705c121SKalle Valo 	IWL_HCMD_DFL_DUP	= BIT(1),
229e705c121SKalle Valo };
230e705c121SKalle Valo 
231e705c121SKalle Valo /**
232e705c121SKalle Valo  * struct iwl_host_cmd - Host command to the uCode
233e705c121SKalle Valo  *
234e705c121SKalle Valo  * @data: array of chunks that composes the data of the host command
235e705c121SKalle Valo  * @resp_pkt: response packet, if %CMD_WANT_SKB was set
236e705c121SKalle Valo  * @_rx_page_order: (internally used to free response packet)
237e705c121SKalle Valo  * @_rx_page_addr: (internally used to free response packet)
238e705c121SKalle Valo  * @flags: can be CMD_*
239e705c121SKalle Valo  * @len: array of the lengths of the chunks in data
240e705c121SKalle Valo  * @dataflags: IWL_HCMD_DFL_*
241e705c121SKalle Valo  * @id: command id of the host command, for wide commands encoding the
242e705c121SKalle Valo  *	version and group as well
243e705c121SKalle Valo  */
244e705c121SKalle Valo struct iwl_host_cmd {
245e705c121SKalle Valo 	const void *data[IWL_MAX_CMD_TBS_PER_TFD];
246e705c121SKalle Valo 	struct iwl_rx_packet *resp_pkt;
247e705c121SKalle Valo 	unsigned long _rx_page_addr;
248e705c121SKalle Valo 	u32 _rx_page_order;
249e705c121SKalle Valo 
250e705c121SKalle Valo 	u32 flags;
251e705c121SKalle Valo 	u32 id;
252e705c121SKalle Valo 	u16 len[IWL_MAX_CMD_TBS_PER_TFD];
253e705c121SKalle Valo 	u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];
254e705c121SKalle Valo };
255e705c121SKalle Valo 
256e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd)
257e705c121SKalle Valo {
258e705c121SKalle Valo 	free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);
259e705c121SKalle Valo }
260e705c121SKalle Valo 
261e705c121SKalle Valo struct iwl_rx_cmd_buffer {
262e705c121SKalle Valo 	struct page *_page;
263e705c121SKalle Valo 	int _offset;
264e705c121SKalle Valo 	bool _page_stolen;
265e705c121SKalle Valo 	u32 _rx_page_order;
266e705c121SKalle Valo 	unsigned int truesize;
2677891965dSSara Sharon 	u8 status;
268e705c121SKalle Valo };
269e705c121SKalle Valo 
270e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)
271e705c121SKalle Valo {
272e705c121SKalle Valo 	return (void *)((unsigned long)page_address(r->_page) + r->_offset);
273e705c121SKalle Valo }
274e705c121SKalle Valo 
275e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)
276e705c121SKalle Valo {
277e705c121SKalle Valo 	return r->_offset;
278e705c121SKalle Valo }
279e705c121SKalle Valo 
280e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)
281e705c121SKalle Valo {
282e705c121SKalle Valo 	r->_page_stolen = true;
283e705c121SKalle Valo 	get_page(r->_page);
284e705c121SKalle Valo 	return r->_page;
285e705c121SKalle Valo }
286e705c121SKalle Valo 
287e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)
288e705c121SKalle Valo {
289e705c121SKalle Valo 	__free_pages(r->_page, r->_rx_page_order);
290e705c121SKalle Valo }
291e705c121SKalle Valo 
292e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS	6
293e705c121SKalle Valo 
294e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
295e705c121SKalle Valo 
296e705c121SKalle Valo /*
297e705c121SKalle Valo  * Maximum number of HW queues the transport layer
298e705c121SKalle Valo  * currently supports
299e705c121SKalle Valo  */
300e705c121SKalle Valo #define IWL_MAX_HW_QUEUES		32
301e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES		512
302e982bc2cSSara Sharon 
303e705c121SKalle Valo #define IWL_MAX_TID_COUNT	8
304c65f4e03SSara Sharon #define IWL_MGMT_TID		15
305e705c121SKalle Valo #define IWL_FRAME_LIMIT	64
306e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES	16
307e705c121SKalle Valo 
308e705c121SKalle Valo /**
309e705c121SKalle Valo  * enum iwl_wowlan_status - WoWLAN image/device status
310e705c121SKalle Valo  * @IWL_D3_STATUS_ALIVE: firmware is still running after resume
311e705c121SKalle Valo  * @IWL_D3_STATUS_RESET: device was reset while suspended
312e705c121SKalle Valo  */
313e705c121SKalle Valo enum iwl_d3_status {
314e705c121SKalle Valo 	IWL_D3_STATUS_ALIVE,
315e705c121SKalle Valo 	IWL_D3_STATUS_RESET,
316e705c121SKalle Valo };
317e705c121SKalle Valo 
318e705c121SKalle Valo /**
319e705c121SKalle Valo  * enum iwl_trans_status: transport status flags
320e705c121SKalle Valo  * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed
321e705c121SKalle Valo  * @STATUS_DEVICE_ENABLED: APM is enabled
322e705c121SKalle Valo  * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)
323e705c121SKalle Valo  * @STATUS_INT_ENABLED: interrupts are enabled
324326477e4SJohannes Berg  * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch
325326477e4SJohannes Berg  * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode
326e705c121SKalle Valo  * @STATUS_FW_ERROR: the fw is in error state
327e705c121SKalle Valo  * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands
328e705c121SKalle Valo  *	are sent
329e705c121SKalle Valo  * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent
330e705c121SKalle Valo  * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation
331e705c121SKalle Valo  */
332e705c121SKalle Valo enum iwl_trans_status {
333e705c121SKalle Valo 	STATUS_SYNC_HCMD_ACTIVE,
334e705c121SKalle Valo 	STATUS_DEVICE_ENABLED,
335e705c121SKalle Valo 	STATUS_TPOWER_PMI,
336e705c121SKalle Valo 	STATUS_INT_ENABLED,
337326477e4SJohannes Berg 	STATUS_RFKILL_HW,
338326477e4SJohannes Berg 	STATUS_RFKILL_OPMODE,
339e705c121SKalle Valo 	STATUS_FW_ERROR,
340e705c121SKalle Valo 	STATUS_TRANS_GOING_IDLE,
341e705c121SKalle Valo 	STATUS_TRANS_IDLE,
342e705c121SKalle Valo 	STATUS_TRANS_DEAD,
343e705c121SKalle Valo };
344e705c121SKalle Valo 
3456c4fbcbcSEmmanuel Grumbach static inline int
3466c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)
3476c4fbcbcSEmmanuel Grumbach {
3486c4fbcbcSEmmanuel Grumbach 	switch (rb_size) {
3491a4968d1SGolan Ben Ami 	case IWL_AMSDU_2K:
3501a4968d1SGolan Ben Ami 		return get_order(2 * 1024);
3516c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_4K:
3526c4fbcbcSEmmanuel Grumbach 		return get_order(4 * 1024);
3536c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_8K:
3546c4fbcbcSEmmanuel Grumbach 		return get_order(8 * 1024);
3556c4fbcbcSEmmanuel Grumbach 	case IWL_AMSDU_12K:
3566c4fbcbcSEmmanuel Grumbach 		return get_order(12 * 1024);
3576c4fbcbcSEmmanuel Grumbach 	default:
3586c4fbcbcSEmmanuel Grumbach 		WARN_ON(1);
3596c4fbcbcSEmmanuel Grumbach 		return -1;
3606c4fbcbcSEmmanuel Grumbach 	}
3616c4fbcbcSEmmanuel Grumbach }
3626c4fbcbcSEmmanuel Grumbach 
36339bdb17eSSharon Dvir struct iwl_hcmd_names {
36439bdb17eSSharon Dvir 	u8 cmd_id;
36539bdb17eSSharon Dvir 	const char *const cmd_name;
36639bdb17eSSharon Dvir };
36739bdb17eSSharon Dvir 
36839bdb17eSSharon Dvir #define HCMD_NAME(x)	\
36939bdb17eSSharon Dvir 	{ .cmd_id = x, .cmd_name = #x }
37039bdb17eSSharon Dvir 
37139bdb17eSSharon Dvir struct iwl_hcmd_arr {
37239bdb17eSSharon Dvir 	const struct iwl_hcmd_names *arr;
37339bdb17eSSharon Dvir 	int size;
37439bdb17eSSharon Dvir };
37539bdb17eSSharon Dvir 
37639bdb17eSSharon Dvir #define HCMD_ARR(x)	\
37739bdb17eSSharon Dvir 	{ .arr = x, .size = ARRAY_SIZE(x) }
37839bdb17eSSharon Dvir 
379e705c121SKalle Valo /**
380e705c121SKalle Valo  * struct iwl_trans_config - transport configuration
381e705c121SKalle Valo  *
382e705c121SKalle Valo  * @op_mode: pointer to the upper layer.
383e705c121SKalle Valo  * @cmd_queue: the index of the command queue.
384e705c121SKalle Valo  *	Must be set before start_fw.
385e705c121SKalle Valo  * @cmd_fifo: the fifo for host commands
386e705c121SKalle Valo  * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue.
387e705c121SKalle Valo  * @no_reclaim_cmds: Some devices erroneously don't set the
388e705c121SKalle Valo  *	SEQ_RX_FRAME bit on some notifications, this is the
389e705c121SKalle Valo  *	list of such notifications to filter. Max length is
390e705c121SKalle Valo  *	%MAX_NO_RECLAIM_CMDS.
391e705c121SKalle Valo  * @n_no_reclaim_cmds: # of commands in list
3926c4fbcbcSEmmanuel Grumbach  * @rx_buf_size: RX buffer size needed for A-MSDUs
393e705c121SKalle Valo  *	if unset 4k will be the RX buffer size
394e705c121SKalle Valo  * @bc_table_dword: set to true if the BC table expects the byte count to be
395e705c121SKalle Valo  *	in DWORD (as opposed to bytes)
396e705c121SKalle Valo  * @scd_set_active: should the transport configure the SCD for HCMD queue
39741837ca9SEmmanuel Grumbach  * @sw_csum_tx: transport should compute the TCP checksum
39839bdb17eSSharon Dvir  * @command_groups: array of command groups, each member is an array of the
39939bdb17eSSharon Dvir  *	commands in the group; for debugging only
40039bdb17eSSharon Dvir  * @command_groups_size: number of command groups, to avoid illegal access
40121cb3222SJohannes Berg  * @cb_data_offs: offset inside skb->cb to store transport data at, must have
40221cb3222SJohannes Berg  *	space for at least two pointers
403e705c121SKalle Valo  */
404e705c121SKalle Valo struct iwl_trans_config {
405e705c121SKalle Valo 	struct iwl_op_mode *op_mode;
406e705c121SKalle Valo 
407e705c121SKalle Valo 	u8 cmd_queue;
408e705c121SKalle Valo 	u8 cmd_fifo;
409e705c121SKalle Valo 	unsigned int cmd_q_wdg_timeout;
410e705c121SKalle Valo 	const u8 *no_reclaim_cmds;
411e705c121SKalle Valo 	unsigned int n_no_reclaim_cmds;
412e705c121SKalle Valo 
4136c4fbcbcSEmmanuel Grumbach 	enum iwl_amsdu_size rx_buf_size;
414e705c121SKalle Valo 	bool bc_table_dword;
415e705c121SKalle Valo 	bool scd_set_active;
41641837ca9SEmmanuel Grumbach 	bool sw_csum_tx;
41739bdb17eSSharon Dvir 	const struct iwl_hcmd_arr *command_groups;
41839bdb17eSSharon Dvir 	int command_groups_size;
419e705c121SKalle Valo 
42021cb3222SJohannes Berg 	u8 cb_data_offs;
421e705c121SKalle Valo };
422e705c121SKalle Valo 
423e705c121SKalle Valo struct iwl_trans_dump_data {
424e705c121SKalle Valo 	u32 len;
425e705c121SKalle Valo 	u8 data[];
426e705c121SKalle Valo };
427e705c121SKalle Valo 
428e705c121SKalle Valo struct iwl_trans;
429e705c121SKalle Valo 
430e705c121SKalle Valo struct iwl_trans_txq_scd_cfg {
431e705c121SKalle Valo 	u8 fifo;
4322a2e9d10SLiad Kaufman 	u8 sta_id;
433e705c121SKalle Valo 	u8 tid;
434e705c121SKalle Valo 	bool aggregate;
435e705c121SKalle Valo 	int frame_limit;
436e705c121SKalle Valo };
437e705c121SKalle Valo 
4386b35ff91SSara Sharon /**
43992536c96SSara Sharon  * struct iwl_trans_rxq_dma_data - RX queue DMA data
44092536c96SSara Sharon  * @fr_bd_cb: DMA address of free BD cyclic buffer
44192536c96SSara Sharon  * @fr_bd_wid: Initial write index of the free BD cyclic buffer
44292536c96SSara Sharon  * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
44392536c96SSara Sharon  * @ur_bd_cb: DMA address of used BD cyclic buffer
44492536c96SSara Sharon  */
44592536c96SSara Sharon struct iwl_trans_rxq_dma_data {
44692536c96SSara Sharon 	u64 fr_bd_cb;
44792536c96SSara Sharon 	u32 fr_bd_wid;
44892536c96SSara Sharon 	u64 urbd_stts_wrptr;
44992536c96SSara Sharon 	u64 ur_bd_cb;
45092536c96SSara Sharon };
45192536c96SSara Sharon 
45292536c96SSara Sharon /**
453e705c121SKalle Valo  * struct iwl_trans_ops - transport specific operations
454e705c121SKalle Valo  *
455e705c121SKalle Valo  * All the handlers MUST be implemented
456e705c121SKalle Valo  *
457e705c121SKalle Valo  * @start_hw: starts the HW. If low_power is true, the NIC needs to be taken
458e705c121SKalle Valo  *	out of a low power state. From that point on, the HW can send
459e705c121SKalle Valo  *	interrupts. May sleep.
460e705c121SKalle Valo  * @op_mode_leave: Turn off the HW RF kill indication if on
461e705c121SKalle Valo  *	May sleep
462e705c121SKalle Valo  * @start_fw: allocates and inits all the resources for the transport
463e705c121SKalle Valo  *	layer. Also kick a fw image.
464e705c121SKalle Valo  *	May sleep
465e705c121SKalle Valo  * @fw_alive: called when the fw sends alive notification. If the fw provides
466e705c121SKalle Valo  *	the SCD base address in SRAM, then provide it here, or 0 otherwise.
467e705c121SKalle Valo  *	May sleep
468e705c121SKalle Valo  * @stop_device: stops the whole device (embedded CPU put to reset) and stops
469e705c121SKalle Valo  *	the HW. If low_power is true, the NIC will be put in low power state.
470e705c121SKalle Valo  *	From that point on, the HW will be stopped but will still issue an
471e705c121SKalle Valo  *	interrupt if the HW RF kill switch is triggered.
472e705c121SKalle Valo  *	This callback must do the right thing and not crash even if %start_hw()
473e705c121SKalle Valo  *	was called but not &start_fw(). May sleep.
474e705c121SKalle Valo  * @d3_suspend: put the device into the correct mode for WoWLAN during
475e705c121SKalle Valo  *	suspend. This is optional, if not implemented WoWLAN will not be
476e705c121SKalle Valo  *	supported. This callback may sleep.
477e705c121SKalle Valo  * @d3_resume: resume the device after WoWLAN, enabling the opmode to
478e705c121SKalle Valo  *	talk to the WoWLAN image to get its status. This is optional, if not
479e705c121SKalle Valo  *	implemented WoWLAN will not be supported. This callback may sleep.
480e705c121SKalle Valo  * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted.
481e705c121SKalle Valo  *	If RFkill is asserted in the middle of a SYNC host command, it must
482e705c121SKalle Valo  *	return -ERFKILL straight away.
483e705c121SKalle Valo  *	May sleep only if CMD_ASYNC is not set
4843f73b8caSEmmanuel Grumbach  * @tx: send an skb. The transport relies on the op_mode to zero the
4856eb5e529SEmmanuel Grumbach  *	the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all
4866eb5e529SEmmanuel Grumbach  *	the CSUM will be taken care of (TCP CSUM and IP header in case of
4876eb5e529SEmmanuel Grumbach  *	IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP
4886eb5e529SEmmanuel Grumbach  *	header if it is IPv4.
489e705c121SKalle Valo  *	Must be atomic
490e705c121SKalle Valo  * @reclaim: free packet until ssn. Returns a list of freed packets.
491e705c121SKalle Valo  *	Must be atomic
492e705c121SKalle Valo  * @txq_enable: setup a queue. To setup an AC queue, use the
493e705c121SKalle Valo  *	iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before
494e705c121SKalle Valo  *	this one. The op_mode must not configure the HCMD queue. The scheduler
495e705c121SKalle Valo  *	configuration may be %NULL, in which case the hardware will not be
496dcfbd67bSEmmanuel Grumbach  *	configured. If true is returned, the operation mode needs to increment
497dcfbd67bSEmmanuel Grumbach  *	the sequence number of the packets routed to this queue because of a
498dcfbd67bSEmmanuel Grumbach  *	hardware scheduler bug. May sleep.
499e705c121SKalle Valo  * @txq_disable: de-configure a Tx queue to send AMPDUs
500e705c121SKalle Valo  *	Must be atomic
50142db09c1SLiad Kaufman  * @txq_set_shared_mode: change Tx queue shared/unshared marking
502d6d517b7SSara Sharon  * @wait_tx_queues_empty: wait until tx queues are empty. May sleep.
503d6d517b7SSara Sharon  * @wait_txq_empty: wait until specific tx queue is empty. May sleep.
504e705c121SKalle Valo  * @freeze_txq_timer: prevents the timer of the queue from firing until the
505e705c121SKalle Valo  *	queue is set to awake. Must be atomic.
5060cd58eaaSEmmanuel Grumbach  * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note
5070cd58eaaSEmmanuel Grumbach  *	that the transport needs to refcount the calls since this function
5080cd58eaaSEmmanuel Grumbach  *	will be called several times with block = true, and then the queues
5090cd58eaaSEmmanuel Grumbach  *	need to be unblocked only after the same number of calls with
5100cd58eaaSEmmanuel Grumbach  *	block = false.
511e705c121SKalle Valo  * @write8: write a u8 to a register at offset ofs from the BAR
512e705c121SKalle Valo  * @write32: write a u32 to a register at offset ofs from the BAR
513e705c121SKalle Valo  * @read32: read a u32 register at offset ofs from the BAR
514e705c121SKalle Valo  * @read_prph: read a DWORD from a periphery register
515e705c121SKalle Valo  * @write_prph: write a DWORD to a periphery register
516e705c121SKalle Valo  * @read_mem: read device's SRAM in DWORD
517e705c121SKalle Valo  * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory
518e705c121SKalle Valo  *	will be zeroed.
519e705c121SKalle Valo  * @configure: configure parameters required by the transport layer from
520e705c121SKalle Valo  *	the op_mode. May be called several times before start_fw, can't be
521e705c121SKalle Valo  *	called after that.
522e705c121SKalle Valo  * @set_pmi: set the power pmi state
523e705c121SKalle Valo  * @grab_nic_access: wake the NIC to be able to access non-HBUS regs.
524e705c121SKalle Valo  *	Sleeping is not allowed between grab_nic_access and
525e705c121SKalle Valo  *	release_nic_access.
526e705c121SKalle Valo  * @release_nic_access: let the NIC go to sleep. The "flags" parameter
527e705c121SKalle Valo  *	must be the same one that was sent before to the grab_nic_access.
528e705c121SKalle Valo  * @set_bits_mask - set SRAM register according to value and mask.
529e705c121SKalle Valo  * @ref: grab a reference to the transport/FW layers, disallowing
530e705c121SKalle Valo  *	certain low power states
531e705c121SKalle Valo  * @unref: release a reference previously taken with @ref. Note that
532e705c121SKalle Valo  *	initially the reference count is 1, making an initial @unref
533e705c121SKalle Valo  *	necessary to allow low power states.
534e705c121SKalle Valo  * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last
535e705c121SKalle Valo  *	TX'ed commands and similar. The buffer will be vfree'd by the caller.
536e705c121SKalle Valo  *	Note that the transport must fill in the proper file headers.
537e705c121SKalle Valo  */
538e705c121SKalle Valo struct iwl_trans_ops {
539e705c121SKalle Valo 
540e705c121SKalle Valo 	int (*start_hw)(struct iwl_trans *iwl_trans, bool low_power);
541e705c121SKalle Valo 	void (*op_mode_leave)(struct iwl_trans *iwl_trans);
542e705c121SKalle Valo 	int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw,
543e705c121SKalle Valo 			bool run_in_rfkill);
544e705c121SKalle Valo 	void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr);
545e705c121SKalle Valo 	void (*stop_device)(struct iwl_trans *trans, bool low_power);
546e705c121SKalle Valo 
54723ae6128SMatti Gottlieb 	void (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset);
548e705c121SKalle Valo 	int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status,
54923ae6128SMatti Gottlieb 			 bool test, bool reset);
550e705c121SKalle Valo 
551e705c121SKalle Valo 	int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
552e705c121SKalle Valo 
553e705c121SKalle Valo 	int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
554e705c121SKalle Valo 		  struct iwl_device_cmd *dev_cmd, int queue);
555e705c121SKalle Valo 	void (*reclaim)(struct iwl_trans *trans, int queue, int ssn,
556e705c121SKalle Valo 			struct sk_buff_head *skbs);
557e705c121SKalle Valo 
558dcfbd67bSEmmanuel Grumbach 	bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn,
559e705c121SKalle Valo 			   const struct iwl_trans_txq_scd_cfg *cfg,
560e705c121SKalle Valo 			   unsigned int queue_wdg_timeout);
561e705c121SKalle Valo 	void (*txq_disable)(struct iwl_trans *trans, int queue,
562e705c121SKalle Valo 			    bool configure_scd);
5632f7a3863SLuca Coelho 	/* 22000 functions */
5646b35ff91SSara Sharon 	int (*txq_alloc)(struct iwl_trans *trans,
5651169310fSGolan Ben Ami 			 __le16 flags, u8 sta_id, u8 tid,
5665369774cSSara Sharon 			 int cmd_id, int size,
5676b35ff91SSara Sharon 			 unsigned int queue_wdg_timeout);
5686b35ff91SSara Sharon 	void (*txq_free)(struct iwl_trans *trans, int queue);
56992536c96SSara Sharon 	int (*rxq_dma_data)(struct iwl_trans *trans, int queue,
57092536c96SSara Sharon 			    struct iwl_trans_rxq_dma_data *data);
571e705c121SKalle Valo 
57242db09c1SLiad Kaufman 	void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id,
57342db09c1SLiad Kaufman 				    bool shared);
57442db09c1SLiad Kaufman 
575a1a57877SSara Sharon 	int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm);
576d6d517b7SSara Sharon 	int (*wait_txq_empty)(struct iwl_trans *trans, int queue);
577e705c121SKalle Valo 	void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs,
578e705c121SKalle Valo 				 bool freeze);
5790cd58eaaSEmmanuel Grumbach 	void (*block_txq_ptrs)(struct iwl_trans *trans, bool block);
580e705c121SKalle Valo 
581e705c121SKalle Valo 	void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val);
582e705c121SKalle Valo 	void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val);
583e705c121SKalle Valo 	u32 (*read32)(struct iwl_trans *trans, u32 ofs);
584e705c121SKalle Valo 	u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
585e705c121SKalle Valo 	void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
586e705c121SKalle Valo 	int (*read_mem)(struct iwl_trans *trans, u32 addr,
587e705c121SKalle Valo 			void *buf, int dwords);
588e705c121SKalle Valo 	int (*write_mem)(struct iwl_trans *trans, u32 addr,
589e705c121SKalle Valo 			 const void *buf, int dwords);
590e705c121SKalle Valo 	void (*configure)(struct iwl_trans *trans,
591e705c121SKalle Valo 			  const struct iwl_trans_config *trans_cfg);
592e705c121SKalle Valo 	void (*set_pmi)(struct iwl_trans *trans, bool state);
593870c2a11SGolan Ben Ami 	void (*sw_reset)(struct iwl_trans *trans);
59423ba9340SEmmanuel Grumbach 	bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags);
595e705c121SKalle Valo 	void (*release_nic_access)(struct iwl_trans *trans,
596e705c121SKalle Valo 				   unsigned long *flags);
597e705c121SKalle Valo 	void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask,
598e705c121SKalle Valo 			      u32 value);
599e705c121SKalle Valo 	void (*ref)(struct iwl_trans *trans);
600e705c121SKalle Valo 	void (*unref)(struct iwl_trans *trans);
601e705c121SKalle Valo 	int  (*suspend)(struct iwl_trans *trans);
602e705c121SKalle Valo 	void (*resume)(struct iwl_trans *trans);
603e705c121SKalle Valo 
604e705c121SKalle Valo 	struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans,
605a80c7a69SEmmanuel Grumbach 						 const struct iwl_fw_dbg_trigger_tlv
606e705c121SKalle Valo 						 *trigger);
607e705c121SKalle Valo };
608e705c121SKalle Valo 
609e705c121SKalle Valo /**
610e705c121SKalle Valo  * enum iwl_trans_state - state of the transport layer
611e705c121SKalle Valo  *
612e705c121SKalle Valo  * @IWL_TRANS_NO_FW: no fw has sent an alive response
613e705c121SKalle Valo  * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response
614e705c121SKalle Valo  */
615e705c121SKalle Valo enum iwl_trans_state {
616e705c121SKalle Valo 	IWL_TRANS_NO_FW = 0,
617e705c121SKalle Valo 	IWL_TRANS_FW_ALIVE	= 1,
618e705c121SKalle Valo };
619e705c121SKalle Valo 
620e705c121SKalle Valo /**
621b7282643SLuca Coelho  * DOC: Platform power management
622e705c121SKalle Valo  *
623b7282643SLuca Coelho  * There are two types of platform power management: system-wide
624b7282643SLuca Coelho  * (WoWLAN) and runtime.
625b7282643SLuca Coelho  *
626b7282643SLuca Coelho  * In system-wide power management the entire platform goes into a low
627b7282643SLuca Coelho  * power state (e.g. idle or suspend to RAM) at the same time and the
628b7282643SLuca Coelho  * device is configured as a wakeup source for the entire platform.
629b7282643SLuca Coelho  * This is usually triggered by userspace activity (e.g. the user
630b7282643SLuca Coelho  * presses the suspend button or a power management daemon decides to
631b7282643SLuca Coelho  * put the platform in low power mode).  The device's behavior in this
632b7282643SLuca Coelho  * mode is dictated by the wake-on-WLAN configuration.
633b7282643SLuca Coelho  *
634b7282643SLuca Coelho  * In runtime power management, only the devices which are themselves
635b7282643SLuca Coelho  * idle enter a low power state.  This is done at runtime, which means
636b7282643SLuca Coelho  * that the entire system is still running normally.  This mode is
637b7282643SLuca Coelho  * usually triggered automatically by the device driver and requires
638b7282643SLuca Coelho  * the ability to enter and exit the low power modes in a very short
639b7282643SLuca Coelho  * time, so there is not much impact in usability.
640b7282643SLuca Coelho  *
641b7282643SLuca Coelho  * The terms used for the device's behavior are as follows:
642b7282643SLuca Coelho  *
643b7282643SLuca Coelho  *	- D0: the device is fully powered and the host is awake;
644b7282643SLuca Coelho  *	- D3: the device is in low power mode and only reacts to
645b7282643SLuca Coelho  *		specific events (e.g. magic-packet received or scan
646b7282643SLuca Coelho  *		results found);
647b7282643SLuca Coelho  *	- D0I3: the device is in low power mode and reacts to any
648b7282643SLuca Coelho  *		activity (e.g. RX);
649b7282643SLuca Coelho  *
650b7282643SLuca Coelho  * These terms reflect the power modes in the firmware and are not to
651b7282643SLuca Coelho  * be confused with the physical device power state.  The NIC can be
652b7282643SLuca Coelho  * in D0I3 mode even if, for instance, the PCI device is in D3 state.
653e705c121SKalle Valo  */
654b7282643SLuca Coelho 
655b7282643SLuca Coelho /**
656b7282643SLuca Coelho  * enum iwl_plat_pm_mode - platform power management mode
657b7282643SLuca Coelho  *
658b7282643SLuca Coelho  * This enumeration describes the device's platform power management
659b7282643SLuca Coelho  * behavior when in idle mode (i.e. runtime power management) or when
660b7282643SLuca Coelho  * in system-wide suspend (i.e WoWLAN).
661b7282643SLuca Coelho  *
662b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this
663b7282643SLuca Coelho  *	device.  At runtime, this means that nothing happens and the
664b7282643SLuca Coelho  *	device always remains in active.  In system-wide suspend mode,
665b7282643SLuca Coelho  *	it means that the all connections will be closed automatically
666b7282643SLuca Coelho  *	by mac80211 before the platform is suspended.
667b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).
668b7282643SLuca Coelho  *	For runtime power management, this mode is not officially
669b7282643SLuca Coelho  *	supported.
670b7282643SLuca Coelho  * @IWL_PLAT_PM_MODE_D0I3: the device goes into D0I3 mode.
671b7282643SLuca Coelho  */
672b7282643SLuca Coelho enum iwl_plat_pm_mode {
673b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_DISABLED,
674b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_D3,
675b7282643SLuca Coelho 	IWL_PLAT_PM_MODE_D0I3,
676e705c121SKalle Valo };
677e705c121SKalle Valo 
6784cbb8e50SLuciano Coelho /* Max time to wait for trans to become idle/non-idle on d0i3
6794cbb8e50SLuciano Coelho  * enter/exit (in msecs).
6804cbb8e50SLuciano Coelho  */
6814cbb8e50SLuciano Coelho #define IWL_TRANS_IDLE_TIMEOUT 2000
68288964b2eSSara Sharon #define IWL_MAX_DEBUG_ALLOCATIONS	1
68388964b2eSSara Sharon 
68488964b2eSSara Sharon /**
68588964b2eSSara Sharon  * struct iwl_dram_data
68688964b2eSSara Sharon  * @physical: page phy pointer
68788964b2eSSara Sharon  * @block: pointer to the allocated block/page
68888964b2eSSara Sharon  * @size: size of the block/page
68988964b2eSSara Sharon  */
69088964b2eSSara Sharon struct iwl_dram_data {
69188964b2eSSara Sharon 	dma_addr_t physical;
69288964b2eSSara Sharon 	void *block;
69388964b2eSSara Sharon 	int size;
69488964b2eSSara Sharon };
6954cbb8e50SLuciano Coelho 
696e705c121SKalle Valo /**
697e705c121SKalle Valo  * struct iwl_trans - transport common data
698e705c121SKalle Valo  *
699e705c121SKalle Valo  * @ops - pointer to iwl_trans_ops
700e705c121SKalle Valo  * @op_mode - pointer to the op_mode
701e705c121SKalle Valo  * @cfg - pointer to the configuration
7026f482e37SSara Sharon  * @drv - pointer to iwl_drv
703e705c121SKalle Valo  * @status: a bit-mask of transport status flags
704e705c121SKalle Valo  * @dev - pointer to struct device * that represents the device
705e705c121SKalle Valo  * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.
706e705c121SKalle Valo  *	0 indicates that frag SKBs (NETIF_F_SG) aren't supported.
7071afb0ae4SHaim Dreyfuss  * @hw_rf_id a u32 with the device RF ID
708e705c121SKalle Valo  * @hw_id: a u32 with the ID of the device / sub-device.
709e705c121SKalle Valo  *	Set during transport allocation.
710e705c121SKalle Valo  * @hw_id_str: a string with info about HW ID. Set during transport allocation.
711e705c121SKalle Valo  * @pm_support: set to true in start_hw if link pm is supported
712e705c121SKalle Valo  * @ltr_enabled: set to true if the LTR is enabled
7135b88792cSSara Sharon  * @wide_cmd_header: true when ucode supports wide command header format
714e705c121SKalle Valo  * @num_rx_queues: number of RX queues allocated by the transport;
715e705c121SKalle Valo  *	the transport must set this before calling iwl_drv_start()
716132db31cSGolan Ben-Ami  * @iml_len: the length of the image loader
717132db31cSGolan Ben-Ami  * @iml: a pointer to the image loader itself
718e705c121SKalle Valo  * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.
719e705c121SKalle Valo  *	The user should use iwl_trans_{alloc,free}_tx_cmd.
720e705c121SKalle Valo  * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before
721e705c121SKalle Valo  *	starting the firmware, used for tracing
722e705c121SKalle Valo  * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the
723e705c121SKalle Valo  *	start of the 802.11 header in the @rx_mpdu_cmd
724e705c121SKalle Valo  * @dflt_pwr_limit: default power limit fetched from the platform (ACPI)
725e705c121SKalle Valo  * @dbg_dest_tlv: points to the destination TLV for debug
726e705c121SKalle Valo  * @dbg_conf_tlv: array of pointers to configuration TLVs for debug
727e705c121SKalle Valo  * @dbg_trigger_tlv: array of pointers to triggers TLVs for debug
728e705c121SKalle Valo  * @dbg_dest_reg_num: num of reg_ops in %dbg_dest_tlv
72988964b2eSSara Sharon  * @num_blocks: number of blocks in fw_mon
73088964b2eSSara Sharon  * @fw_mon: address of the buffers for firmware monitor
731b7282643SLuca Coelho  * @system_pm_mode: the system-wide power management mode in use.
732b7282643SLuca Coelho  *	This mode is set dynamically, depending on the WoWLAN values
733b7282643SLuca Coelho  *	configured from the userspace at runtime.
734b7282643SLuca Coelho  * @runtime_pm_mode: the runtime power management mode in use.  This
735b7282643SLuca Coelho  *	mode is set during the initialization phase and is not
736b7282643SLuca Coelho  *	supposed to change during runtime.
737e705c121SKalle Valo  */
738e705c121SKalle Valo struct iwl_trans {
739e705c121SKalle Valo 	const struct iwl_trans_ops *ops;
740e705c121SKalle Valo 	struct iwl_op_mode *op_mode;
741e705c121SKalle Valo 	const struct iwl_cfg *cfg;
7426f482e37SSara Sharon 	struct iwl_drv *drv;
743e705c121SKalle Valo 	enum iwl_trans_state state;
744e705c121SKalle Valo 	unsigned long status;
745e705c121SKalle Valo 
746e705c121SKalle Valo 	struct device *dev;
747e705c121SKalle Valo 	u32 max_skb_frags;
748e705c121SKalle Valo 	u32 hw_rev;
7491afb0ae4SHaim Dreyfuss 	u32 hw_rf_id;
750e705c121SKalle Valo 	u32 hw_id;
751e705c121SKalle Valo 	char hw_id_str[52];
752e705c121SKalle Valo 
753e705c121SKalle Valo 	u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
754e705c121SKalle Valo 
755e705c121SKalle Valo 	bool pm_support;
756e705c121SKalle Valo 	bool ltr_enabled;
757e705c121SKalle Valo 
75839bdb17eSSharon Dvir 	const struct iwl_hcmd_arr *command_groups;
75939bdb17eSSharon Dvir 	int command_groups_size;
7605b88792cSSara Sharon 	bool wide_cmd_header;
76139bdb17eSSharon Dvir 
762e705c121SKalle Valo 	u8 num_rx_queues;
763e705c121SKalle Valo 
764132db31cSGolan Ben-Ami 	size_t iml_len;
765132db31cSGolan Ben-Ami 	u8 *iml;
766132db31cSGolan Ben-Ami 
767e705c121SKalle Valo 	/* The following fields are internal only */
768e705c121SKalle Valo 	struct kmem_cache *dev_cmd_pool;
769e705c121SKalle Valo 	char dev_cmd_pool_name[50];
770e705c121SKalle Valo 
771e705c121SKalle Valo 	struct dentry *dbgfs_dir;
772e705c121SKalle Valo 
773e705c121SKalle Valo #ifdef CONFIG_LOCKDEP
774e705c121SKalle Valo 	struct lockdep_map sync_cmd_lockdep_map;
775e705c121SKalle Valo #endif
776e705c121SKalle Valo 
777fd527eb5SGolan Ben Ami 	const struct iwl_fw_dbg_dest_tlv_v1 *dbg_dest_tlv;
778e705c121SKalle Valo 	const struct iwl_fw_dbg_conf_tlv *dbg_conf_tlv[FW_DBG_CONF_MAX];
779e705c121SKalle Valo 	struct iwl_fw_dbg_trigger_tlv * const *dbg_trigger_tlv;
780520f03eaSShahar S Matityahu 	u32 dbg_dump_mask;
781e705c121SKalle Valo 	u8 dbg_dest_reg_num;
78288964b2eSSara Sharon 	int num_blocks;
78388964b2eSSara Sharon 	struct iwl_dram_data fw_mon[IWL_MAX_DEBUG_ALLOCATIONS];
784e705c121SKalle Valo 
785b7282643SLuca Coelho 	enum iwl_plat_pm_mode system_pm_mode;
786b7282643SLuca Coelho 	enum iwl_plat_pm_mode runtime_pm_mode;
787863eac30SLuca Coelho 	bool suspending;
788e705c121SKalle Valo 
789e705c121SKalle Valo 	/* pointer to trans specific struct */
790e705c121SKalle Valo 	/*Ensure that this pointer will always be aligned to sizeof pointer */
791e705c121SKalle Valo 	char trans_specific[0] __aligned(sizeof(void *));
792e705c121SKalle Valo };
793e705c121SKalle Valo 
79439bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);
79539bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);
79639bdb17eSSharon Dvir 
797e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans,
798e705c121SKalle Valo 				       const struct iwl_trans_config *trans_cfg)
799e705c121SKalle Valo {
800e705c121SKalle Valo 	trans->op_mode = trans_cfg->op_mode;
801e705c121SKalle Valo 
802e705c121SKalle Valo 	trans->ops->configure(trans, trans_cfg);
80339bdb17eSSharon Dvir 	WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg));
804e705c121SKalle Valo }
805e705c121SKalle Valo 
806e705c121SKalle Valo static inline int _iwl_trans_start_hw(struct iwl_trans *trans, bool low_power)
807e705c121SKalle Valo {
808e705c121SKalle Valo 	might_sleep();
809e705c121SKalle Valo 
810e705c121SKalle Valo 	return trans->ops->start_hw(trans, low_power);
811e705c121SKalle Valo }
812e705c121SKalle Valo 
813e705c121SKalle Valo static inline int iwl_trans_start_hw(struct iwl_trans *trans)
814e705c121SKalle Valo {
815e705c121SKalle Valo 	return trans->ops->start_hw(trans, true);
816e705c121SKalle Valo }
817e705c121SKalle Valo 
818e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans)
819e705c121SKalle Valo {
820e705c121SKalle Valo 	might_sleep();
821e705c121SKalle Valo 
822e705c121SKalle Valo 	if (trans->ops->op_mode_leave)
823e705c121SKalle Valo 		trans->ops->op_mode_leave(trans);
824e705c121SKalle Valo 
825e705c121SKalle Valo 	trans->op_mode = NULL;
826e705c121SKalle Valo 
827e705c121SKalle Valo 	trans->state = IWL_TRANS_NO_FW;
828e705c121SKalle Valo }
829e705c121SKalle Valo 
830e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr)
831e705c121SKalle Valo {
832e705c121SKalle Valo 	might_sleep();
833e705c121SKalle Valo 
834e705c121SKalle Valo 	trans->state = IWL_TRANS_FW_ALIVE;
835e705c121SKalle Valo 
836e705c121SKalle Valo 	trans->ops->fw_alive(trans, scd_addr);
837e705c121SKalle Valo }
838e705c121SKalle Valo 
839e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans,
840e705c121SKalle Valo 				     const struct fw_img *fw,
841e705c121SKalle Valo 				     bool run_in_rfkill)
842e705c121SKalle Valo {
843e705c121SKalle Valo 	might_sleep();
844e705c121SKalle Valo 
845e705c121SKalle Valo 	WARN_ON_ONCE(!trans->rx_mpdu_cmd);
846e705c121SKalle Valo 
847e705c121SKalle Valo 	clear_bit(STATUS_FW_ERROR, &trans->status);
848e705c121SKalle Valo 	return trans->ops->start_fw(trans, fw, run_in_rfkill);
849e705c121SKalle Valo }
850e705c121SKalle Valo 
851e705c121SKalle Valo static inline void _iwl_trans_stop_device(struct iwl_trans *trans,
852e705c121SKalle Valo 					  bool low_power)
853e705c121SKalle Valo {
854e705c121SKalle Valo 	might_sleep();
855e705c121SKalle Valo 
856e705c121SKalle Valo 	trans->ops->stop_device(trans, low_power);
857e705c121SKalle Valo 
858e705c121SKalle Valo 	trans->state = IWL_TRANS_NO_FW;
859e705c121SKalle Valo }
860e705c121SKalle Valo 
861e705c121SKalle Valo static inline void iwl_trans_stop_device(struct iwl_trans *trans)
862e705c121SKalle Valo {
863e705c121SKalle Valo 	_iwl_trans_stop_device(trans, true);
864e705c121SKalle Valo }
865e705c121SKalle Valo 
86623ae6128SMatti Gottlieb static inline void iwl_trans_d3_suspend(struct iwl_trans *trans, bool test,
86723ae6128SMatti Gottlieb 					bool reset)
868e705c121SKalle Valo {
869e705c121SKalle Valo 	might_sleep();
870e705c121SKalle Valo 	if (trans->ops->d3_suspend)
87123ae6128SMatti Gottlieb 		trans->ops->d3_suspend(trans, test, reset);
872e705c121SKalle Valo }
873e705c121SKalle Valo 
874e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans,
875e705c121SKalle Valo 				      enum iwl_d3_status *status,
87623ae6128SMatti Gottlieb 				      bool test, bool reset)
877e705c121SKalle Valo {
878e705c121SKalle Valo 	might_sleep();
879e705c121SKalle Valo 	if (!trans->ops->d3_resume)
880e705c121SKalle Valo 		return 0;
881e705c121SKalle Valo 
88223ae6128SMatti Gottlieb 	return trans->ops->d3_resume(trans, status, test, reset);
883e705c121SKalle Valo }
884e705c121SKalle Valo 
885e705c121SKalle Valo static inline int iwl_trans_suspend(struct iwl_trans *trans)
886e705c121SKalle Valo {
887e705c121SKalle Valo 	if (!trans->ops->suspend)
888e705c121SKalle Valo 		return 0;
889e705c121SKalle Valo 
890e705c121SKalle Valo 	return trans->ops->suspend(trans);
891e705c121SKalle Valo }
892e705c121SKalle Valo 
893e705c121SKalle Valo static inline void iwl_trans_resume(struct iwl_trans *trans)
894e705c121SKalle Valo {
895e705c121SKalle Valo 	if (trans->ops->resume)
896e705c121SKalle Valo 		trans->ops->resume(trans);
897e705c121SKalle Valo }
898e705c121SKalle Valo 
899e705c121SKalle Valo static inline struct iwl_trans_dump_data *
900e705c121SKalle Valo iwl_trans_dump_data(struct iwl_trans *trans,
901a80c7a69SEmmanuel Grumbach 		    const struct iwl_fw_dbg_trigger_tlv *trigger)
902e705c121SKalle Valo {
903e705c121SKalle Valo 	if (!trans->ops->dump_data)
904e705c121SKalle Valo 		return NULL;
905e705c121SKalle Valo 	return trans->ops->dump_data(trans, trigger);
906e705c121SKalle Valo }
907e705c121SKalle Valo 
908e705c121SKalle Valo static inline struct iwl_device_cmd *
909e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)
910e705c121SKalle Valo {
9110ae0bb3fSLuca Coelho 	return kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC);
912e705c121SKalle Valo }
913e705c121SKalle Valo 
91492fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
91592fe8343SEmmanuel Grumbach 
916e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,
917e705c121SKalle Valo 					 struct iwl_device_cmd *dev_cmd)
918e705c121SKalle Valo {
9191ea423b0SLuca Coelho 	kmem_cache_free(trans->dev_cmd_pool, dev_cmd);
920e705c121SKalle Valo }
921e705c121SKalle Valo 
922e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
923e705c121SKalle Valo 			       struct iwl_device_cmd *dev_cmd, int queue)
924e705c121SKalle Valo {
925e705c121SKalle Valo 	if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status)))
926e705c121SKalle Valo 		return -EIO;
927e705c121SKalle Valo 
928e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
929e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
930e5d15cb5SEliad Peller 		return -EIO;
931e5d15cb5SEliad Peller 	}
932e705c121SKalle Valo 
933e705c121SKalle Valo 	return trans->ops->tx(trans, skb, dev_cmd, queue);
934e705c121SKalle Valo }
935e705c121SKalle Valo 
936e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue,
937e705c121SKalle Valo 				     int ssn, struct sk_buff_head *skbs)
938e705c121SKalle Valo {
939e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
940e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
941e5d15cb5SEliad Peller 		return;
942e5d15cb5SEliad Peller 	}
943e705c121SKalle Valo 
944e705c121SKalle Valo 	trans->ops->reclaim(trans, queue, ssn, skbs);
945e705c121SKalle Valo }
946e705c121SKalle Valo 
947e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,
948e705c121SKalle Valo 					 bool configure_scd)
949e705c121SKalle Valo {
950e705c121SKalle Valo 	trans->ops->txq_disable(trans, queue, configure_scd);
951e705c121SKalle Valo }
952e705c121SKalle Valo 
953dcfbd67bSEmmanuel Grumbach static inline bool
954e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,
955e705c121SKalle Valo 			 const struct iwl_trans_txq_scd_cfg *cfg,
956e705c121SKalle Valo 			 unsigned int queue_wdg_timeout)
957e705c121SKalle Valo {
958e705c121SKalle Valo 	might_sleep();
959e705c121SKalle Valo 
960e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
961e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
962dcfbd67bSEmmanuel Grumbach 		return false;
963e5d15cb5SEliad Peller 	}
964e705c121SKalle Valo 
965dcfbd67bSEmmanuel Grumbach 	return trans->ops->txq_enable(trans, queue, ssn,
966dcfbd67bSEmmanuel Grumbach 				      cfg, queue_wdg_timeout);
967e705c121SKalle Valo }
968e705c121SKalle Valo 
96992536c96SSara Sharon static inline int
97092536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,
97192536c96SSara Sharon 			   struct iwl_trans_rxq_dma_data *data)
97292536c96SSara Sharon {
97392536c96SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->rxq_dma_data))
97492536c96SSara Sharon 		return -ENOTSUPP;
97592536c96SSara Sharon 
97692536c96SSara Sharon 	return trans->ops->rxq_dma_data(trans, queue, data);
97792536c96SSara Sharon }
97892536c96SSara Sharon 
9796b35ff91SSara Sharon static inline void
9806b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue)
9816b35ff91SSara Sharon {
9826b35ff91SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->txq_free))
9836b35ff91SSara Sharon 		return;
9846b35ff91SSara Sharon 
9856b35ff91SSara Sharon 	trans->ops->txq_free(trans, queue);
9866b35ff91SSara Sharon }
9876b35ff91SSara Sharon 
9886b35ff91SSara Sharon static inline int
9896b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans,
9901169310fSGolan Ben Ami 		    __le16 flags, u8 sta_id, u8 tid,
9915369774cSSara Sharon 		    int cmd_id, int size,
9925369774cSSara Sharon 		    unsigned int wdg_timeout)
9936b35ff91SSara Sharon {
9946b35ff91SSara Sharon 	might_sleep();
9956b35ff91SSara Sharon 
9966b35ff91SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->txq_alloc))
9976b35ff91SSara Sharon 		return -ENOTSUPP;
9986b35ff91SSara Sharon 
9996b35ff91SSara Sharon 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
10006b35ff91SSara Sharon 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
10016b35ff91SSara Sharon 		return -EIO;
10026b35ff91SSara Sharon 	}
10036b35ff91SSara Sharon 
10041169310fSGolan Ben Ami 	return trans->ops->txq_alloc(trans, flags, sta_id, tid,
10051169310fSGolan Ben Ami 				     cmd_id, size, wdg_timeout);
10066b35ff91SSara Sharon }
10076b35ff91SSara Sharon 
100842db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,
100942db09c1SLiad Kaufman 						 int queue, bool shared_mode)
101042db09c1SLiad Kaufman {
101142db09c1SLiad Kaufman 	if (trans->ops->txq_set_shared_mode)
101242db09c1SLiad Kaufman 		trans->ops->txq_set_shared_mode(trans, queue, shared_mode);
101342db09c1SLiad Kaufman }
101442db09c1SLiad Kaufman 
1015e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,
1016e705c121SKalle Valo 					int fifo, int sta_id, int tid,
1017e705c121SKalle Valo 					int frame_limit, u16 ssn,
1018e705c121SKalle Valo 					unsigned int queue_wdg_timeout)
1019e705c121SKalle Valo {
1020e705c121SKalle Valo 	struct iwl_trans_txq_scd_cfg cfg = {
1021e705c121SKalle Valo 		.fifo = fifo,
1022e705c121SKalle Valo 		.sta_id = sta_id,
1023e705c121SKalle Valo 		.tid = tid,
1024e705c121SKalle Valo 		.frame_limit = frame_limit,
1025e705c121SKalle Valo 		.aggregate = sta_id >= 0,
1026e705c121SKalle Valo 	};
1027e705c121SKalle Valo 
1028e705c121SKalle Valo 	iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);
1029e705c121SKalle Valo }
1030e705c121SKalle Valo 
1031e705c121SKalle Valo static inline
1032e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,
1033e705c121SKalle Valo 			     unsigned int queue_wdg_timeout)
1034e705c121SKalle Valo {
1035e705c121SKalle Valo 	struct iwl_trans_txq_scd_cfg cfg = {
1036e705c121SKalle Valo 		.fifo = fifo,
1037e705c121SKalle Valo 		.sta_id = -1,
1038e705c121SKalle Valo 		.tid = IWL_MAX_TID_COUNT,
1039e705c121SKalle Valo 		.frame_limit = IWL_FRAME_LIMIT,
1040e705c121SKalle Valo 		.aggregate = false,
1041e705c121SKalle Valo 	};
1042e705c121SKalle Valo 
1043e705c121SKalle Valo 	iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);
1044e705c121SKalle Valo }
1045e705c121SKalle Valo 
1046e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,
1047e705c121SKalle Valo 					      unsigned long txqs,
1048e705c121SKalle Valo 					      bool freeze)
1049e705c121SKalle Valo {
1050e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1051e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1052e5d15cb5SEliad Peller 		return;
1053e5d15cb5SEliad Peller 	}
1054e705c121SKalle Valo 
1055e705c121SKalle Valo 	if (trans->ops->freeze_txq_timer)
1056e705c121SKalle Valo 		trans->ops->freeze_txq_timer(trans, txqs, freeze);
1057e705c121SKalle Valo }
1058e705c121SKalle Valo 
10590cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans,
10600cd58eaaSEmmanuel Grumbach 					    bool block)
10610cd58eaaSEmmanuel Grumbach {
1062e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
10630cd58eaaSEmmanuel Grumbach 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1064e5d15cb5SEliad Peller 		return;
1065e5d15cb5SEliad Peller 	}
10660cd58eaaSEmmanuel Grumbach 
10670cd58eaaSEmmanuel Grumbach 	if (trans->ops->block_txq_ptrs)
10680cd58eaaSEmmanuel Grumbach 		trans->ops->block_txq_ptrs(trans, block);
10690cd58eaaSEmmanuel Grumbach }
10700cd58eaaSEmmanuel Grumbach 
1071a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans,
1072e705c121SKalle Valo 						 u32 txqs)
1073e705c121SKalle Valo {
1074d6d517b7SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty))
1075d6d517b7SSara Sharon 		return -ENOTSUPP;
1076d6d517b7SSara Sharon 
1077e5d15cb5SEliad Peller 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1078e705c121SKalle Valo 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1079e5d15cb5SEliad Peller 		return -EIO;
1080e5d15cb5SEliad Peller 	}
1081e705c121SKalle Valo 
1082a1a57877SSara Sharon 	return trans->ops->wait_tx_queues_empty(trans, txqs);
1083e705c121SKalle Valo }
1084e705c121SKalle Valo 
1085d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue)
1086d6d517b7SSara Sharon {
1087d6d517b7SSara Sharon 	if (WARN_ON_ONCE(!trans->ops->wait_txq_empty))
1088d6d517b7SSara Sharon 		return -ENOTSUPP;
1089d6d517b7SSara Sharon 
1090d6d517b7SSara Sharon 	if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) {
1091d6d517b7SSara Sharon 		IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state);
1092d6d517b7SSara Sharon 		return -EIO;
1093d6d517b7SSara Sharon 	}
1094d6d517b7SSara Sharon 
1095d6d517b7SSara Sharon 	return trans->ops->wait_txq_empty(trans, queue);
1096d6d517b7SSara Sharon }
1097d6d517b7SSara Sharon 
1098e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1099e705c121SKalle Valo {
1100e705c121SKalle Valo 	trans->ops->write8(trans, ofs, val);
1101e705c121SKalle Valo }
1102e705c121SKalle Valo 
1103e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1104e705c121SKalle Valo {
1105e705c121SKalle Valo 	trans->ops->write32(trans, ofs, val);
1106e705c121SKalle Valo }
1107e705c121SKalle Valo 
1108e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs)
1109e705c121SKalle Valo {
1110e705c121SKalle Valo 	return trans->ops->read32(trans, ofs);
1111e705c121SKalle Valo }
1112e705c121SKalle Valo 
1113e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs)
1114e705c121SKalle Valo {
1115e705c121SKalle Valo 	return trans->ops->read_prph(trans, ofs);
1116e705c121SKalle Valo }
1117e705c121SKalle Valo 
1118e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
1119e705c121SKalle Valo 					u32 val)
1120e705c121SKalle Valo {
1121e705c121SKalle Valo 	return trans->ops->write_prph(trans, ofs, val);
1122e705c121SKalle Valo }
1123e705c121SKalle Valo 
1124e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
1125e705c121SKalle Valo 				     void *buf, int dwords)
1126e705c121SKalle Valo {
1127e705c121SKalle Valo 	return trans->ops->read_mem(trans, addr, buf, dwords);
1128e705c121SKalle Valo }
1129e705c121SKalle Valo 
1130e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize)		      \
1131e705c121SKalle Valo 	do {								      \
1132e705c121SKalle Valo 		if (__builtin_constant_p(bufsize))			      \
1133e705c121SKalle Valo 			BUILD_BUG_ON((bufsize) % sizeof(u32));		      \
1134e705c121SKalle Valo 		iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
1135e705c121SKalle Valo 	} while (0)
1136e705c121SKalle Valo 
1137e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
1138e705c121SKalle Valo {
1139e705c121SKalle Valo 	u32 value;
1140e705c121SKalle Valo 
1141e705c121SKalle Valo 	if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
1142e705c121SKalle Valo 		return 0xa5a5a5a5;
1143e705c121SKalle Valo 
1144e705c121SKalle Valo 	return value;
1145e705c121SKalle Valo }
1146e705c121SKalle Valo 
1147e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
1148e705c121SKalle Valo 				      const void *buf, int dwords)
1149e705c121SKalle Valo {
1150e705c121SKalle Valo 	return trans->ops->write_mem(trans, addr, buf, dwords);
1151e705c121SKalle Valo }
1152e705c121SKalle Valo 
1153e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
1154e705c121SKalle Valo 					u32 val)
1155e705c121SKalle Valo {
1156e705c121SKalle Valo 	return iwl_trans_write_mem(trans, addr, &val, 1);
1157e705c121SKalle Valo }
1158e705c121SKalle Valo 
1159e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
1160e705c121SKalle Valo {
1161e705c121SKalle Valo 	if (trans->ops->set_pmi)
1162e705c121SKalle Valo 		trans->ops->set_pmi(trans, state);
1163e705c121SKalle Valo }
1164e705c121SKalle Valo 
1165870c2a11SGolan Ben Ami static inline void iwl_trans_sw_reset(struct iwl_trans *trans)
1166870c2a11SGolan Ben Ami {
1167870c2a11SGolan Ben Ami 	if (trans->ops->sw_reset)
1168870c2a11SGolan Ben Ami 		trans->ops->sw_reset(trans);
1169870c2a11SGolan Ben Ami }
1170870c2a11SGolan Ben Ami 
1171e705c121SKalle Valo static inline void
1172e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
1173e705c121SKalle Valo {
1174e705c121SKalle Valo 	trans->ops->set_bits_mask(trans, reg, mask, value);
1175e705c121SKalle Valo }
1176e705c121SKalle Valo 
117723ba9340SEmmanuel Grumbach #define iwl_trans_grab_nic_access(trans, flags)	\
1178e705c121SKalle Valo 	__cond_lock(nic_access,				\
117923ba9340SEmmanuel Grumbach 		    likely((trans)->ops->grab_nic_access(trans, flags)))
1180e705c121SKalle Valo 
1181e705c121SKalle Valo static inline void __releases(nic_access)
1182e705c121SKalle Valo iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags)
1183e705c121SKalle Valo {
1184e705c121SKalle Valo 	trans->ops->release_nic_access(trans, flags);
1185e705c121SKalle Valo 	__release(nic_access);
1186e705c121SKalle Valo }
1187e705c121SKalle Valo 
1188e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans)
1189e705c121SKalle Valo {
1190e705c121SKalle Valo 	if (WARN_ON_ONCE(!trans->op_mode))
1191e705c121SKalle Valo 		return;
1192e705c121SKalle Valo 
1193e705c121SKalle Valo 	/* prevent double restarts due to the same erroneous FW */
1194e705c121SKalle Valo 	if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status))
1195e705c121SKalle Valo 		iwl_op_mode_nic_error(trans->op_mode);
1196e705c121SKalle Valo }
1197e705c121SKalle Valo 
1198e705c121SKalle Valo /*****************************************************
1199e705c121SKalle Valo  * transport helper functions
1200e705c121SKalle Valo  *****************************************************/
1201e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,
1202e705c121SKalle Valo 				  struct device *dev,
1203e705c121SKalle Valo 				  const struct iwl_cfg *cfg,
12041ea423b0SLuca Coelho 				  const struct iwl_trans_ops *ops);
1205e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans);
1206d621d3c7SLuca Coelho void iwl_trans_ref(struct iwl_trans *trans);
1207d621d3c7SLuca Coelho void iwl_trans_unref(struct iwl_trans *trans);
1208e705c121SKalle Valo 
1209e705c121SKalle Valo /*****************************************************
1210e705c121SKalle Valo * driver (transport) register/unregister functions
1211e705c121SKalle Valo ******************************************************/
1212e705c121SKalle Valo int __must_check iwl_pci_register_driver(void);
1213e705c121SKalle Valo void iwl_pci_unregister_driver(void);
1214e705c121SKalle Valo 
1215e705c121SKalle Valo #endif /* __iwl_trans_h__ */
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