1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 106b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 336b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #ifndef __iwl_trans_h__ 65e705c121SKalle Valo #define __iwl_trans_h__ 66e705c121SKalle Valo 67e705c121SKalle Valo #include <linux/ieee80211.h> 68e705c121SKalle Valo #include <linux/mm.h> /* for page_address */ 69e705c121SKalle Valo #include <linux/lockdep.h> 7039bdb17eSSharon Dvir #include <linux/kernel.h> 71e705c121SKalle Valo 72e705c121SKalle Valo #include "iwl-debug.h" 73e705c121SKalle Valo #include "iwl-config.h" 74d962f9b1SJohannes Berg #include "fw/img.h" 75e705c121SKalle Valo #include "iwl-op-mode.h" 76d172a5efSJohannes Berg #include "fw/api/cmdhdr.h" 77d172a5efSJohannes Berg #include "fw/api/txq.h" 78f14cda6fSSara Sharon #include "fw/api/dbg-tlv.h" 79f14cda6fSSara Sharon #include "iwl-dbg-tlv.h" 80e705c121SKalle Valo 81e705c121SKalle Valo /** 82e705c121SKalle Valo * DOC: Transport layer - what is it ? 83e705c121SKalle Valo * 84e705c121SKalle Valo * The transport layer is the layer that deals with the HW directly. It provides 85e705c121SKalle Valo * an abstraction of the underlying HW to the upper layer. The transport layer 86e705c121SKalle Valo * doesn't provide any policy, algorithm or anything of this kind, but only 87e705c121SKalle Valo * mechanisms to make the HW do something. It is not completely stateless but 88e705c121SKalle Valo * close to it. 89e705c121SKalle Valo * We will have an implementation for each different supported bus. 90e705c121SKalle Valo */ 91e705c121SKalle Valo 92e705c121SKalle Valo /** 93e705c121SKalle Valo * DOC: Life cycle of the transport layer 94e705c121SKalle Valo * 95e705c121SKalle Valo * The transport layer has a very precise life cycle. 96e705c121SKalle Valo * 97e705c121SKalle Valo * 1) A helper function is called during the module initialization and 98e705c121SKalle Valo * registers the bus driver's ops with the transport's alloc function. 99e705c121SKalle Valo * 2) Bus's probe calls to the transport layer's allocation functions. 100e705c121SKalle Valo * Of course this function is bus specific. 101e705c121SKalle Valo * 3) This allocation functions will spawn the upper layer which will 102e705c121SKalle Valo * register mac80211. 103e705c121SKalle Valo * 104e705c121SKalle Valo * 4) At some point (i.e. mac80211's start call), the op_mode will call 105e705c121SKalle Valo * the following sequence: 106e705c121SKalle Valo * start_hw 107e705c121SKalle Valo * start_fw 108e705c121SKalle Valo * 109e705c121SKalle Valo * 5) Then when finished (or reset): 110e705c121SKalle Valo * stop_device 111e705c121SKalle Valo * 112e705c121SKalle Valo * 6) Eventually, the free function will be called. 113e705c121SKalle Valo */ 114e705c121SKalle Valo 115e701da0cSLuca Coelho #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 116e701da0cSLuca Coelho 117e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 118e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID 0x55550000 119e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN 0x40 120fbe41127SSara Sharon #define FH_RSCSR_RPA_EN BIT(25) 1219d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN BIT(26) 122ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS 16 123ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK 0x3F0000 124e705c121SKalle Valo 125e705c121SKalle Valo struct iwl_rx_packet { 126e705c121SKalle Valo /* 127e705c121SKalle Valo * The first 4 bytes of the RX frame header contain both the RX frame 128e705c121SKalle Valo * size and some flags. 129e705c121SKalle Valo * Bit fields: 130e705c121SKalle Valo * 31: flag flush RB request 131e705c121SKalle Valo * 30: flag ignore TC (terminal counter) request 132e705c121SKalle Valo * 29: flag fast IRQ request 1339d0fc5a5SDavid Spinadel * 28-27: Reserved 1349d0fc5a5SDavid Spinadel * 26: RADA enabled 135fbe41127SSara Sharon * 25: Offload enabled 136ab2e696bSSara Sharon * 24: RPF enabled 137ab2e696bSSara Sharon * 23: RSS enabled 138ab2e696bSSara Sharon * 22: Checksum enabled 139ab2e696bSSara Sharon * 21-16: RX queue 140ab2e696bSSara Sharon * 15-14: Reserved 141e705c121SKalle Valo * 13-00: RX frame size 142e705c121SKalle Valo */ 143e705c121SKalle Valo __le32 len_n_flags; 144e705c121SKalle Valo struct iwl_cmd_header hdr; 145e705c121SKalle Valo u8 data[]; 146e705c121SKalle Valo } __packed; 147e705c121SKalle Valo 148e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 149e705c121SKalle Valo { 150e705c121SKalle Valo return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 151e705c121SKalle Valo } 152e705c121SKalle Valo 153e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 154e705c121SKalle Valo { 155e705c121SKalle Valo return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 156e705c121SKalle Valo } 157e705c121SKalle Valo 158e705c121SKalle Valo /** 159e705c121SKalle Valo * enum CMD_MODE - how to send the host commands ? 160e705c121SKalle Valo * 161e705c121SKalle Valo * @CMD_ASYNC: Return right away and don't wait for the response 162e705c121SKalle Valo * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 163e705c121SKalle Valo * the response. The caller needs to call iwl_free_resp when done. 164dcbb4746SEmmanuel Grumbach * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 165dcbb4746SEmmanuel Grumbach * called after this command completes. Valid only with CMD_ASYNC. 166e705c121SKalle Valo */ 167e705c121SKalle Valo enum CMD_MODE { 168e705c121SKalle Valo CMD_ASYNC = BIT(0), 169e705c121SKalle Valo CMD_WANT_SKB = BIT(1), 170e705c121SKalle Valo CMD_SEND_IN_RFKILL = BIT(2), 171043fa901SEmmanuel Grumbach CMD_WANT_ASYNC_CALLBACK = BIT(3), 172e705c121SKalle Valo }; 173e705c121SKalle Valo 174e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320 175e705c121SKalle Valo 176e705c121SKalle Valo /** 177e705c121SKalle Valo * struct iwl_device_cmd 178e705c121SKalle Valo * 179e705c121SKalle Valo * For allocation of the command and tx queues, this establishes the overall 180e705c121SKalle Valo * size of the largest command we send to uCode, except for commands that 181e705c121SKalle Valo * aren't fully copied and use other TFD space. 182e705c121SKalle Valo */ 183e705c121SKalle Valo struct iwl_device_cmd { 184e705c121SKalle Valo union { 185e705c121SKalle Valo struct { 186e705c121SKalle Valo struct iwl_cmd_header hdr; /* uCode API */ 187e705c121SKalle Valo u8 payload[DEF_CMD_PAYLOAD_SIZE]; 188e705c121SKalle Valo }; 189e705c121SKalle Valo struct { 190e705c121SKalle Valo struct iwl_cmd_header_wide hdr_wide; 191e705c121SKalle Valo u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 192e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide) + 193e705c121SKalle Valo sizeof(struct iwl_cmd_header)]; 194e705c121SKalle Valo }; 195e705c121SKalle Valo }; 196e705c121SKalle Valo } __packed; 197e705c121SKalle Valo 198a89c72ffSJohannes Berg /** 199a89c72ffSJohannes Berg * struct iwl_device_tx_cmd - buffer for TX command 200a89c72ffSJohannes Berg * @hdr: the header 201a89c72ffSJohannes Berg * @payload: the payload placeholder 202a89c72ffSJohannes Berg * 203a89c72ffSJohannes Berg * The actual structure is sized dynamically according to need. 204a89c72ffSJohannes Berg */ 205a89c72ffSJohannes Berg struct iwl_device_tx_cmd { 206a89c72ffSJohannes Berg struct iwl_cmd_header hdr; 207a89c72ffSJohannes Berg u8 payload[]; 208a89c72ffSJohannes Berg } __packed; 209a89c72ffSJohannes Berg 210e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 211e705c121SKalle Valo 212e705c121SKalle Valo /* 213e705c121SKalle Valo * number of transfer buffers (fragments) per transmit frame descriptor; 214e705c121SKalle Valo * this is just the driver's idea, the hardware supports 20 215e705c121SKalle Valo */ 216e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD 2 217e705c121SKalle Valo 218e705c121SKalle Valo /** 219b8aed81cSJohannes Berg * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 220e705c121SKalle Valo * 221e705c121SKalle Valo * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 222e705c121SKalle Valo * ring. The transport layer doesn't map the command's buffer to DMA, but 223e705c121SKalle Valo * rather copies it to a previously allocated DMA buffer. This flag tells 224e705c121SKalle Valo * the transport layer not to copy the command, but to map the existing 225e705c121SKalle Valo * buffer (that is passed in) instead. This saves the memcpy and allows 226e705c121SKalle Valo * commands that are bigger than the fixed buffer to be submitted. 227e705c121SKalle Valo * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 228e705c121SKalle Valo * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 229e705c121SKalle Valo * chunk internally and free it again after the command completes. This 230e705c121SKalle Valo * can (currently) be used only once per command. 231e705c121SKalle Valo * Note that a TFD entry after a DUP one cannot be a normal copied one. 232e705c121SKalle Valo */ 233e705c121SKalle Valo enum iwl_hcmd_dataflag { 234e705c121SKalle Valo IWL_HCMD_DFL_NOCOPY = BIT(0), 235e705c121SKalle Valo IWL_HCMD_DFL_DUP = BIT(1), 236e705c121SKalle Valo }; 237e705c121SKalle Valo 23822463857SShahar S Matityahu enum iwl_error_event_table_status { 23922463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 24022463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 24122463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 24222463857SShahar S Matityahu }; 24322463857SShahar S Matityahu 244e705c121SKalle Valo /** 245e705c121SKalle Valo * struct iwl_host_cmd - Host command to the uCode 246e705c121SKalle Valo * 247e705c121SKalle Valo * @data: array of chunks that composes the data of the host command 248e705c121SKalle Valo * @resp_pkt: response packet, if %CMD_WANT_SKB was set 249e705c121SKalle Valo * @_rx_page_order: (internally used to free response packet) 250e705c121SKalle Valo * @_rx_page_addr: (internally used to free response packet) 251e705c121SKalle Valo * @flags: can be CMD_* 252e705c121SKalle Valo * @len: array of the lengths of the chunks in data 253e705c121SKalle Valo * @dataflags: IWL_HCMD_DFL_* 254e705c121SKalle Valo * @id: command id of the host command, for wide commands encoding the 255e705c121SKalle Valo * version and group as well 256e705c121SKalle Valo */ 257e705c121SKalle Valo struct iwl_host_cmd { 258e705c121SKalle Valo const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 259e705c121SKalle Valo struct iwl_rx_packet *resp_pkt; 260e705c121SKalle Valo unsigned long _rx_page_addr; 261e705c121SKalle Valo u32 _rx_page_order; 262e705c121SKalle Valo 263e705c121SKalle Valo u32 flags; 264e705c121SKalle Valo u32 id; 265e705c121SKalle Valo u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 266e705c121SKalle Valo u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 267e705c121SKalle Valo }; 268e705c121SKalle Valo 269e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 270e705c121SKalle Valo { 271e705c121SKalle Valo free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 272e705c121SKalle Valo } 273e705c121SKalle Valo 274e705c121SKalle Valo struct iwl_rx_cmd_buffer { 275e705c121SKalle Valo struct page *_page; 276e705c121SKalle Valo int _offset; 277e705c121SKalle Valo bool _page_stolen; 278e705c121SKalle Valo u32 _rx_page_order; 279e705c121SKalle Valo unsigned int truesize; 280e705c121SKalle Valo }; 281e705c121SKalle Valo 282e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 283e705c121SKalle Valo { 284e705c121SKalle Valo return (void *)((unsigned long)page_address(r->_page) + r->_offset); 285e705c121SKalle Valo } 286e705c121SKalle Valo 287e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 288e705c121SKalle Valo { 289e705c121SKalle Valo return r->_offset; 290e705c121SKalle Valo } 291e705c121SKalle Valo 292e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 293e705c121SKalle Valo { 294e705c121SKalle Valo r->_page_stolen = true; 295e705c121SKalle Valo get_page(r->_page); 296e705c121SKalle Valo return r->_page; 297e705c121SKalle Valo } 298e705c121SKalle Valo 299e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 300e705c121SKalle Valo { 301e705c121SKalle Valo __free_pages(r->_page, r->_rx_page_order); 302e705c121SKalle Valo } 303e705c121SKalle Valo 304e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS 6 305e705c121SKalle Valo 306e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 307e705c121SKalle Valo 308e705c121SKalle Valo /* 309e705c121SKalle Valo * Maximum number of HW queues the transport layer 310e705c121SKalle Valo * currently supports 311e705c121SKalle Valo */ 312e705c121SKalle Valo #define IWL_MAX_HW_QUEUES 32 313e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES 512 314e982bc2cSSara Sharon 315e705c121SKalle Valo #define IWL_MAX_TID_COUNT 8 316c65f4e03SSara Sharon #define IWL_MGMT_TID 15 317e705c121SKalle Valo #define IWL_FRAME_LIMIT 64 318e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES 16 319e705c121SKalle Valo 320e705c121SKalle Valo /** 321e705c121SKalle Valo * enum iwl_wowlan_status - WoWLAN image/device status 322e705c121SKalle Valo * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 323e705c121SKalle Valo * @IWL_D3_STATUS_RESET: device was reset while suspended 324e705c121SKalle Valo */ 325e705c121SKalle Valo enum iwl_d3_status { 326e705c121SKalle Valo IWL_D3_STATUS_ALIVE, 327e705c121SKalle Valo IWL_D3_STATUS_RESET, 328e705c121SKalle Valo }; 329e705c121SKalle Valo 330e705c121SKalle Valo /** 331e705c121SKalle Valo * enum iwl_trans_status: transport status flags 332e705c121SKalle Valo * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 333e705c121SKalle Valo * @STATUS_DEVICE_ENABLED: APM is enabled 334e705c121SKalle Valo * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 335e705c121SKalle Valo * @STATUS_INT_ENABLED: interrupts are enabled 336326477e4SJohannes Berg * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 337326477e4SJohannes Berg * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 338e705c121SKalle Valo * @STATUS_FW_ERROR: the fw is in error state 339e705c121SKalle Valo * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 340e705c121SKalle Valo * are sent 341e705c121SKalle Valo * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 342e705c121SKalle Valo * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 343e705c121SKalle Valo */ 344e705c121SKalle Valo enum iwl_trans_status { 345e705c121SKalle Valo STATUS_SYNC_HCMD_ACTIVE, 346e705c121SKalle Valo STATUS_DEVICE_ENABLED, 347e705c121SKalle Valo STATUS_TPOWER_PMI, 348e705c121SKalle Valo STATUS_INT_ENABLED, 349326477e4SJohannes Berg STATUS_RFKILL_HW, 350326477e4SJohannes Berg STATUS_RFKILL_OPMODE, 351e705c121SKalle Valo STATUS_FW_ERROR, 352e705c121SKalle Valo STATUS_TRANS_GOING_IDLE, 353e705c121SKalle Valo STATUS_TRANS_IDLE, 354e705c121SKalle Valo STATUS_TRANS_DEAD, 355e705c121SKalle Valo }; 356e705c121SKalle Valo 3576c4fbcbcSEmmanuel Grumbach static inline int 3586c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 3596c4fbcbcSEmmanuel Grumbach { 3606c4fbcbcSEmmanuel Grumbach switch (rb_size) { 3611a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 3621a4968d1SGolan Ben Ami return get_order(2 * 1024); 3636c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 3646c4fbcbcSEmmanuel Grumbach return get_order(4 * 1024); 3656c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 3666c4fbcbcSEmmanuel Grumbach return get_order(8 * 1024); 3676c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 3686c4fbcbcSEmmanuel Grumbach return get_order(12 * 1024); 3696c4fbcbcSEmmanuel Grumbach default: 3706c4fbcbcSEmmanuel Grumbach WARN_ON(1); 3716c4fbcbcSEmmanuel Grumbach return -1; 3726c4fbcbcSEmmanuel Grumbach } 3736c4fbcbcSEmmanuel Grumbach } 3746c4fbcbcSEmmanuel Grumbach 37580084e35SJohannes Berg static inline int 37680084e35SJohannes Berg iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 37780084e35SJohannes Berg { 37880084e35SJohannes Berg switch (rb_size) { 37980084e35SJohannes Berg case IWL_AMSDU_2K: 38080084e35SJohannes Berg return 2 * 1024; 38180084e35SJohannes Berg case IWL_AMSDU_4K: 38280084e35SJohannes Berg return 4 * 1024; 38380084e35SJohannes Berg case IWL_AMSDU_8K: 38480084e35SJohannes Berg return 8 * 1024; 38580084e35SJohannes Berg case IWL_AMSDU_12K: 38680084e35SJohannes Berg return 12 * 1024; 38780084e35SJohannes Berg default: 38880084e35SJohannes Berg WARN_ON(1); 38980084e35SJohannes Berg return 0; 39080084e35SJohannes Berg } 39180084e35SJohannes Berg } 39280084e35SJohannes Berg 39339bdb17eSSharon Dvir struct iwl_hcmd_names { 39439bdb17eSSharon Dvir u8 cmd_id; 39539bdb17eSSharon Dvir const char *const cmd_name; 39639bdb17eSSharon Dvir }; 39739bdb17eSSharon Dvir 39839bdb17eSSharon Dvir #define HCMD_NAME(x) \ 39939bdb17eSSharon Dvir { .cmd_id = x, .cmd_name = #x } 40039bdb17eSSharon Dvir 40139bdb17eSSharon Dvir struct iwl_hcmd_arr { 40239bdb17eSSharon Dvir const struct iwl_hcmd_names *arr; 40339bdb17eSSharon Dvir int size; 40439bdb17eSSharon Dvir }; 40539bdb17eSSharon Dvir 40639bdb17eSSharon Dvir #define HCMD_ARR(x) \ 40739bdb17eSSharon Dvir { .arr = x, .size = ARRAY_SIZE(x) } 40839bdb17eSSharon Dvir 409e705c121SKalle Valo /** 410e705c121SKalle Valo * struct iwl_trans_config - transport configuration 411e705c121SKalle Valo * 412e705c121SKalle Valo * @op_mode: pointer to the upper layer. 413e705c121SKalle Valo * @cmd_queue: the index of the command queue. 414e705c121SKalle Valo * Must be set before start_fw. 415e705c121SKalle Valo * @cmd_fifo: the fifo for host commands 416e705c121SKalle Valo * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 417e705c121SKalle Valo * @no_reclaim_cmds: Some devices erroneously don't set the 418e705c121SKalle Valo * SEQ_RX_FRAME bit on some notifications, this is the 419e705c121SKalle Valo * list of such notifications to filter. Max length is 420e705c121SKalle Valo * %MAX_NO_RECLAIM_CMDS. 421e705c121SKalle Valo * @n_no_reclaim_cmds: # of commands in list 4226c4fbcbcSEmmanuel Grumbach * @rx_buf_size: RX buffer size needed for A-MSDUs 423e705c121SKalle Valo * if unset 4k will be the RX buffer size 424e705c121SKalle Valo * @bc_table_dword: set to true if the BC table expects the byte count to be 425e705c121SKalle Valo * in DWORD (as opposed to bytes) 426e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 42741837ca9SEmmanuel Grumbach * @sw_csum_tx: transport should compute the TCP checksum 42839bdb17eSSharon Dvir * @command_groups: array of command groups, each member is an array of the 42939bdb17eSSharon Dvir * commands in the group; for debugging only 43039bdb17eSSharon Dvir * @command_groups_size: number of command groups, to avoid illegal access 43121cb3222SJohannes Berg * @cb_data_offs: offset inside skb->cb to store transport data at, must have 43221cb3222SJohannes Berg * space for at least two pointers 433e705c121SKalle Valo */ 434e705c121SKalle Valo struct iwl_trans_config { 435e705c121SKalle Valo struct iwl_op_mode *op_mode; 436e705c121SKalle Valo 437e705c121SKalle Valo u8 cmd_queue; 438e705c121SKalle Valo u8 cmd_fifo; 439e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 440e705c121SKalle Valo const u8 *no_reclaim_cmds; 441e705c121SKalle Valo unsigned int n_no_reclaim_cmds; 442e705c121SKalle Valo 4436c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 444e705c121SKalle Valo bool bc_table_dword; 445e705c121SKalle Valo bool scd_set_active; 44641837ca9SEmmanuel Grumbach bool sw_csum_tx; 44739bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 44839bdb17eSSharon Dvir int command_groups_size; 449e705c121SKalle Valo 45021cb3222SJohannes Berg u8 cb_data_offs; 451e705c121SKalle Valo }; 452e705c121SKalle Valo 453e705c121SKalle Valo struct iwl_trans_dump_data { 454e705c121SKalle Valo u32 len; 455e705c121SKalle Valo u8 data[]; 456e705c121SKalle Valo }; 457e705c121SKalle Valo 458e705c121SKalle Valo struct iwl_trans; 459e705c121SKalle Valo 460e705c121SKalle Valo struct iwl_trans_txq_scd_cfg { 461e705c121SKalle Valo u8 fifo; 4622a2e9d10SLiad Kaufman u8 sta_id; 463e705c121SKalle Valo u8 tid; 464e705c121SKalle Valo bool aggregate; 465e705c121SKalle Valo int frame_limit; 466e705c121SKalle Valo }; 467e705c121SKalle Valo 4686b35ff91SSara Sharon /** 46992536c96SSara Sharon * struct iwl_trans_rxq_dma_data - RX queue DMA data 47092536c96SSara Sharon * @fr_bd_cb: DMA address of free BD cyclic buffer 47192536c96SSara Sharon * @fr_bd_wid: Initial write index of the free BD cyclic buffer 47292536c96SSara Sharon * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 47392536c96SSara Sharon * @ur_bd_cb: DMA address of used BD cyclic buffer 47492536c96SSara Sharon */ 47592536c96SSara Sharon struct iwl_trans_rxq_dma_data { 47692536c96SSara Sharon u64 fr_bd_cb; 47792536c96SSara Sharon u32 fr_bd_wid; 47892536c96SSara Sharon u64 urbd_stts_wrptr; 47992536c96SSara Sharon u64 ur_bd_cb; 48092536c96SSara Sharon }; 48192536c96SSara Sharon 48292536c96SSara Sharon /** 483e705c121SKalle Valo * struct iwl_trans_ops - transport specific operations 484e705c121SKalle Valo * 485e705c121SKalle Valo * All the handlers MUST be implemented 486e705c121SKalle Valo * 487bab3cb92SEmmanuel Grumbach * @start_hw: starts the HW. From that point on, the HW can send interrupts. 488bab3cb92SEmmanuel Grumbach * May sleep. 489e705c121SKalle Valo * @op_mode_leave: Turn off the HW RF kill indication if on 490e705c121SKalle Valo * May sleep 491e705c121SKalle Valo * @start_fw: allocates and inits all the resources for the transport 492e705c121SKalle Valo * layer. Also kick a fw image. 493e705c121SKalle Valo * May sleep 494e705c121SKalle Valo * @fw_alive: called when the fw sends alive notification. If the fw provides 495e705c121SKalle Valo * the SCD base address in SRAM, then provide it here, or 0 otherwise. 496e705c121SKalle Valo * May sleep 497e705c121SKalle Valo * @stop_device: stops the whole device (embedded CPU put to reset) and stops 498bab3cb92SEmmanuel Grumbach * the HW. From that point on, the HW will be stopped but will still issue 499bab3cb92SEmmanuel Grumbach * an interrupt if the HW RF kill switch is triggered. 500e705c121SKalle Valo * This callback must do the right thing and not crash even if %start_hw() 501e705c121SKalle Valo * was called but not &start_fw(). May sleep. 502e705c121SKalle Valo * @d3_suspend: put the device into the correct mode for WoWLAN during 503e705c121SKalle Valo * suspend. This is optional, if not implemented WoWLAN will not be 504e705c121SKalle Valo * supported. This callback may sleep. 505e705c121SKalle Valo * @d3_resume: resume the device after WoWLAN, enabling the opmode to 506e705c121SKalle Valo * talk to the WoWLAN image to get its status. This is optional, if not 507e705c121SKalle Valo * implemented WoWLAN will not be supported. This callback may sleep. 508e705c121SKalle Valo * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 509e705c121SKalle Valo * If RFkill is asserted in the middle of a SYNC host command, it must 510e705c121SKalle Valo * return -ERFKILL straight away. 511e705c121SKalle Valo * May sleep only if CMD_ASYNC is not set 5123f73b8caSEmmanuel Grumbach * @tx: send an skb. The transport relies on the op_mode to zero the 5136eb5e529SEmmanuel Grumbach * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 5146eb5e529SEmmanuel Grumbach * the CSUM will be taken care of (TCP CSUM and IP header in case of 5156eb5e529SEmmanuel Grumbach * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 5166eb5e529SEmmanuel Grumbach * header if it is IPv4. 517e705c121SKalle Valo * Must be atomic 518e705c121SKalle Valo * @reclaim: free packet until ssn. Returns a list of freed packets. 519e705c121SKalle Valo * Must be atomic 520e705c121SKalle Valo * @txq_enable: setup a queue. To setup an AC queue, use the 521e705c121SKalle Valo * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 522e705c121SKalle Valo * this one. The op_mode must not configure the HCMD queue. The scheduler 523e705c121SKalle Valo * configuration may be %NULL, in which case the hardware will not be 524dcfbd67bSEmmanuel Grumbach * configured. If true is returned, the operation mode needs to increment 525dcfbd67bSEmmanuel Grumbach * the sequence number of the packets routed to this queue because of a 526dcfbd67bSEmmanuel Grumbach * hardware scheduler bug. May sleep. 527e705c121SKalle Valo * @txq_disable: de-configure a Tx queue to send AMPDUs 528e705c121SKalle Valo * Must be atomic 52942db09c1SLiad Kaufman * @txq_set_shared_mode: change Tx queue shared/unshared marking 530d6d517b7SSara Sharon * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 531d6d517b7SSara Sharon * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 532e705c121SKalle Valo * @freeze_txq_timer: prevents the timer of the queue from firing until the 533e705c121SKalle Valo * queue is set to awake. Must be atomic. 5340cd58eaaSEmmanuel Grumbach * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 5350cd58eaaSEmmanuel Grumbach * that the transport needs to refcount the calls since this function 5360cd58eaaSEmmanuel Grumbach * will be called several times with block = true, and then the queues 5370cd58eaaSEmmanuel Grumbach * need to be unblocked only after the same number of calls with 5380cd58eaaSEmmanuel Grumbach * block = false. 539e705c121SKalle Valo * @write8: write a u8 to a register at offset ofs from the BAR 540e705c121SKalle Valo * @write32: write a u32 to a register at offset ofs from the BAR 541e705c121SKalle Valo * @read32: read a u32 register at offset ofs from the BAR 542e705c121SKalle Valo * @read_prph: read a DWORD from a periphery register 543e705c121SKalle Valo * @write_prph: write a DWORD to a periphery register 544e705c121SKalle Valo * @read_mem: read device's SRAM in DWORD 545e705c121SKalle Valo * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 546e705c121SKalle Valo * will be zeroed. 547f696a7eeSLuca Coelho * @read_config32: read a u32 value from the device's config space at 548f696a7eeSLuca Coelho * the given offset. 549e705c121SKalle Valo * @configure: configure parameters required by the transport layer from 550e705c121SKalle Valo * the op_mode. May be called several times before start_fw, can't be 551e705c121SKalle Valo * called after that. 552e705c121SKalle Valo * @set_pmi: set the power pmi state 553e705c121SKalle Valo * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 554e705c121SKalle Valo * Sleeping is not allowed between grab_nic_access and 555e705c121SKalle Valo * release_nic_access. 556e705c121SKalle Valo * @release_nic_access: let the NIC go to sleep. The "flags" parameter 557e705c121SKalle Valo * must be the same one that was sent before to the grab_nic_access. 558e705c121SKalle Valo * @set_bits_mask - set SRAM register according to value and mask. 559e705c121SKalle Valo * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 560e705c121SKalle Valo * TX'ed commands and similar. The buffer will be vfree'd by the caller. 561e705c121SKalle Valo * Note that the transport must fill in the proper file headers. 562f7805b33SLior Cohen * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 563f7805b33SLior Cohen * of the trans debugfs 564e705c121SKalle Valo */ 565e705c121SKalle Valo struct iwl_trans_ops { 566e705c121SKalle Valo 567bab3cb92SEmmanuel Grumbach int (*start_hw)(struct iwl_trans *iwl_trans); 568e705c121SKalle Valo void (*op_mode_leave)(struct iwl_trans *iwl_trans); 569e705c121SKalle Valo int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 570e705c121SKalle Valo bool run_in_rfkill); 571e705c121SKalle Valo void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 572bab3cb92SEmmanuel Grumbach void (*stop_device)(struct iwl_trans *trans); 573e705c121SKalle Valo 574e5f3f215SHaim Dreyfuss int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 575e705c121SKalle Valo int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 57623ae6128SMatti Gottlieb bool test, bool reset); 577e705c121SKalle Valo 578e705c121SKalle Valo int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 579e705c121SKalle Valo 580e705c121SKalle Valo int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 581a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue); 582e705c121SKalle Valo void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 583e705c121SKalle Valo struct sk_buff_head *skbs); 584e705c121SKalle Valo 585ba7136f3SAlex Malamud void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 586ba7136f3SAlex Malamud 587dcfbd67bSEmmanuel Grumbach bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 588e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 589e705c121SKalle Valo unsigned int queue_wdg_timeout); 590e705c121SKalle Valo void (*txq_disable)(struct iwl_trans *trans, int queue, 591e705c121SKalle Valo bool configure_scd); 5922f7a3863SLuca Coelho /* 22000 functions */ 5936b35ff91SSara Sharon int (*txq_alloc)(struct iwl_trans *trans, 5941169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 5955369774cSSara Sharon int cmd_id, int size, 5966b35ff91SSara Sharon unsigned int queue_wdg_timeout); 5976b35ff91SSara Sharon void (*txq_free)(struct iwl_trans *trans, int queue); 59892536c96SSara Sharon int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 59992536c96SSara Sharon struct iwl_trans_rxq_dma_data *data); 600e705c121SKalle Valo 60142db09c1SLiad Kaufman void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 60242db09c1SLiad Kaufman bool shared); 60342db09c1SLiad Kaufman 604a1a57877SSara Sharon int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 605d6d517b7SSara Sharon int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 606e705c121SKalle Valo void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 607e705c121SKalle Valo bool freeze); 6080cd58eaaSEmmanuel Grumbach void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 609e705c121SKalle Valo 610e705c121SKalle Valo void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 611e705c121SKalle Valo void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 612e705c121SKalle Valo u32 (*read32)(struct iwl_trans *trans, u32 ofs); 613e705c121SKalle Valo u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 614e705c121SKalle Valo void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 615e705c121SKalle Valo int (*read_mem)(struct iwl_trans *trans, u32 addr, 616e705c121SKalle Valo void *buf, int dwords); 617e705c121SKalle Valo int (*write_mem)(struct iwl_trans *trans, u32 addr, 618e705c121SKalle Valo const void *buf, int dwords); 619f696a7eeSLuca Coelho int (*read_config32)(struct iwl_trans *trans, u32 ofs, u32 *val); 620e705c121SKalle Valo void (*configure)(struct iwl_trans *trans, 621e705c121SKalle Valo const struct iwl_trans_config *trans_cfg); 622e705c121SKalle Valo void (*set_pmi)(struct iwl_trans *trans, bool state); 623870c2a11SGolan Ben Ami void (*sw_reset)(struct iwl_trans *trans); 62423ba9340SEmmanuel Grumbach bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags); 625e705c121SKalle Valo void (*release_nic_access)(struct iwl_trans *trans, 626e705c121SKalle Valo unsigned long *flags); 627e705c121SKalle Valo void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 628e705c121SKalle Valo u32 value); 629e705c121SKalle Valo int (*suspend)(struct iwl_trans *trans); 630e705c121SKalle Valo void (*resume)(struct iwl_trans *trans); 631e705c121SKalle Valo 632e705c121SKalle Valo struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 63379f033f6SSara Sharon u32 dump_mask); 634f7805b33SLior Cohen void (*debugfs_cleanup)(struct iwl_trans *trans); 635d1967ce6SShahar S Matityahu void (*sync_nmi)(struct iwl_trans *trans); 636e705c121SKalle Valo }; 637e705c121SKalle Valo 638e705c121SKalle Valo /** 639e705c121SKalle Valo * enum iwl_trans_state - state of the transport layer 640e705c121SKalle Valo * 641e705c121SKalle Valo * @IWL_TRANS_NO_FW: no fw has sent an alive response 642e705c121SKalle Valo * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response 643e705c121SKalle Valo */ 644e705c121SKalle Valo enum iwl_trans_state { 645e705c121SKalle Valo IWL_TRANS_NO_FW = 0, 646e705c121SKalle Valo IWL_TRANS_FW_ALIVE = 1, 647e705c121SKalle Valo }; 648e705c121SKalle Valo 649e705c121SKalle Valo /** 650b7282643SLuca Coelho * DOC: Platform power management 651e705c121SKalle Valo * 652b7282643SLuca Coelho * In system-wide power management the entire platform goes into a low 653b7282643SLuca Coelho * power state (e.g. idle or suspend to RAM) at the same time and the 654b7282643SLuca Coelho * device is configured as a wakeup source for the entire platform. 655b7282643SLuca Coelho * This is usually triggered by userspace activity (e.g. the user 656b7282643SLuca Coelho * presses the suspend button or a power management daemon decides to 657b7282643SLuca Coelho * put the platform in low power mode). The device's behavior in this 658b7282643SLuca Coelho * mode is dictated by the wake-on-WLAN configuration. 659b7282643SLuca Coelho * 660b7282643SLuca Coelho * The terms used for the device's behavior are as follows: 661b7282643SLuca Coelho * 662b7282643SLuca Coelho * - D0: the device is fully powered and the host is awake; 663b7282643SLuca Coelho * - D3: the device is in low power mode and only reacts to 664b7282643SLuca Coelho * specific events (e.g. magic-packet received or scan 665b7282643SLuca Coelho * results found); 666b7282643SLuca Coelho * 667b7282643SLuca Coelho * These terms reflect the power modes in the firmware and are not to 668f60e2750SEmmanuel Grumbach * be confused with the physical device power state. 669e705c121SKalle Valo */ 670b7282643SLuca Coelho 671b7282643SLuca Coelho /** 672b7282643SLuca Coelho * enum iwl_plat_pm_mode - platform power management mode 673b7282643SLuca Coelho * 674b7282643SLuca Coelho * This enumeration describes the device's platform power management 675f60e2750SEmmanuel Grumbach * behavior when in system-wide suspend (i.e WoWLAN). 676b7282643SLuca Coelho * 677b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 678f60e2750SEmmanuel Grumbach * device. In system-wide suspend mode, it means that the all 679f60e2750SEmmanuel Grumbach * connections will be closed automatically by mac80211 before 680f60e2750SEmmanuel Grumbach * the platform is suspended. 681b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 682b7282643SLuca Coelho */ 683b7282643SLuca Coelho enum iwl_plat_pm_mode { 684b7282643SLuca Coelho IWL_PLAT_PM_MODE_DISABLED, 685b7282643SLuca Coelho IWL_PLAT_PM_MODE_D3, 686e705c121SKalle Valo }; 687e705c121SKalle Valo 688341bd290SShahar S Matityahu /** 689341bd290SShahar S Matityahu * enum iwl_ini_cfg_state 690341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 691341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 692341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 693341bd290SShahar S Matityahu * are corrupted. The rest of the debug TLVs will still be used 694341bd290SShahar S Matityahu */ 695341bd290SShahar S Matityahu enum iwl_ini_cfg_state { 696341bd290SShahar S Matityahu IWL_INI_CFG_STATE_NOT_LOADED, 697341bd290SShahar S Matityahu IWL_INI_CFG_STATE_LOADED, 698341bd290SShahar S Matityahu IWL_INI_CFG_STATE_CORRUPTED, 699341bd290SShahar S Matityahu }; 700341bd290SShahar S Matityahu 701b8a7547dSShahar S Matityahu /* Max time to wait for nmi interrupt */ 702b8a7547dSShahar S Matityahu #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 703b8a7547dSShahar S Matityahu 70488964b2eSSara Sharon /** 70588964b2eSSara Sharon * struct iwl_dram_data 70688964b2eSSara Sharon * @physical: page phy pointer 70788964b2eSSara Sharon * @block: pointer to the allocated block/page 70888964b2eSSara Sharon * @size: size of the block/page 70988964b2eSSara Sharon */ 71088964b2eSSara Sharon struct iwl_dram_data { 71188964b2eSSara Sharon dma_addr_t physical; 71288964b2eSSara Sharon void *block; 71388964b2eSSara Sharon int size; 71488964b2eSSara Sharon }; 7154cbb8e50SLuciano Coelho 716e705c121SKalle Valo /** 717593fae3eSShahar S Matityahu * struct iwl_fw_mon - fw monitor per allocation id 718593fae3eSShahar S Matityahu * @num_frags: number of fragments 719593fae3eSShahar S Matityahu * @frags: an array of DRAM buffer fragments 720593fae3eSShahar S Matityahu */ 721593fae3eSShahar S Matityahu struct iwl_fw_mon { 722593fae3eSShahar S Matityahu u32 num_frags; 723593fae3eSShahar S Matityahu struct iwl_dram_data *frags; 724593fae3eSShahar S Matityahu }; 725593fae3eSShahar S Matityahu 726593fae3eSShahar S Matityahu /** 727505a00c0SShahar S Matityahu * struct iwl_self_init_dram - dram data used by self init process 728505a00c0SShahar S Matityahu * @fw: lmac and umac dram data 729505a00c0SShahar S Matityahu * @fw_cnt: total number of items in array 730505a00c0SShahar S Matityahu * @paging: paging dram data 731505a00c0SShahar S Matityahu * @paging_cnt: total number of items in array 732505a00c0SShahar S Matityahu */ 733505a00c0SShahar S Matityahu struct iwl_self_init_dram { 734505a00c0SShahar S Matityahu struct iwl_dram_data *fw; 735505a00c0SShahar S Matityahu int fw_cnt; 736505a00c0SShahar S Matityahu struct iwl_dram_data *paging; 737505a00c0SShahar S Matityahu int paging_cnt; 738505a00c0SShahar S Matityahu }; 739505a00c0SShahar S Matityahu 740505a00c0SShahar S Matityahu /** 74191c28b83SShahar S Matityahu * struct iwl_trans_debug - transport debug related data 74291c28b83SShahar S Matityahu * 74391c28b83SShahar S Matityahu * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 74491c28b83SShahar S Matityahu * @rec_on: true iff there is a fw debug recording currently active 74591c28b83SShahar S Matityahu * @dest_tlv: points to the destination TLV for debug 74691c28b83SShahar S Matityahu * @conf_tlv: array of pointers to configuration TLVs for debug 74791c28b83SShahar S Matityahu * @trigger_tlv: array of pointers to triggers TLVs for debug 74891c28b83SShahar S Matityahu * @lmac_error_event_table: addrs of lmacs error tables 74991c28b83SShahar S Matityahu * @umac_error_event_table: addr of umac error table 75091c28b83SShahar S Matityahu * @error_event_table_tlv_status: bitmap that indicates what error table 75191c28b83SShahar S Matityahu * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 752341bd290SShahar S Matityahu * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 753341bd290SShahar S Matityahu * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 754593fae3eSShahar S Matityahu * @fw_mon_cfg: debug buffer allocation configuration 755593fae3eSShahar S Matityahu * @fw_mon_ini: DRAM buffer fragments per allocation id 75669f0e505SShahar S Matityahu * @fw_mon: DRAM buffer for firmware monitor 75791c28b83SShahar S Matityahu * @hw_error: equals true if hw error interrupt was received from the FW 758029c25f3SShahar S Matityahu * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 7593b589d56SShahar S Matityahu * @active_regions: active regions 760677d25b2SShahar S Matityahu * @debug_info_tlv_list: list of debug info TLVs 761a9248de4SShahar S Matityahu * @time_point: array of debug time points 76260e8abd9SShahar S Matityahu * @periodic_trig_list: periodic triggers list 763cf29c5b6SShahar S Matityahu * @domains_bitmap: bitmap of active domains other than 764cf29c5b6SShahar S Matityahu * &IWL_FW_INI_DOMAIN_ALWAYS_ON 76591c28b83SShahar S Matityahu */ 76691c28b83SShahar S Matityahu struct iwl_trans_debug { 76791c28b83SShahar S Matityahu u8 n_dest_reg; 76891c28b83SShahar S Matityahu bool rec_on; 76991c28b83SShahar S Matityahu 77091c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 77191c28b83SShahar S Matityahu const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 77291c28b83SShahar S Matityahu struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 77391c28b83SShahar S Matityahu 77491c28b83SShahar S Matityahu u32 lmac_error_event_table[2]; 77591c28b83SShahar S Matityahu u32 umac_error_event_table; 77691c28b83SShahar S Matityahu unsigned int error_event_table_tlv_status; 77791c28b83SShahar S Matityahu 778341bd290SShahar S Matityahu enum iwl_ini_cfg_state internal_ini_cfg; 779341bd290SShahar S Matityahu enum iwl_ini_cfg_state external_ini_cfg; 78091c28b83SShahar S Matityahu 781593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 782593fae3eSShahar S Matityahu struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 783593fae3eSShahar S Matityahu 78469f0e505SShahar S Matityahu struct iwl_dram_data fw_mon; 78591c28b83SShahar S Matityahu 78691c28b83SShahar S Matityahu bool hw_error; 787029c25f3SShahar S Matityahu enum iwl_fw_ini_buffer_location ini_dest; 7883b589d56SShahar S Matityahu 7893b589d56SShahar S Matityahu struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 790677d25b2SShahar S Matityahu struct list_head debug_info_tlv_list; 791a9248de4SShahar S Matityahu struct iwl_dbg_tlv_time_point_data 792a9248de4SShahar S Matityahu time_point[IWL_FW_INI_TIME_POINT_NUM]; 79360e8abd9SShahar S Matityahu struct list_head periodic_trig_list; 794cf29c5b6SShahar S Matityahu 795cf29c5b6SShahar S Matityahu u32 domains_bitmap; 79691c28b83SShahar S Matityahu }; 79791c28b83SShahar S Matityahu 7984807e736SMordechay Goodstein struct iwl_dma_ptr { 7994807e736SMordechay Goodstein dma_addr_t dma; 8004807e736SMordechay Goodstein void *addr; 8014807e736SMordechay Goodstein size_t size; 8024807e736SMordechay Goodstein }; 8034807e736SMordechay Goodstein 8044807e736SMordechay Goodstein struct iwl_cmd_meta { 8054807e736SMordechay Goodstein /* only for SYNC commands, iff the reply skb is wanted */ 8064807e736SMordechay Goodstein struct iwl_host_cmd *source; 8074807e736SMordechay Goodstein u32 flags; 8084807e736SMordechay Goodstein u32 tbs; 8094807e736SMordechay Goodstein }; 8104807e736SMordechay Goodstein 8114807e736SMordechay Goodstein /* 8124807e736SMordechay Goodstein * The FH will write back to the first TB only, so we need to copy some data 8134807e736SMordechay Goodstein * into the buffer regardless of whether it should be mapped or not. 8144807e736SMordechay Goodstein * This indicates how big the first TB must be to include the scratch buffer 8154807e736SMordechay Goodstein * and the assigned PN. 8164807e736SMordechay Goodstein * Since PN location is 8 bytes at offset 12, it's 20 now. 8174807e736SMordechay Goodstein * If we make it bigger then allocations will be bigger and copy slower, so 8184807e736SMordechay Goodstein * that's probably not useful. 8194807e736SMordechay Goodstein */ 8204807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE 20 8214807e736SMordechay Goodstein #define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 8224807e736SMordechay Goodstein 8234807e736SMordechay Goodstein struct iwl_pcie_txq_entry { 8244807e736SMordechay Goodstein void *cmd; 8254807e736SMordechay Goodstein struct sk_buff *skb; 8264807e736SMordechay Goodstein /* buffer to free after command completes */ 8274807e736SMordechay Goodstein const void *free_buf; 8284807e736SMordechay Goodstein struct iwl_cmd_meta meta; 8294807e736SMordechay Goodstein }; 8304807e736SMordechay Goodstein 8314807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf { 8324807e736SMordechay Goodstein u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 8334807e736SMordechay Goodstein }; 8344807e736SMordechay Goodstein 8354807e736SMordechay Goodstein /** 8364807e736SMordechay Goodstein * struct iwl_txq - Tx Queue for DMA 8374807e736SMordechay Goodstein * @q: generic Rx/Tx queue descriptor 8384807e736SMordechay Goodstein * @tfds: transmit frame descriptors (DMA memory) 8394807e736SMordechay Goodstein * @first_tb_bufs: start of command headers, including scratch buffers, for 8404807e736SMordechay Goodstein * the writeback -- this is DMA memory and an array holding one buffer 8414807e736SMordechay Goodstein * for each command on the queue 8424807e736SMordechay Goodstein * @first_tb_dma: DMA address for the first_tb_bufs start 8434807e736SMordechay Goodstein * @entries: transmit entries (driver state) 8444807e736SMordechay Goodstein * @lock: queue lock 8454807e736SMordechay Goodstein * @stuck_timer: timer that fires if queue gets stuck 8464807e736SMordechay Goodstein * @trans: pointer back to transport (for timer) 8474807e736SMordechay Goodstein * @need_update: indicates need to update read/write index 8484807e736SMordechay Goodstein * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 8494807e736SMordechay Goodstein * @wd_timeout: queue watchdog timeout (jiffies) - per queue 8504807e736SMordechay Goodstein * @frozen: tx stuck queue timer is frozen 8514807e736SMordechay Goodstein * @frozen_expiry_remainder: remember how long until the timer fires 8524807e736SMordechay Goodstein * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 8534807e736SMordechay Goodstein * @write_ptr: 1-st empty entry (index) host_w 8544807e736SMordechay Goodstein * @read_ptr: last used entry (index) host_r 8554807e736SMordechay Goodstein * @dma_addr: physical addr for BD's 8564807e736SMordechay Goodstein * @n_window: safe queue window 8574807e736SMordechay Goodstein * @id: queue id 8584807e736SMordechay Goodstein * @low_mark: low watermark, resume queue if free space more than this 8594807e736SMordechay Goodstein * @high_mark: high watermark, stop queue if free space less than this 8604807e736SMordechay Goodstein * 8614807e736SMordechay Goodstein * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 8624807e736SMordechay Goodstein * descriptors) and required locking structures. 8634807e736SMordechay Goodstein * 8644807e736SMordechay Goodstein * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 8654807e736SMordechay Goodstein * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 8664807e736SMordechay Goodstein * there might be HW changes in the future). For the normal TX 8674807e736SMordechay Goodstein * queues, n_window, which is the size of the software queue data 8684807e736SMordechay Goodstein * is also 256; however, for the command queue, n_window is only 8694807e736SMordechay Goodstein * 32 since we don't need so many commands pending. Since the HW 8704807e736SMordechay Goodstein * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 8714807e736SMordechay Goodstein * This means that we end up with the following: 8724807e736SMordechay Goodstein * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 8734807e736SMordechay Goodstein * SW entries: | 0 | ... | 31 | 8744807e736SMordechay Goodstein * where N is a number between 0 and 7. This means that the SW 8754807e736SMordechay Goodstein * data is a window overlayed over the HW queue. 8764807e736SMordechay Goodstein */ 8774807e736SMordechay Goodstein struct iwl_txq { 8784807e736SMordechay Goodstein void *tfds; 8794807e736SMordechay Goodstein struct iwl_pcie_first_tb_buf *first_tb_bufs; 8804807e736SMordechay Goodstein dma_addr_t first_tb_dma; 8814807e736SMordechay Goodstein struct iwl_pcie_txq_entry *entries; 8824807e736SMordechay Goodstein /* lock for syncing changes on the queue */ 8834807e736SMordechay Goodstein spinlock_t lock; 8844807e736SMordechay Goodstein unsigned long frozen_expiry_remainder; 8854807e736SMordechay Goodstein struct timer_list stuck_timer; 8864807e736SMordechay Goodstein struct iwl_trans *trans; 8874807e736SMordechay Goodstein bool need_update; 8884807e736SMordechay Goodstein bool frozen; 8894807e736SMordechay Goodstein bool ampdu; 8904807e736SMordechay Goodstein int block; 8914807e736SMordechay Goodstein unsigned long wd_timeout; 8924807e736SMordechay Goodstein struct sk_buff_head overflow_q; 8934807e736SMordechay Goodstein struct iwl_dma_ptr bc_tbl; 8944807e736SMordechay Goodstein 8954807e736SMordechay Goodstein int write_ptr; 8964807e736SMordechay Goodstein int read_ptr; 8974807e736SMordechay Goodstein dma_addr_t dma_addr; 8984807e736SMordechay Goodstein int n_window; 8994807e736SMordechay Goodstein u32 id; 9004807e736SMordechay Goodstein int low_mark; 9014807e736SMordechay Goodstein int high_mark; 9024807e736SMordechay Goodstein 9034807e736SMordechay Goodstein bool overflow_tx; 9044807e736SMordechay Goodstein }; 90591c28b83SShahar S Matityahu /** 906e705c121SKalle Valo * struct iwl_trans - transport common data 907e705c121SKalle Valo * 908e705c121SKalle Valo * @ops - pointer to iwl_trans_ops 909e705c121SKalle Valo * @op_mode - pointer to the op_mode 910286ca8ebSLuca Coelho * @trans_cfg: the trans-specific configuration part 911e705c121SKalle Valo * @cfg - pointer to the configuration 9126f482e37SSara Sharon * @drv - pointer to iwl_drv 913e705c121SKalle Valo * @status: a bit-mask of transport status flags 914e705c121SKalle Valo * @dev - pointer to struct device * that represents the device 915e705c121SKalle Valo * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 916e705c121SKalle Valo * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 9171afb0ae4SHaim Dreyfuss * @hw_rf_id a u32 with the device RF ID 918e705c121SKalle Valo * @hw_id: a u32 with the ID of the device / sub-device. 919e705c121SKalle Valo * Set during transport allocation. 920e705c121SKalle Valo * @hw_id_str: a string with info about HW ID. Set during transport allocation. 921e705c121SKalle Valo * @pm_support: set to true in start_hw if link pm is supported 922e705c121SKalle Valo * @ltr_enabled: set to true if the LTR is enabled 9235b88792cSSara Sharon * @wide_cmd_header: true when ucode supports wide command header format 924e705c121SKalle Valo * @num_rx_queues: number of RX queues allocated by the transport; 925e705c121SKalle Valo * the transport must set this before calling iwl_drv_start() 926132db31cSGolan Ben-Ami * @iml_len: the length of the image loader 927132db31cSGolan Ben-Ami * @iml: a pointer to the image loader itself 928e705c121SKalle Valo * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 929e705c121SKalle Valo * The user should use iwl_trans_{alloc,free}_tx_cmd. 930e705c121SKalle Valo * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 931e705c121SKalle Valo * starting the firmware, used for tracing 932e705c121SKalle Valo * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 933e705c121SKalle Valo * start of the 802.11 header in the @rx_mpdu_cmd 934e705c121SKalle Valo * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 935b7282643SLuca Coelho * @system_pm_mode: the system-wide power management mode in use. 936b7282643SLuca Coelho * This mode is set dynamically, depending on the WoWLAN values 937b7282643SLuca Coelho * configured from the userspace at runtime. 938e705c121SKalle Valo */ 939e705c121SKalle Valo struct iwl_trans { 940e705c121SKalle Valo const struct iwl_trans_ops *ops; 941e705c121SKalle Valo struct iwl_op_mode *op_mode; 942286ca8ebSLuca Coelho const struct iwl_cfg_trans_params *trans_cfg; 943e705c121SKalle Valo const struct iwl_cfg *cfg; 9446f482e37SSara Sharon struct iwl_drv *drv; 945e705c121SKalle Valo enum iwl_trans_state state; 946e705c121SKalle Valo unsigned long status; 947e705c121SKalle Valo 948e705c121SKalle Valo struct device *dev; 949e705c121SKalle Valo u32 max_skb_frags; 950e705c121SKalle Valo u32 hw_rev; 9511afb0ae4SHaim Dreyfuss u32 hw_rf_id; 952e705c121SKalle Valo u32 hw_id; 953e705c121SKalle Valo char hw_id_str[52]; 954e705c121SKalle Valo 955e705c121SKalle Valo u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 956e705c121SKalle Valo 957e705c121SKalle Valo bool pm_support; 958e705c121SKalle Valo bool ltr_enabled; 959e705c121SKalle Valo 96039bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 96139bdb17eSSharon Dvir int command_groups_size; 9625b88792cSSara Sharon bool wide_cmd_header; 96339bdb17eSSharon Dvir 964e705c121SKalle Valo u8 num_rx_queues; 965e705c121SKalle Valo 966132db31cSGolan Ben-Ami size_t iml_len; 967132db31cSGolan Ben-Ami u8 *iml; 968132db31cSGolan Ben-Ami 969e705c121SKalle Valo /* The following fields are internal only */ 970e705c121SKalle Valo struct kmem_cache *dev_cmd_pool; 971e705c121SKalle Valo char dev_cmd_pool_name[50]; 972e705c121SKalle Valo 973e705c121SKalle Valo struct dentry *dbgfs_dir; 974e705c121SKalle Valo 975e705c121SKalle Valo #ifdef CONFIG_LOCKDEP 976e705c121SKalle Valo struct lockdep_map sync_cmd_lockdep_map; 977e705c121SKalle Valo #endif 978e705c121SKalle Valo 97991c28b83SShahar S Matityahu struct iwl_trans_debug dbg; 980505a00c0SShahar S Matityahu struct iwl_self_init_dram init_dram; 981e705c121SKalle Valo 982b7282643SLuca Coelho enum iwl_plat_pm_mode system_pm_mode; 983700b3799SShahar S Matityahu 9840b295a1eSLuca Coelho const char *name; 9850b295a1eSLuca Coelho 986e705c121SKalle Valo /* pointer to trans specific struct */ 987e705c121SKalle Valo /*Ensure that this pointer will always be aligned to sizeof pointer */ 988e705c121SKalle Valo char trans_specific[0] __aligned(sizeof(void *)); 989e705c121SKalle Valo }; 990e705c121SKalle Valo 99139bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 99239bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 99339bdb17eSSharon Dvir 994e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans, 995e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 996e705c121SKalle Valo { 997e705c121SKalle Valo trans->op_mode = trans_cfg->op_mode; 998e705c121SKalle Valo 999e705c121SKalle Valo trans->ops->configure(trans, trans_cfg); 100039bdb17eSSharon Dvir WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 1001e705c121SKalle Valo } 1002e705c121SKalle Valo 1003bab3cb92SEmmanuel Grumbach static inline int iwl_trans_start_hw(struct iwl_trans *trans) 1004e705c121SKalle Valo { 1005e705c121SKalle Valo might_sleep(); 1006e705c121SKalle Valo 1007bab3cb92SEmmanuel Grumbach return trans->ops->start_hw(trans); 1008e705c121SKalle Valo } 1009e705c121SKalle Valo 1010e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 1011e705c121SKalle Valo { 1012e705c121SKalle Valo might_sleep(); 1013e705c121SKalle Valo 1014e705c121SKalle Valo if (trans->ops->op_mode_leave) 1015e705c121SKalle Valo trans->ops->op_mode_leave(trans); 1016e705c121SKalle Valo 1017e705c121SKalle Valo trans->op_mode = NULL; 1018e705c121SKalle Valo 1019e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1020e705c121SKalle Valo } 1021e705c121SKalle Valo 1022e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1023e705c121SKalle Valo { 1024e705c121SKalle Valo might_sleep(); 1025e705c121SKalle Valo 1026e705c121SKalle Valo trans->state = IWL_TRANS_FW_ALIVE; 1027e705c121SKalle Valo 1028e705c121SKalle Valo trans->ops->fw_alive(trans, scd_addr); 1029e705c121SKalle Valo } 1030e705c121SKalle Valo 1031e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans, 1032e705c121SKalle Valo const struct fw_img *fw, 1033e705c121SKalle Valo bool run_in_rfkill) 1034e705c121SKalle Valo { 1035e705c121SKalle Valo might_sleep(); 1036e705c121SKalle Valo 1037e705c121SKalle Valo WARN_ON_ONCE(!trans->rx_mpdu_cmd); 1038e705c121SKalle Valo 1039e705c121SKalle Valo clear_bit(STATUS_FW_ERROR, &trans->status); 1040e705c121SKalle Valo return trans->ops->start_fw(trans, fw, run_in_rfkill); 1041e705c121SKalle Valo } 1042e705c121SKalle Valo 1043bab3cb92SEmmanuel Grumbach static inline void iwl_trans_stop_device(struct iwl_trans *trans) 1044e705c121SKalle Valo { 1045e705c121SKalle Valo might_sleep(); 1046e705c121SKalle Valo 1047bab3cb92SEmmanuel Grumbach trans->ops->stop_device(trans); 1048e705c121SKalle Valo 1049e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 1050e705c121SKalle Valo } 1051e705c121SKalle Valo 1052e5f3f215SHaim Dreyfuss static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 105323ae6128SMatti Gottlieb bool reset) 1054e705c121SKalle Valo { 1055e705c121SKalle Valo might_sleep(); 1056e5f3f215SHaim Dreyfuss if (!trans->ops->d3_suspend) 1057e5f3f215SHaim Dreyfuss return 0; 1058e5f3f215SHaim Dreyfuss 1059e5f3f215SHaim Dreyfuss return trans->ops->d3_suspend(trans, test, reset); 1060e705c121SKalle Valo } 1061e705c121SKalle Valo 1062e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 1063e705c121SKalle Valo enum iwl_d3_status *status, 106423ae6128SMatti Gottlieb bool test, bool reset) 1065e705c121SKalle Valo { 1066e705c121SKalle Valo might_sleep(); 1067e705c121SKalle Valo if (!trans->ops->d3_resume) 1068e705c121SKalle Valo return 0; 1069e705c121SKalle Valo 107023ae6128SMatti Gottlieb return trans->ops->d3_resume(trans, status, test, reset); 1071e705c121SKalle Valo } 1072e705c121SKalle Valo 1073e705c121SKalle Valo static inline int iwl_trans_suspend(struct iwl_trans *trans) 1074e705c121SKalle Valo { 1075e705c121SKalle Valo if (!trans->ops->suspend) 1076e705c121SKalle Valo return 0; 1077e705c121SKalle Valo 1078e705c121SKalle Valo return trans->ops->suspend(trans); 1079e705c121SKalle Valo } 1080e705c121SKalle Valo 1081e705c121SKalle Valo static inline void iwl_trans_resume(struct iwl_trans *trans) 1082e705c121SKalle Valo { 1083e705c121SKalle Valo if (trans->ops->resume) 1084e705c121SKalle Valo trans->ops->resume(trans); 1085e705c121SKalle Valo } 1086e705c121SKalle Valo 1087e705c121SKalle Valo static inline struct iwl_trans_dump_data * 108879f033f6SSara Sharon iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask) 1089e705c121SKalle Valo { 1090e705c121SKalle Valo if (!trans->ops->dump_data) 1091e705c121SKalle Valo return NULL; 109279f033f6SSara Sharon return trans->ops->dump_data(trans, dump_mask); 1093e705c121SKalle Valo } 1094e705c121SKalle Valo 1095a89c72ffSJohannes Berg static inline struct iwl_device_tx_cmd * 1096e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 1097e705c121SKalle Valo { 1098a89c72ffSJohannes Berg return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC); 1099e705c121SKalle Valo } 1100e705c121SKalle Valo 110192fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 110292fe8343SEmmanuel Grumbach 1103e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 1104a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd) 1105e705c121SKalle Valo { 11061ea423b0SLuca Coelho kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 1107e705c121SKalle Valo } 1108e705c121SKalle Valo 1109e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 1110a89c72ffSJohannes Berg struct iwl_device_tx_cmd *dev_cmd, int queue) 1111e705c121SKalle Valo { 1112e705c121SKalle Valo if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 1113e705c121SKalle Valo return -EIO; 1114e705c121SKalle Valo 1115e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1116e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1117e5d15cb5SEliad Peller return -EIO; 1118e5d15cb5SEliad Peller } 1119e705c121SKalle Valo 1120e705c121SKalle Valo return trans->ops->tx(trans, skb, dev_cmd, queue); 1121e705c121SKalle Valo } 1122e705c121SKalle Valo 1123e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1124e705c121SKalle Valo int ssn, struct sk_buff_head *skbs) 1125e705c121SKalle Valo { 1126e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1127e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1128e5d15cb5SEliad Peller return; 1129e5d15cb5SEliad Peller } 1130e705c121SKalle Valo 1131e705c121SKalle Valo trans->ops->reclaim(trans, queue, ssn, skbs); 1132e705c121SKalle Valo } 1133e705c121SKalle Valo 1134ba7136f3SAlex Malamud static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1135ba7136f3SAlex Malamud int ptr) 1136ba7136f3SAlex Malamud { 1137ba7136f3SAlex Malamud if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1138ba7136f3SAlex Malamud IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1139ba7136f3SAlex Malamud return; 1140ba7136f3SAlex Malamud } 1141ba7136f3SAlex Malamud 1142ba7136f3SAlex Malamud trans->ops->set_q_ptrs(trans, queue, ptr); 1143ba7136f3SAlex Malamud } 1144ba7136f3SAlex Malamud 1145e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1146e705c121SKalle Valo bool configure_scd) 1147e705c121SKalle Valo { 1148e705c121SKalle Valo trans->ops->txq_disable(trans, queue, configure_scd); 1149e705c121SKalle Valo } 1150e705c121SKalle Valo 1151dcfbd67bSEmmanuel Grumbach static inline bool 1152e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1153e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1154e705c121SKalle Valo unsigned int queue_wdg_timeout) 1155e705c121SKalle Valo { 1156e705c121SKalle Valo might_sleep(); 1157e705c121SKalle Valo 1158e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1159e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1160dcfbd67bSEmmanuel Grumbach return false; 1161e5d15cb5SEliad Peller } 1162e705c121SKalle Valo 1163dcfbd67bSEmmanuel Grumbach return trans->ops->txq_enable(trans, queue, ssn, 1164dcfbd67bSEmmanuel Grumbach cfg, queue_wdg_timeout); 1165e705c121SKalle Valo } 1166e705c121SKalle Valo 116792536c96SSara Sharon static inline int 116892536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 116992536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 117092536c96SSara Sharon { 117192536c96SSara Sharon if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 117292536c96SSara Sharon return -ENOTSUPP; 117392536c96SSara Sharon 117492536c96SSara Sharon return trans->ops->rxq_dma_data(trans, queue, data); 117592536c96SSara Sharon } 117692536c96SSara Sharon 11776b35ff91SSara Sharon static inline void 11786b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue) 11796b35ff91SSara Sharon { 11806b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_free)) 11816b35ff91SSara Sharon return; 11826b35ff91SSara Sharon 11836b35ff91SSara Sharon trans->ops->txq_free(trans, queue); 11846b35ff91SSara Sharon } 11856b35ff91SSara Sharon 11866b35ff91SSara Sharon static inline int 11876b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans, 11881169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 11895369774cSSara Sharon int cmd_id, int size, 11905369774cSSara Sharon unsigned int wdg_timeout) 11916b35ff91SSara Sharon { 11926b35ff91SSara Sharon might_sleep(); 11936b35ff91SSara Sharon 11946b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 11956b35ff91SSara Sharon return -ENOTSUPP; 11966b35ff91SSara Sharon 11976b35ff91SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 11986b35ff91SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 11996b35ff91SSara Sharon return -EIO; 12006b35ff91SSara Sharon } 12016b35ff91SSara Sharon 12021169310fSGolan Ben Ami return trans->ops->txq_alloc(trans, flags, sta_id, tid, 12031169310fSGolan Ben Ami cmd_id, size, wdg_timeout); 12046b35ff91SSara Sharon } 12056b35ff91SSara Sharon 120642db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 120742db09c1SLiad Kaufman int queue, bool shared_mode) 120842db09c1SLiad Kaufman { 120942db09c1SLiad Kaufman if (trans->ops->txq_set_shared_mode) 121042db09c1SLiad Kaufman trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 121142db09c1SLiad Kaufman } 121242db09c1SLiad Kaufman 1213e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1214e705c121SKalle Valo int fifo, int sta_id, int tid, 1215e705c121SKalle Valo int frame_limit, u16 ssn, 1216e705c121SKalle Valo unsigned int queue_wdg_timeout) 1217e705c121SKalle Valo { 1218e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1219e705c121SKalle Valo .fifo = fifo, 1220e705c121SKalle Valo .sta_id = sta_id, 1221e705c121SKalle Valo .tid = tid, 1222e705c121SKalle Valo .frame_limit = frame_limit, 1223e705c121SKalle Valo .aggregate = sta_id >= 0, 1224e705c121SKalle Valo }; 1225e705c121SKalle Valo 1226e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1227e705c121SKalle Valo } 1228e705c121SKalle Valo 1229e705c121SKalle Valo static inline 1230e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1231e705c121SKalle Valo unsigned int queue_wdg_timeout) 1232e705c121SKalle Valo { 1233e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1234e705c121SKalle Valo .fifo = fifo, 1235e705c121SKalle Valo .sta_id = -1, 1236e705c121SKalle Valo .tid = IWL_MAX_TID_COUNT, 1237e705c121SKalle Valo .frame_limit = IWL_FRAME_LIMIT, 1238e705c121SKalle Valo .aggregate = false, 1239e705c121SKalle Valo }; 1240e705c121SKalle Valo 1241e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1242e705c121SKalle Valo } 1243e705c121SKalle Valo 1244e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1245e705c121SKalle Valo unsigned long txqs, 1246e705c121SKalle Valo bool freeze) 1247e705c121SKalle Valo { 1248e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1249e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1250e5d15cb5SEliad Peller return; 1251e5d15cb5SEliad Peller } 1252e705c121SKalle Valo 1253e705c121SKalle Valo if (trans->ops->freeze_txq_timer) 1254e705c121SKalle Valo trans->ops->freeze_txq_timer(trans, txqs, freeze); 1255e705c121SKalle Valo } 1256e705c121SKalle Valo 12570cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 12580cd58eaaSEmmanuel Grumbach bool block) 12590cd58eaaSEmmanuel Grumbach { 1260e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 12610cd58eaaSEmmanuel Grumbach IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1262e5d15cb5SEliad Peller return; 1263e5d15cb5SEliad Peller } 12640cd58eaaSEmmanuel Grumbach 12650cd58eaaSEmmanuel Grumbach if (trans->ops->block_txq_ptrs) 12660cd58eaaSEmmanuel Grumbach trans->ops->block_txq_ptrs(trans, block); 12670cd58eaaSEmmanuel Grumbach } 12680cd58eaaSEmmanuel Grumbach 1269a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1270e705c121SKalle Valo u32 txqs) 1271e705c121SKalle Valo { 1272d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1273d6d517b7SSara Sharon return -ENOTSUPP; 1274d6d517b7SSara Sharon 1275e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1276e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1277e5d15cb5SEliad Peller return -EIO; 1278e5d15cb5SEliad Peller } 1279e705c121SKalle Valo 1280a1a57877SSara Sharon return trans->ops->wait_tx_queues_empty(trans, txqs); 1281e705c121SKalle Valo } 1282e705c121SKalle Valo 1283d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1284d6d517b7SSara Sharon { 1285d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1286d6d517b7SSara Sharon return -ENOTSUPP; 1287d6d517b7SSara Sharon 1288d6d517b7SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1289d6d517b7SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1290d6d517b7SSara Sharon return -EIO; 1291d6d517b7SSara Sharon } 1292d6d517b7SSara Sharon 1293d6d517b7SSara Sharon return trans->ops->wait_txq_empty(trans, queue); 1294d6d517b7SSara Sharon } 1295d6d517b7SSara Sharon 1296e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1297e705c121SKalle Valo { 1298e705c121SKalle Valo trans->ops->write8(trans, ofs, val); 1299e705c121SKalle Valo } 1300e705c121SKalle Valo 1301e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1302e705c121SKalle Valo { 1303e705c121SKalle Valo trans->ops->write32(trans, ofs, val); 1304e705c121SKalle Valo } 1305e705c121SKalle Valo 1306e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1307e705c121SKalle Valo { 1308e705c121SKalle Valo return trans->ops->read32(trans, ofs); 1309e705c121SKalle Valo } 1310e705c121SKalle Valo 1311e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1312e705c121SKalle Valo { 1313e705c121SKalle Valo return trans->ops->read_prph(trans, ofs); 1314e705c121SKalle Valo } 1315e705c121SKalle Valo 1316e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1317e705c121SKalle Valo u32 val) 1318e705c121SKalle Valo { 1319e705c121SKalle Valo return trans->ops->write_prph(trans, ofs, val); 1320e705c121SKalle Valo } 1321e705c121SKalle Valo 1322e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1323e705c121SKalle Valo void *buf, int dwords) 1324e705c121SKalle Valo { 1325e705c121SKalle Valo return trans->ops->read_mem(trans, addr, buf, dwords); 1326e705c121SKalle Valo } 1327e705c121SKalle Valo 1328e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1329e705c121SKalle Valo do { \ 1330e705c121SKalle Valo if (__builtin_constant_p(bufsize)) \ 1331e705c121SKalle Valo BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1332e705c121SKalle Valo iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1333e705c121SKalle Valo } while (0) 1334e705c121SKalle Valo 1335e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1336e705c121SKalle Valo { 1337e705c121SKalle Valo u32 value; 1338e705c121SKalle Valo 1339e705c121SKalle Valo if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1340e705c121SKalle Valo return 0xa5a5a5a5; 1341e705c121SKalle Valo 1342e705c121SKalle Valo return value; 1343e705c121SKalle Valo } 1344e705c121SKalle Valo 1345e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1346e705c121SKalle Valo const void *buf, int dwords) 1347e705c121SKalle Valo { 1348e705c121SKalle Valo return trans->ops->write_mem(trans, addr, buf, dwords); 1349e705c121SKalle Valo } 1350e705c121SKalle Valo 1351e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1352e705c121SKalle Valo u32 val) 1353e705c121SKalle Valo { 1354e705c121SKalle Valo return iwl_trans_write_mem(trans, addr, &val, 1); 1355e705c121SKalle Valo } 1356e705c121SKalle Valo 1357e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1358e705c121SKalle Valo { 1359e705c121SKalle Valo if (trans->ops->set_pmi) 1360e705c121SKalle Valo trans->ops->set_pmi(trans, state); 1361e705c121SKalle Valo } 1362e705c121SKalle Valo 1363870c2a11SGolan Ben Ami static inline void iwl_trans_sw_reset(struct iwl_trans *trans) 1364870c2a11SGolan Ben Ami { 1365870c2a11SGolan Ben Ami if (trans->ops->sw_reset) 1366870c2a11SGolan Ben Ami trans->ops->sw_reset(trans); 1367870c2a11SGolan Ben Ami } 1368870c2a11SGolan Ben Ami 1369e705c121SKalle Valo static inline void 1370e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1371e705c121SKalle Valo { 1372e705c121SKalle Valo trans->ops->set_bits_mask(trans, reg, mask, value); 1373e705c121SKalle Valo } 1374e705c121SKalle Valo 137523ba9340SEmmanuel Grumbach #define iwl_trans_grab_nic_access(trans, flags) \ 1376e705c121SKalle Valo __cond_lock(nic_access, \ 137723ba9340SEmmanuel Grumbach likely((trans)->ops->grab_nic_access(trans, flags))) 1378e705c121SKalle Valo 1379e705c121SKalle Valo static inline void __releases(nic_access) 1380e705c121SKalle Valo iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) 1381e705c121SKalle Valo { 1382e705c121SKalle Valo trans->ops->release_nic_access(trans, flags); 1383e705c121SKalle Valo __release(nic_access); 1384e705c121SKalle Valo } 1385e705c121SKalle Valo 1386e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans) 1387e705c121SKalle Valo { 1388e705c121SKalle Valo if (WARN_ON_ONCE(!trans->op_mode)) 1389e705c121SKalle Valo return; 1390e705c121SKalle Valo 1391e705c121SKalle Valo /* prevent double restarts due to the same erroneous FW */ 1392e705c121SKalle Valo if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) 1393e705c121SKalle Valo iwl_op_mode_nic_error(trans->op_mode); 1394e705c121SKalle Valo } 1395e705c121SKalle Valo 1396068893b7SShahar S Matityahu static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1397068893b7SShahar S Matityahu { 1398068893b7SShahar S Matityahu return trans->state == IWL_TRANS_FW_ALIVE; 1399068893b7SShahar S Matityahu } 1400068893b7SShahar S Matityahu 1401d1967ce6SShahar S Matityahu static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1402d1967ce6SShahar S Matityahu { 1403d1967ce6SShahar S Matityahu if (trans->ops->sync_nmi) 1404d1967ce6SShahar S Matityahu trans->ops->sync_nmi(trans); 1405d1967ce6SShahar S Matityahu } 1406d1967ce6SShahar S Matityahu 1407a1af4c48SShahar S Matityahu static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1408a1af4c48SShahar S Matityahu { 1409341bd290SShahar S Matityahu return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1410341bd290SShahar S Matityahu trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1411a1af4c48SShahar S Matityahu } 1412a1af4c48SShahar S Matityahu 1413e705c121SKalle Valo /***************************************************** 1414e705c121SKalle Valo * transport helper functions 1415e705c121SKalle Valo *****************************************************/ 1416e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1417e705c121SKalle Valo struct device *dev, 1418a89c72ffSJohannes Berg const struct iwl_trans_ops *ops, 1419a89c72ffSJohannes Berg unsigned int cmd_pool_size, 1420a89c72ffSJohannes Berg unsigned int cmd_pool_align); 1421e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans); 1422e705c121SKalle Valo 1423e705c121SKalle Valo /***************************************************** 1424e705c121SKalle Valo * driver (transport) register/unregister functions 1425e705c121SKalle Valo ******************************************************/ 1426e705c121SKalle Valo int __must_check iwl_pci_register_driver(void); 1427e705c121SKalle Valo void iwl_pci_unregister_driver(void); 1428e705c121SKalle Valo 1429e705c121SKalle Valo #endif /* __iwl_trans_h__ */ 1430