1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 106b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 336b35ff91SSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34700b3799SShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #ifndef __iwl_trans_h__ 65e705c121SKalle Valo #define __iwl_trans_h__ 66e705c121SKalle Valo 67e705c121SKalle Valo #include <linux/ieee80211.h> 68e705c121SKalle Valo #include <linux/mm.h> /* for page_address */ 69e705c121SKalle Valo #include <linux/lockdep.h> 7039bdb17eSSharon Dvir #include <linux/kernel.h> 71e705c121SKalle Valo 72e705c121SKalle Valo #include "iwl-debug.h" 73e705c121SKalle Valo #include "iwl-config.h" 74d962f9b1SJohannes Berg #include "fw/img.h" 75e705c121SKalle Valo #include "iwl-op-mode.h" 76d172a5efSJohannes Berg #include "fw/api/cmdhdr.h" 77d172a5efSJohannes Berg #include "fw/api/txq.h" 78f14cda6fSSara Sharon #include "fw/api/dbg-tlv.h" 79f14cda6fSSara Sharon #include "iwl-dbg-tlv.h" 80e705c121SKalle Valo 81e705c121SKalle Valo /** 82e705c121SKalle Valo * DOC: Transport layer - what is it ? 83e705c121SKalle Valo * 84e705c121SKalle Valo * The transport layer is the layer that deals with the HW directly. It provides 85e705c121SKalle Valo * an abstraction of the underlying HW to the upper layer. The transport layer 86e705c121SKalle Valo * doesn't provide any policy, algorithm or anything of this kind, but only 87e705c121SKalle Valo * mechanisms to make the HW do something. It is not completely stateless but 88e705c121SKalle Valo * close to it. 89e705c121SKalle Valo * We will have an implementation for each different supported bus. 90e705c121SKalle Valo */ 91e705c121SKalle Valo 92e705c121SKalle Valo /** 93e705c121SKalle Valo * DOC: Life cycle of the transport layer 94e705c121SKalle Valo * 95e705c121SKalle Valo * The transport layer has a very precise life cycle. 96e705c121SKalle Valo * 97e705c121SKalle Valo * 1) A helper function is called during the module initialization and 98e705c121SKalle Valo * registers the bus driver's ops with the transport's alloc function. 99e705c121SKalle Valo * 2) Bus's probe calls to the transport layer's allocation functions. 100e705c121SKalle Valo * Of course this function is bus specific. 101e705c121SKalle Valo * 3) This allocation functions will spawn the upper layer which will 102e705c121SKalle Valo * register mac80211. 103e705c121SKalle Valo * 104e705c121SKalle Valo * 4) At some point (i.e. mac80211's start call), the op_mode will call 105e705c121SKalle Valo * the following sequence: 106e705c121SKalle Valo * start_hw 107e705c121SKalle Valo * start_fw 108e705c121SKalle Valo * 109e705c121SKalle Valo * 5) Then when finished (or reset): 110e705c121SKalle Valo * stop_device 111e705c121SKalle Valo * 112e705c121SKalle Valo * 6) Eventually, the free function will be called. 113e705c121SKalle Valo */ 114e705c121SKalle Valo 115e701da0cSLuca Coelho #define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 116e701da0cSLuca Coelho 117e705c121SKalle Valo #define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 118e705c121SKalle Valo #define FH_RSCSR_FRAME_INVALID 0x55550000 119e705c121SKalle Valo #define FH_RSCSR_FRAME_ALIGN 0x40 120fbe41127SSara Sharon #define FH_RSCSR_RPA_EN BIT(25) 1219d0fc5a5SDavid Spinadel #define FH_RSCSR_RADA_EN BIT(26) 122ab2e696bSSara Sharon #define FH_RSCSR_RXQ_POS 16 123ab2e696bSSara Sharon #define FH_RSCSR_RXQ_MASK 0x3F0000 124e705c121SKalle Valo 125e705c121SKalle Valo struct iwl_rx_packet { 126e705c121SKalle Valo /* 127e705c121SKalle Valo * The first 4 bytes of the RX frame header contain both the RX frame 128e705c121SKalle Valo * size and some flags. 129e705c121SKalle Valo * Bit fields: 130e705c121SKalle Valo * 31: flag flush RB request 131e705c121SKalle Valo * 30: flag ignore TC (terminal counter) request 132e705c121SKalle Valo * 29: flag fast IRQ request 1339d0fc5a5SDavid Spinadel * 28-27: Reserved 1349d0fc5a5SDavid Spinadel * 26: RADA enabled 135fbe41127SSara Sharon * 25: Offload enabled 136ab2e696bSSara Sharon * 24: RPF enabled 137ab2e696bSSara Sharon * 23: RSS enabled 138ab2e696bSSara Sharon * 22: Checksum enabled 139ab2e696bSSara Sharon * 21-16: RX queue 140ab2e696bSSara Sharon * 15-14: Reserved 141e705c121SKalle Valo * 13-00: RX frame size 142e705c121SKalle Valo */ 143e705c121SKalle Valo __le32 len_n_flags; 144e705c121SKalle Valo struct iwl_cmd_header hdr; 145e705c121SKalle Valo u8 data[]; 146e705c121SKalle Valo } __packed; 147e705c121SKalle Valo 148e705c121SKalle Valo static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 149e705c121SKalle Valo { 150e705c121SKalle Valo return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 151e705c121SKalle Valo } 152e705c121SKalle Valo 153e705c121SKalle Valo static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 154e705c121SKalle Valo { 155e705c121SKalle Valo return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 156e705c121SKalle Valo } 157e705c121SKalle Valo 158e705c121SKalle Valo /** 159e705c121SKalle Valo * enum CMD_MODE - how to send the host commands ? 160e705c121SKalle Valo * 161e705c121SKalle Valo * @CMD_ASYNC: Return right away and don't wait for the response 162e705c121SKalle Valo * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 163e705c121SKalle Valo * the response. The caller needs to call iwl_free_resp when done. 164dcbb4746SEmmanuel Grumbach * @CMD_WANT_ASYNC_CALLBACK: the op_mode's async callback function must be 165dcbb4746SEmmanuel Grumbach * called after this command completes. Valid only with CMD_ASYNC. 166e705c121SKalle Valo */ 167e705c121SKalle Valo enum CMD_MODE { 168e705c121SKalle Valo CMD_ASYNC = BIT(0), 169e705c121SKalle Valo CMD_WANT_SKB = BIT(1), 170e705c121SKalle Valo CMD_SEND_IN_RFKILL = BIT(2), 171043fa901SEmmanuel Grumbach CMD_WANT_ASYNC_CALLBACK = BIT(3), 172e705c121SKalle Valo }; 173e705c121SKalle Valo 174e705c121SKalle Valo #define DEF_CMD_PAYLOAD_SIZE 320 175e705c121SKalle Valo 176e705c121SKalle Valo /** 177e705c121SKalle Valo * struct iwl_device_cmd 178e705c121SKalle Valo * 179e705c121SKalle Valo * For allocation of the command and tx queues, this establishes the overall 180e705c121SKalle Valo * size of the largest command we send to uCode, except for commands that 181e705c121SKalle Valo * aren't fully copied and use other TFD space. 182e705c121SKalle Valo */ 183e705c121SKalle Valo struct iwl_device_cmd { 184e705c121SKalle Valo union { 185e705c121SKalle Valo struct { 186e705c121SKalle Valo struct iwl_cmd_header hdr; /* uCode API */ 187e705c121SKalle Valo u8 payload[DEF_CMD_PAYLOAD_SIZE]; 188e705c121SKalle Valo }; 189e705c121SKalle Valo struct { 190e705c121SKalle Valo struct iwl_cmd_header_wide hdr_wide; 191e705c121SKalle Valo u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 192e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide) + 193e705c121SKalle Valo sizeof(struct iwl_cmd_header)]; 194e705c121SKalle Valo }; 195e705c121SKalle Valo }; 196e705c121SKalle Valo } __packed; 197e705c121SKalle Valo 198e705c121SKalle Valo #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 199e705c121SKalle Valo 200e705c121SKalle Valo /* 201e705c121SKalle Valo * number of transfer buffers (fragments) per transmit frame descriptor; 202e705c121SKalle Valo * this is just the driver's idea, the hardware supports 20 203e705c121SKalle Valo */ 204e705c121SKalle Valo #define IWL_MAX_CMD_TBS_PER_TFD 2 205e705c121SKalle Valo 206e705c121SKalle Valo /** 207b8aed81cSJohannes Berg * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 208e705c121SKalle Valo * 209e705c121SKalle Valo * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 210e705c121SKalle Valo * ring. The transport layer doesn't map the command's buffer to DMA, but 211e705c121SKalle Valo * rather copies it to a previously allocated DMA buffer. This flag tells 212e705c121SKalle Valo * the transport layer not to copy the command, but to map the existing 213e705c121SKalle Valo * buffer (that is passed in) instead. This saves the memcpy and allows 214e705c121SKalle Valo * commands that are bigger than the fixed buffer to be submitted. 215e705c121SKalle Valo * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 216e705c121SKalle Valo * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 217e705c121SKalle Valo * chunk internally and free it again after the command completes. This 218e705c121SKalle Valo * can (currently) be used only once per command. 219e705c121SKalle Valo * Note that a TFD entry after a DUP one cannot be a normal copied one. 220e705c121SKalle Valo */ 221e705c121SKalle Valo enum iwl_hcmd_dataflag { 222e705c121SKalle Valo IWL_HCMD_DFL_NOCOPY = BIT(0), 223e705c121SKalle Valo IWL_HCMD_DFL_DUP = BIT(1), 224e705c121SKalle Valo }; 225e705c121SKalle Valo 22622463857SShahar S Matityahu enum iwl_error_event_table_status { 22722463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 22822463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 22922463857SShahar S Matityahu IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 23022463857SShahar S Matityahu }; 23122463857SShahar S Matityahu 232e705c121SKalle Valo /** 233e705c121SKalle Valo * struct iwl_host_cmd - Host command to the uCode 234e705c121SKalle Valo * 235e705c121SKalle Valo * @data: array of chunks that composes the data of the host command 236e705c121SKalle Valo * @resp_pkt: response packet, if %CMD_WANT_SKB was set 237e705c121SKalle Valo * @_rx_page_order: (internally used to free response packet) 238e705c121SKalle Valo * @_rx_page_addr: (internally used to free response packet) 239e705c121SKalle Valo * @flags: can be CMD_* 240e705c121SKalle Valo * @len: array of the lengths of the chunks in data 241e705c121SKalle Valo * @dataflags: IWL_HCMD_DFL_* 242e705c121SKalle Valo * @id: command id of the host command, for wide commands encoding the 243e705c121SKalle Valo * version and group as well 244e705c121SKalle Valo */ 245e705c121SKalle Valo struct iwl_host_cmd { 246e705c121SKalle Valo const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 247e705c121SKalle Valo struct iwl_rx_packet *resp_pkt; 248e705c121SKalle Valo unsigned long _rx_page_addr; 249e705c121SKalle Valo u32 _rx_page_order; 250e705c121SKalle Valo 251e705c121SKalle Valo u32 flags; 252e705c121SKalle Valo u32 id; 253e705c121SKalle Valo u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 254e705c121SKalle Valo u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 255e705c121SKalle Valo }; 256e705c121SKalle Valo 257e705c121SKalle Valo static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 258e705c121SKalle Valo { 259e705c121SKalle Valo free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 260e705c121SKalle Valo } 261e705c121SKalle Valo 262e705c121SKalle Valo struct iwl_rx_cmd_buffer { 263e705c121SKalle Valo struct page *_page; 264e705c121SKalle Valo int _offset; 265e705c121SKalle Valo bool _page_stolen; 266e705c121SKalle Valo u32 _rx_page_order; 267e705c121SKalle Valo unsigned int truesize; 268e705c121SKalle Valo }; 269e705c121SKalle Valo 270e705c121SKalle Valo static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 271e705c121SKalle Valo { 272e705c121SKalle Valo return (void *)((unsigned long)page_address(r->_page) + r->_offset); 273e705c121SKalle Valo } 274e705c121SKalle Valo 275e705c121SKalle Valo static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 276e705c121SKalle Valo { 277e705c121SKalle Valo return r->_offset; 278e705c121SKalle Valo } 279e705c121SKalle Valo 280e705c121SKalle Valo static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 281e705c121SKalle Valo { 282e705c121SKalle Valo r->_page_stolen = true; 283e705c121SKalle Valo get_page(r->_page); 284e705c121SKalle Valo return r->_page; 285e705c121SKalle Valo } 286e705c121SKalle Valo 287e705c121SKalle Valo static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 288e705c121SKalle Valo { 289e705c121SKalle Valo __free_pages(r->_page, r->_rx_page_order); 290e705c121SKalle Valo } 291e705c121SKalle Valo 292e705c121SKalle Valo #define MAX_NO_RECLAIM_CMDS 6 293e705c121SKalle Valo 294e705c121SKalle Valo #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 295e705c121SKalle Valo 296e705c121SKalle Valo /* 297e705c121SKalle Valo * Maximum number of HW queues the transport layer 298e705c121SKalle Valo * currently supports 299e705c121SKalle Valo */ 300e705c121SKalle Valo #define IWL_MAX_HW_QUEUES 32 301e982bc2cSSara Sharon #define IWL_MAX_TVQM_QUEUES 512 302e982bc2cSSara Sharon 303e705c121SKalle Valo #define IWL_MAX_TID_COUNT 8 304c65f4e03SSara Sharon #define IWL_MGMT_TID 15 305e705c121SKalle Valo #define IWL_FRAME_LIMIT 64 306e705c121SKalle Valo #define IWL_MAX_RX_HW_QUEUES 16 307e705c121SKalle Valo 308e705c121SKalle Valo /** 309e705c121SKalle Valo * enum iwl_wowlan_status - WoWLAN image/device status 310e705c121SKalle Valo * @IWL_D3_STATUS_ALIVE: firmware is still running after resume 311e705c121SKalle Valo * @IWL_D3_STATUS_RESET: device was reset while suspended 312e705c121SKalle Valo */ 313e705c121SKalle Valo enum iwl_d3_status { 314e705c121SKalle Valo IWL_D3_STATUS_ALIVE, 315e705c121SKalle Valo IWL_D3_STATUS_RESET, 316e705c121SKalle Valo }; 317e705c121SKalle Valo 318e705c121SKalle Valo /** 319e705c121SKalle Valo * enum iwl_trans_status: transport status flags 320e705c121SKalle Valo * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 321e705c121SKalle Valo * @STATUS_DEVICE_ENABLED: APM is enabled 322e705c121SKalle Valo * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 323e705c121SKalle Valo * @STATUS_INT_ENABLED: interrupts are enabled 324326477e4SJohannes Berg * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 325326477e4SJohannes Berg * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 326e705c121SKalle Valo * @STATUS_FW_ERROR: the fw is in error state 327e705c121SKalle Valo * @STATUS_TRANS_GOING_IDLE: shutting down the trans, only special commands 328e705c121SKalle Valo * are sent 329e705c121SKalle Valo * @STATUS_TRANS_IDLE: the trans is idle - general commands are not to be sent 330e705c121SKalle Valo * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 331e705c121SKalle Valo */ 332e705c121SKalle Valo enum iwl_trans_status { 333e705c121SKalle Valo STATUS_SYNC_HCMD_ACTIVE, 334e705c121SKalle Valo STATUS_DEVICE_ENABLED, 335e705c121SKalle Valo STATUS_TPOWER_PMI, 336e705c121SKalle Valo STATUS_INT_ENABLED, 337326477e4SJohannes Berg STATUS_RFKILL_HW, 338326477e4SJohannes Berg STATUS_RFKILL_OPMODE, 339e705c121SKalle Valo STATUS_FW_ERROR, 340e705c121SKalle Valo STATUS_TRANS_GOING_IDLE, 341e705c121SKalle Valo STATUS_TRANS_IDLE, 342e705c121SKalle Valo STATUS_TRANS_DEAD, 343e705c121SKalle Valo }; 344e705c121SKalle Valo 3456c4fbcbcSEmmanuel Grumbach static inline int 3466c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 3476c4fbcbcSEmmanuel Grumbach { 3486c4fbcbcSEmmanuel Grumbach switch (rb_size) { 3491a4968d1SGolan Ben Ami case IWL_AMSDU_2K: 3501a4968d1SGolan Ben Ami return get_order(2 * 1024); 3516c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_4K: 3526c4fbcbcSEmmanuel Grumbach return get_order(4 * 1024); 3536c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_8K: 3546c4fbcbcSEmmanuel Grumbach return get_order(8 * 1024); 3556c4fbcbcSEmmanuel Grumbach case IWL_AMSDU_12K: 3566c4fbcbcSEmmanuel Grumbach return get_order(12 * 1024); 3576c4fbcbcSEmmanuel Grumbach default: 3586c4fbcbcSEmmanuel Grumbach WARN_ON(1); 3596c4fbcbcSEmmanuel Grumbach return -1; 3606c4fbcbcSEmmanuel Grumbach } 3616c4fbcbcSEmmanuel Grumbach } 3626c4fbcbcSEmmanuel Grumbach 36380084e35SJohannes Berg static inline int 36480084e35SJohannes Berg iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 36580084e35SJohannes Berg { 36680084e35SJohannes Berg switch (rb_size) { 36780084e35SJohannes Berg case IWL_AMSDU_2K: 36880084e35SJohannes Berg return 2 * 1024; 36980084e35SJohannes Berg case IWL_AMSDU_4K: 37080084e35SJohannes Berg return 4 * 1024; 37180084e35SJohannes Berg case IWL_AMSDU_8K: 37280084e35SJohannes Berg return 8 * 1024; 37380084e35SJohannes Berg case IWL_AMSDU_12K: 37480084e35SJohannes Berg return 12 * 1024; 37580084e35SJohannes Berg default: 37680084e35SJohannes Berg WARN_ON(1); 37780084e35SJohannes Berg return 0; 37880084e35SJohannes Berg } 37980084e35SJohannes Berg } 38080084e35SJohannes Berg 38139bdb17eSSharon Dvir struct iwl_hcmd_names { 38239bdb17eSSharon Dvir u8 cmd_id; 38339bdb17eSSharon Dvir const char *const cmd_name; 38439bdb17eSSharon Dvir }; 38539bdb17eSSharon Dvir 38639bdb17eSSharon Dvir #define HCMD_NAME(x) \ 38739bdb17eSSharon Dvir { .cmd_id = x, .cmd_name = #x } 38839bdb17eSSharon Dvir 38939bdb17eSSharon Dvir struct iwl_hcmd_arr { 39039bdb17eSSharon Dvir const struct iwl_hcmd_names *arr; 39139bdb17eSSharon Dvir int size; 39239bdb17eSSharon Dvir }; 39339bdb17eSSharon Dvir 39439bdb17eSSharon Dvir #define HCMD_ARR(x) \ 39539bdb17eSSharon Dvir { .arr = x, .size = ARRAY_SIZE(x) } 39639bdb17eSSharon Dvir 397e705c121SKalle Valo /** 398e705c121SKalle Valo * struct iwl_trans_config - transport configuration 399e705c121SKalle Valo * 400e705c121SKalle Valo * @op_mode: pointer to the upper layer. 401e705c121SKalle Valo * @cmd_queue: the index of the command queue. 402e705c121SKalle Valo * Must be set before start_fw. 403e705c121SKalle Valo * @cmd_fifo: the fifo for host commands 404e705c121SKalle Valo * @cmd_q_wdg_timeout: the timeout of the watchdog timer for the command queue. 405e705c121SKalle Valo * @no_reclaim_cmds: Some devices erroneously don't set the 406e705c121SKalle Valo * SEQ_RX_FRAME bit on some notifications, this is the 407e705c121SKalle Valo * list of such notifications to filter. Max length is 408e705c121SKalle Valo * %MAX_NO_RECLAIM_CMDS. 409e705c121SKalle Valo * @n_no_reclaim_cmds: # of commands in list 4106c4fbcbcSEmmanuel Grumbach * @rx_buf_size: RX buffer size needed for A-MSDUs 411e705c121SKalle Valo * if unset 4k will be the RX buffer size 412e705c121SKalle Valo * @bc_table_dword: set to true if the BC table expects the byte count to be 413e705c121SKalle Valo * in DWORD (as opposed to bytes) 414e705c121SKalle Valo * @scd_set_active: should the transport configure the SCD for HCMD queue 41541837ca9SEmmanuel Grumbach * @sw_csum_tx: transport should compute the TCP checksum 41639bdb17eSSharon Dvir * @command_groups: array of command groups, each member is an array of the 41739bdb17eSSharon Dvir * commands in the group; for debugging only 41839bdb17eSSharon Dvir * @command_groups_size: number of command groups, to avoid illegal access 41921cb3222SJohannes Berg * @cb_data_offs: offset inside skb->cb to store transport data at, must have 42021cb3222SJohannes Berg * space for at least two pointers 421e705c121SKalle Valo */ 422e705c121SKalle Valo struct iwl_trans_config { 423e705c121SKalle Valo struct iwl_op_mode *op_mode; 424e705c121SKalle Valo 425e705c121SKalle Valo u8 cmd_queue; 426e705c121SKalle Valo u8 cmd_fifo; 427e705c121SKalle Valo unsigned int cmd_q_wdg_timeout; 428e705c121SKalle Valo const u8 *no_reclaim_cmds; 429e705c121SKalle Valo unsigned int n_no_reclaim_cmds; 430e705c121SKalle Valo 4316c4fbcbcSEmmanuel Grumbach enum iwl_amsdu_size rx_buf_size; 432e705c121SKalle Valo bool bc_table_dword; 433e705c121SKalle Valo bool scd_set_active; 43441837ca9SEmmanuel Grumbach bool sw_csum_tx; 43539bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 43639bdb17eSSharon Dvir int command_groups_size; 437e705c121SKalle Valo 43821cb3222SJohannes Berg u8 cb_data_offs; 439e705c121SKalle Valo }; 440e705c121SKalle Valo 441e705c121SKalle Valo struct iwl_trans_dump_data { 442e705c121SKalle Valo u32 len; 443e705c121SKalle Valo u8 data[]; 444e705c121SKalle Valo }; 445e705c121SKalle Valo 446e705c121SKalle Valo struct iwl_trans; 447e705c121SKalle Valo 448e705c121SKalle Valo struct iwl_trans_txq_scd_cfg { 449e705c121SKalle Valo u8 fifo; 4502a2e9d10SLiad Kaufman u8 sta_id; 451e705c121SKalle Valo u8 tid; 452e705c121SKalle Valo bool aggregate; 453e705c121SKalle Valo int frame_limit; 454e705c121SKalle Valo }; 455e705c121SKalle Valo 4566b35ff91SSara Sharon /** 45792536c96SSara Sharon * struct iwl_trans_rxq_dma_data - RX queue DMA data 45892536c96SSara Sharon * @fr_bd_cb: DMA address of free BD cyclic buffer 45992536c96SSara Sharon * @fr_bd_wid: Initial write index of the free BD cyclic buffer 46092536c96SSara Sharon * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 46192536c96SSara Sharon * @ur_bd_cb: DMA address of used BD cyclic buffer 46292536c96SSara Sharon */ 46392536c96SSara Sharon struct iwl_trans_rxq_dma_data { 46492536c96SSara Sharon u64 fr_bd_cb; 46592536c96SSara Sharon u32 fr_bd_wid; 46692536c96SSara Sharon u64 urbd_stts_wrptr; 46792536c96SSara Sharon u64 ur_bd_cb; 46892536c96SSara Sharon }; 46992536c96SSara Sharon 47092536c96SSara Sharon /** 471e705c121SKalle Valo * struct iwl_trans_ops - transport specific operations 472e705c121SKalle Valo * 473e705c121SKalle Valo * All the handlers MUST be implemented 474e705c121SKalle Valo * 475bab3cb92SEmmanuel Grumbach * @start_hw: starts the HW. From that point on, the HW can send interrupts. 476bab3cb92SEmmanuel Grumbach * May sleep. 477e705c121SKalle Valo * @op_mode_leave: Turn off the HW RF kill indication if on 478e705c121SKalle Valo * May sleep 479e705c121SKalle Valo * @start_fw: allocates and inits all the resources for the transport 480e705c121SKalle Valo * layer. Also kick a fw image. 481e705c121SKalle Valo * May sleep 482e705c121SKalle Valo * @fw_alive: called when the fw sends alive notification. If the fw provides 483e705c121SKalle Valo * the SCD base address in SRAM, then provide it here, or 0 otherwise. 484e705c121SKalle Valo * May sleep 485e705c121SKalle Valo * @stop_device: stops the whole device (embedded CPU put to reset) and stops 486bab3cb92SEmmanuel Grumbach * the HW. From that point on, the HW will be stopped but will still issue 487bab3cb92SEmmanuel Grumbach * an interrupt if the HW RF kill switch is triggered. 488e705c121SKalle Valo * This callback must do the right thing and not crash even if %start_hw() 489e705c121SKalle Valo * was called but not &start_fw(). May sleep. 490e705c121SKalle Valo * @d3_suspend: put the device into the correct mode for WoWLAN during 491e705c121SKalle Valo * suspend. This is optional, if not implemented WoWLAN will not be 492e705c121SKalle Valo * supported. This callback may sleep. 493e705c121SKalle Valo * @d3_resume: resume the device after WoWLAN, enabling the opmode to 494e705c121SKalle Valo * talk to the WoWLAN image to get its status. This is optional, if not 495e705c121SKalle Valo * implemented WoWLAN will not be supported. This callback may sleep. 496e705c121SKalle Valo * @send_cmd:send a host command. Must return -ERFKILL if RFkill is asserted. 497e705c121SKalle Valo * If RFkill is asserted in the middle of a SYNC host command, it must 498e705c121SKalle Valo * return -ERFKILL straight away. 499e705c121SKalle Valo * May sleep only if CMD_ASYNC is not set 5003f73b8caSEmmanuel Grumbach * @tx: send an skb. The transport relies on the op_mode to zero the 5016eb5e529SEmmanuel Grumbach * the ieee80211_tx_info->driver_data. If the MPDU is an A-MSDU, all 5026eb5e529SEmmanuel Grumbach * the CSUM will be taken care of (TCP CSUM and IP header in case of 5036eb5e529SEmmanuel Grumbach * IPv4). If the MPDU is a single MSDU, the op_mode must compute the IP 5046eb5e529SEmmanuel Grumbach * header if it is IPv4. 505e705c121SKalle Valo * Must be atomic 506e705c121SKalle Valo * @reclaim: free packet until ssn. Returns a list of freed packets. 507e705c121SKalle Valo * Must be atomic 508e705c121SKalle Valo * @txq_enable: setup a queue. To setup an AC queue, use the 509e705c121SKalle Valo * iwl_trans_ac_txq_enable wrapper. fw_alive must have been called before 510e705c121SKalle Valo * this one. The op_mode must not configure the HCMD queue. The scheduler 511e705c121SKalle Valo * configuration may be %NULL, in which case the hardware will not be 512dcfbd67bSEmmanuel Grumbach * configured. If true is returned, the operation mode needs to increment 513dcfbd67bSEmmanuel Grumbach * the sequence number of the packets routed to this queue because of a 514dcfbd67bSEmmanuel Grumbach * hardware scheduler bug. May sleep. 515e705c121SKalle Valo * @txq_disable: de-configure a Tx queue to send AMPDUs 516e705c121SKalle Valo * Must be atomic 51742db09c1SLiad Kaufman * @txq_set_shared_mode: change Tx queue shared/unshared marking 518d6d517b7SSara Sharon * @wait_tx_queues_empty: wait until tx queues are empty. May sleep. 519d6d517b7SSara Sharon * @wait_txq_empty: wait until specific tx queue is empty. May sleep. 520e705c121SKalle Valo * @freeze_txq_timer: prevents the timer of the queue from firing until the 521e705c121SKalle Valo * queue is set to awake. Must be atomic. 5220cd58eaaSEmmanuel Grumbach * @block_txq_ptrs: stop updating the write pointers of the Tx queues. Note 5230cd58eaaSEmmanuel Grumbach * that the transport needs to refcount the calls since this function 5240cd58eaaSEmmanuel Grumbach * will be called several times with block = true, and then the queues 5250cd58eaaSEmmanuel Grumbach * need to be unblocked only after the same number of calls with 5260cd58eaaSEmmanuel Grumbach * block = false. 527e705c121SKalle Valo * @write8: write a u8 to a register at offset ofs from the BAR 528e705c121SKalle Valo * @write32: write a u32 to a register at offset ofs from the BAR 529e705c121SKalle Valo * @read32: read a u32 register at offset ofs from the BAR 530e705c121SKalle Valo * @read_prph: read a DWORD from a periphery register 531e705c121SKalle Valo * @write_prph: write a DWORD to a periphery register 532e705c121SKalle Valo * @read_mem: read device's SRAM in DWORD 533e705c121SKalle Valo * @write_mem: write device's SRAM in DWORD. If %buf is %NULL, then the memory 534e705c121SKalle Valo * will be zeroed. 535e705c121SKalle Valo * @configure: configure parameters required by the transport layer from 536e705c121SKalle Valo * the op_mode. May be called several times before start_fw, can't be 537e705c121SKalle Valo * called after that. 538e705c121SKalle Valo * @set_pmi: set the power pmi state 539e705c121SKalle Valo * @grab_nic_access: wake the NIC to be able to access non-HBUS regs. 540e705c121SKalle Valo * Sleeping is not allowed between grab_nic_access and 541e705c121SKalle Valo * release_nic_access. 542e705c121SKalle Valo * @release_nic_access: let the NIC go to sleep. The "flags" parameter 543e705c121SKalle Valo * must be the same one that was sent before to the grab_nic_access. 544e705c121SKalle Valo * @set_bits_mask - set SRAM register according to value and mask. 545e705c121SKalle Valo * @dump_data: return a vmalloc'ed buffer with debug data, maybe containing last 546e705c121SKalle Valo * TX'ed commands and similar. The buffer will be vfree'd by the caller. 547e705c121SKalle Valo * Note that the transport must fill in the proper file headers. 548f7805b33SLior Cohen * @debugfs_cleanup: used in the driver unload flow to make a proper cleanup 549f7805b33SLior Cohen * of the trans debugfs 550e705c121SKalle Valo */ 551e705c121SKalle Valo struct iwl_trans_ops { 552e705c121SKalle Valo 553bab3cb92SEmmanuel Grumbach int (*start_hw)(struct iwl_trans *iwl_trans); 554e705c121SKalle Valo void (*op_mode_leave)(struct iwl_trans *iwl_trans); 555e705c121SKalle Valo int (*start_fw)(struct iwl_trans *trans, const struct fw_img *fw, 556e705c121SKalle Valo bool run_in_rfkill); 557e705c121SKalle Valo void (*fw_alive)(struct iwl_trans *trans, u32 scd_addr); 558bab3cb92SEmmanuel Grumbach void (*stop_device)(struct iwl_trans *trans); 559e705c121SKalle Valo 560e5f3f215SHaim Dreyfuss int (*d3_suspend)(struct iwl_trans *trans, bool test, bool reset); 561e705c121SKalle Valo int (*d3_resume)(struct iwl_trans *trans, enum iwl_d3_status *status, 56223ae6128SMatti Gottlieb bool test, bool reset); 563e705c121SKalle Valo 564e705c121SKalle Valo int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 565e705c121SKalle Valo 566e705c121SKalle Valo int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, 567e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int queue); 568e705c121SKalle Valo void (*reclaim)(struct iwl_trans *trans, int queue, int ssn, 569e705c121SKalle Valo struct sk_buff_head *skbs); 570e705c121SKalle Valo 571ba7136f3SAlex Malamud void (*set_q_ptrs)(struct iwl_trans *trans, int queue, int ptr); 572ba7136f3SAlex Malamud 573dcfbd67bSEmmanuel Grumbach bool (*txq_enable)(struct iwl_trans *trans, int queue, u16 ssn, 574e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 575e705c121SKalle Valo unsigned int queue_wdg_timeout); 576e705c121SKalle Valo void (*txq_disable)(struct iwl_trans *trans, int queue, 577e705c121SKalle Valo bool configure_scd); 5782f7a3863SLuca Coelho /* 22000 functions */ 5796b35ff91SSara Sharon int (*txq_alloc)(struct iwl_trans *trans, 5801169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 5815369774cSSara Sharon int cmd_id, int size, 5826b35ff91SSara Sharon unsigned int queue_wdg_timeout); 5836b35ff91SSara Sharon void (*txq_free)(struct iwl_trans *trans, int queue); 58492536c96SSara Sharon int (*rxq_dma_data)(struct iwl_trans *trans, int queue, 58592536c96SSara Sharon struct iwl_trans_rxq_dma_data *data); 586e705c121SKalle Valo 58742db09c1SLiad Kaufman void (*txq_set_shared_mode)(struct iwl_trans *trans, u32 txq_id, 58842db09c1SLiad Kaufman bool shared); 58942db09c1SLiad Kaufman 590a1a57877SSara Sharon int (*wait_tx_queues_empty)(struct iwl_trans *trans, u32 txq_bm); 591d6d517b7SSara Sharon int (*wait_txq_empty)(struct iwl_trans *trans, int queue); 592e705c121SKalle Valo void (*freeze_txq_timer)(struct iwl_trans *trans, unsigned long txqs, 593e705c121SKalle Valo bool freeze); 5940cd58eaaSEmmanuel Grumbach void (*block_txq_ptrs)(struct iwl_trans *trans, bool block); 595e705c121SKalle Valo 596e705c121SKalle Valo void (*write8)(struct iwl_trans *trans, u32 ofs, u8 val); 597e705c121SKalle Valo void (*write32)(struct iwl_trans *trans, u32 ofs, u32 val); 598e705c121SKalle Valo u32 (*read32)(struct iwl_trans *trans, u32 ofs); 599e705c121SKalle Valo u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); 600e705c121SKalle Valo void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); 601e705c121SKalle Valo int (*read_mem)(struct iwl_trans *trans, u32 addr, 602e705c121SKalle Valo void *buf, int dwords); 603e705c121SKalle Valo int (*write_mem)(struct iwl_trans *trans, u32 addr, 604e705c121SKalle Valo const void *buf, int dwords); 605e705c121SKalle Valo void (*configure)(struct iwl_trans *trans, 606e705c121SKalle Valo const struct iwl_trans_config *trans_cfg); 607e705c121SKalle Valo void (*set_pmi)(struct iwl_trans *trans, bool state); 608870c2a11SGolan Ben Ami void (*sw_reset)(struct iwl_trans *trans); 60923ba9340SEmmanuel Grumbach bool (*grab_nic_access)(struct iwl_trans *trans, unsigned long *flags); 610e705c121SKalle Valo void (*release_nic_access)(struct iwl_trans *trans, 611e705c121SKalle Valo unsigned long *flags); 612e705c121SKalle Valo void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, 613e705c121SKalle Valo u32 value); 614e705c121SKalle Valo int (*suspend)(struct iwl_trans *trans); 615e705c121SKalle Valo void (*resume)(struct iwl_trans *trans); 616e705c121SKalle Valo 617e705c121SKalle Valo struct iwl_trans_dump_data *(*dump_data)(struct iwl_trans *trans, 61879f033f6SSara Sharon u32 dump_mask); 619f7805b33SLior Cohen void (*debugfs_cleanup)(struct iwl_trans *trans); 620d1967ce6SShahar S Matityahu void (*sync_nmi)(struct iwl_trans *trans); 621e705c121SKalle Valo }; 622e705c121SKalle Valo 623e705c121SKalle Valo /** 624e705c121SKalle Valo * enum iwl_trans_state - state of the transport layer 625e705c121SKalle Valo * 626e705c121SKalle Valo * @IWL_TRANS_NO_FW: no fw has sent an alive response 627e705c121SKalle Valo * @IWL_TRANS_FW_ALIVE: a fw has sent an alive response 628e705c121SKalle Valo */ 629e705c121SKalle Valo enum iwl_trans_state { 630e705c121SKalle Valo IWL_TRANS_NO_FW = 0, 631e705c121SKalle Valo IWL_TRANS_FW_ALIVE = 1, 632e705c121SKalle Valo }; 633e705c121SKalle Valo 634e705c121SKalle Valo /** 635b7282643SLuca Coelho * DOC: Platform power management 636e705c121SKalle Valo * 637b7282643SLuca Coelho * In system-wide power management the entire platform goes into a low 638b7282643SLuca Coelho * power state (e.g. idle or suspend to RAM) at the same time and the 639b7282643SLuca Coelho * device is configured as a wakeup source for the entire platform. 640b7282643SLuca Coelho * This is usually triggered by userspace activity (e.g. the user 641b7282643SLuca Coelho * presses the suspend button or a power management daemon decides to 642b7282643SLuca Coelho * put the platform in low power mode). The device's behavior in this 643b7282643SLuca Coelho * mode is dictated by the wake-on-WLAN configuration. 644b7282643SLuca Coelho * 645b7282643SLuca Coelho * The terms used for the device's behavior are as follows: 646b7282643SLuca Coelho * 647b7282643SLuca Coelho * - D0: the device is fully powered and the host is awake; 648b7282643SLuca Coelho * - D3: the device is in low power mode and only reacts to 649b7282643SLuca Coelho * specific events (e.g. magic-packet received or scan 650b7282643SLuca Coelho * results found); 651b7282643SLuca Coelho * 652b7282643SLuca Coelho * These terms reflect the power modes in the firmware and are not to 653f60e2750SEmmanuel Grumbach * be confused with the physical device power state. 654e705c121SKalle Valo */ 655b7282643SLuca Coelho 656b7282643SLuca Coelho /** 657b7282643SLuca Coelho * enum iwl_plat_pm_mode - platform power management mode 658b7282643SLuca Coelho * 659b7282643SLuca Coelho * This enumeration describes the device's platform power management 660f60e2750SEmmanuel Grumbach * behavior when in system-wide suspend (i.e WoWLAN). 661b7282643SLuca Coelho * 662b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this 663f60e2750SEmmanuel Grumbach * device. In system-wide suspend mode, it means that the all 664f60e2750SEmmanuel Grumbach * connections will be closed automatically by mac80211 before 665f60e2750SEmmanuel Grumbach * the platform is suspended. 666b7282643SLuca Coelho * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN). 667b7282643SLuca Coelho */ 668b7282643SLuca Coelho enum iwl_plat_pm_mode { 669b7282643SLuca Coelho IWL_PLAT_PM_MODE_DISABLED, 670b7282643SLuca Coelho IWL_PLAT_PM_MODE_D3, 671e705c121SKalle Valo }; 672e705c121SKalle Valo 673341bd290SShahar S Matityahu /** 674341bd290SShahar S Matityahu * enum iwl_ini_cfg_state 675341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 676341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 677341bd290SShahar S Matityahu * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 678341bd290SShahar S Matityahu * are corrupted. The rest of the debug TLVs will still be used 679341bd290SShahar S Matityahu */ 680341bd290SShahar S Matityahu enum iwl_ini_cfg_state { 681341bd290SShahar S Matityahu IWL_INI_CFG_STATE_NOT_LOADED, 682341bd290SShahar S Matityahu IWL_INI_CFG_STATE_LOADED, 683341bd290SShahar S Matityahu IWL_INI_CFG_STATE_CORRUPTED, 684341bd290SShahar S Matityahu }; 685341bd290SShahar S Matityahu 686b8a7547dSShahar S Matityahu /* Max time to wait for nmi interrupt */ 687b8a7547dSShahar S Matityahu #define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 688b8a7547dSShahar S Matityahu 68988964b2eSSara Sharon /** 69088964b2eSSara Sharon * struct iwl_dram_data 69188964b2eSSara Sharon * @physical: page phy pointer 69288964b2eSSara Sharon * @block: pointer to the allocated block/page 69388964b2eSSara Sharon * @size: size of the block/page 69488964b2eSSara Sharon */ 69588964b2eSSara Sharon struct iwl_dram_data { 69688964b2eSSara Sharon dma_addr_t physical; 69788964b2eSSara Sharon void *block; 69888964b2eSSara Sharon int size; 69988964b2eSSara Sharon }; 7004cbb8e50SLuciano Coelho 701e705c121SKalle Valo /** 702593fae3eSShahar S Matityahu * struct iwl_fw_mon - fw monitor per allocation id 703593fae3eSShahar S Matityahu * @num_frags: number of fragments 704593fae3eSShahar S Matityahu * @frags: an array of DRAM buffer fragments 705593fae3eSShahar S Matityahu */ 706593fae3eSShahar S Matityahu struct iwl_fw_mon { 707593fae3eSShahar S Matityahu u32 num_frags; 708593fae3eSShahar S Matityahu struct iwl_dram_data *frags; 709593fae3eSShahar S Matityahu }; 710593fae3eSShahar S Matityahu 711593fae3eSShahar S Matityahu /** 712505a00c0SShahar S Matityahu * struct iwl_self_init_dram - dram data used by self init process 713505a00c0SShahar S Matityahu * @fw: lmac and umac dram data 714505a00c0SShahar S Matityahu * @fw_cnt: total number of items in array 715505a00c0SShahar S Matityahu * @paging: paging dram data 716505a00c0SShahar S Matityahu * @paging_cnt: total number of items in array 717505a00c0SShahar S Matityahu */ 718505a00c0SShahar S Matityahu struct iwl_self_init_dram { 719505a00c0SShahar S Matityahu struct iwl_dram_data *fw; 720505a00c0SShahar S Matityahu int fw_cnt; 721505a00c0SShahar S Matityahu struct iwl_dram_data *paging; 722505a00c0SShahar S Matityahu int paging_cnt; 723505a00c0SShahar S Matityahu }; 724505a00c0SShahar S Matityahu 725505a00c0SShahar S Matityahu /** 72691c28b83SShahar S Matityahu * struct iwl_trans_debug - transport debug related data 72791c28b83SShahar S Matityahu * 72891c28b83SShahar S Matityahu * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 72991c28b83SShahar S Matityahu * @rec_on: true iff there is a fw debug recording currently active 73091c28b83SShahar S Matityahu * @dest_tlv: points to the destination TLV for debug 73191c28b83SShahar S Matityahu * @conf_tlv: array of pointers to configuration TLVs for debug 73291c28b83SShahar S Matityahu * @trigger_tlv: array of pointers to triggers TLVs for debug 73391c28b83SShahar S Matityahu * @lmac_error_event_table: addrs of lmacs error tables 73491c28b83SShahar S Matityahu * @umac_error_event_table: addr of umac error table 73591c28b83SShahar S Matityahu * @error_event_table_tlv_status: bitmap that indicates what error table 73691c28b83SShahar S Matityahu * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 737341bd290SShahar S Matityahu * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 738341bd290SShahar S Matityahu * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 739593fae3eSShahar S Matityahu * @fw_mon_cfg: debug buffer allocation configuration 740593fae3eSShahar S Matityahu * @fw_mon_ini: DRAM buffer fragments per allocation id 74169f0e505SShahar S Matityahu * @fw_mon: DRAM buffer for firmware monitor 74291c28b83SShahar S Matityahu * @hw_error: equals true if hw error interrupt was received from the FW 743029c25f3SShahar S Matityahu * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 7443b589d56SShahar S Matityahu * @active_regions: active regions 745677d25b2SShahar S Matityahu * @debug_info_tlv_list: list of debug info TLVs 746a9248de4SShahar S Matityahu * @time_point: array of debug time points 74760e8abd9SShahar S Matityahu * @periodic_trig_list: periodic triggers list 748cf29c5b6SShahar S Matityahu * @domains_bitmap: bitmap of active domains other than 749cf29c5b6SShahar S Matityahu * &IWL_FW_INI_DOMAIN_ALWAYS_ON 75091c28b83SShahar S Matityahu */ 75191c28b83SShahar S Matityahu struct iwl_trans_debug { 75291c28b83SShahar S Matityahu u8 n_dest_reg; 75391c28b83SShahar S Matityahu bool rec_on; 75491c28b83SShahar S Matityahu 75591c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 75691c28b83SShahar S Matityahu const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX]; 75791c28b83SShahar S Matityahu struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv; 75891c28b83SShahar S Matityahu 75991c28b83SShahar S Matityahu u32 lmac_error_event_table[2]; 76091c28b83SShahar S Matityahu u32 umac_error_event_table; 76191c28b83SShahar S Matityahu unsigned int error_event_table_tlv_status; 76291c28b83SShahar S Matityahu 763341bd290SShahar S Matityahu enum iwl_ini_cfg_state internal_ini_cfg; 764341bd290SShahar S Matityahu enum iwl_ini_cfg_state external_ini_cfg; 76591c28b83SShahar S Matityahu 766593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 767593fae3eSShahar S Matityahu struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 768593fae3eSShahar S Matityahu 76969f0e505SShahar S Matityahu struct iwl_dram_data fw_mon; 77091c28b83SShahar S Matityahu 77191c28b83SShahar S Matityahu bool hw_error; 772029c25f3SShahar S Matityahu enum iwl_fw_ini_buffer_location ini_dest; 7733b589d56SShahar S Matityahu 7743b589d56SShahar S Matityahu struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 775677d25b2SShahar S Matityahu struct list_head debug_info_tlv_list; 776a9248de4SShahar S Matityahu struct iwl_dbg_tlv_time_point_data 777a9248de4SShahar S Matityahu time_point[IWL_FW_INI_TIME_POINT_NUM]; 77860e8abd9SShahar S Matityahu struct list_head periodic_trig_list; 779cf29c5b6SShahar S Matityahu 780cf29c5b6SShahar S Matityahu u32 domains_bitmap; 78191c28b83SShahar S Matityahu }; 78291c28b83SShahar S Matityahu 78391c28b83SShahar S Matityahu /** 784e705c121SKalle Valo * struct iwl_trans - transport common data 785e705c121SKalle Valo * 786e705c121SKalle Valo * @ops - pointer to iwl_trans_ops 787e705c121SKalle Valo * @op_mode - pointer to the op_mode 788286ca8ebSLuca Coelho * @trans_cfg: the trans-specific configuration part 789e705c121SKalle Valo * @cfg - pointer to the configuration 7906f482e37SSara Sharon * @drv - pointer to iwl_drv 791e705c121SKalle Valo * @status: a bit-mask of transport status flags 792e705c121SKalle Valo * @dev - pointer to struct device * that represents the device 793e705c121SKalle Valo * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 794e705c121SKalle Valo * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 7951afb0ae4SHaim Dreyfuss * @hw_rf_id a u32 with the device RF ID 796e705c121SKalle Valo * @hw_id: a u32 with the ID of the device / sub-device. 797e705c121SKalle Valo * Set during transport allocation. 798e705c121SKalle Valo * @hw_id_str: a string with info about HW ID. Set during transport allocation. 799e705c121SKalle Valo * @pm_support: set to true in start_hw if link pm is supported 800e705c121SKalle Valo * @ltr_enabled: set to true if the LTR is enabled 8015b88792cSSara Sharon * @wide_cmd_header: true when ucode supports wide command header format 802e705c121SKalle Valo * @num_rx_queues: number of RX queues allocated by the transport; 803e705c121SKalle Valo * the transport must set this before calling iwl_drv_start() 804132db31cSGolan Ben-Ami * @iml_len: the length of the image loader 805132db31cSGolan Ben-Ami * @iml: a pointer to the image loader itself 806e705c121SKalle Valo * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only. 807e705c121SKalle Valo * The user should use iwl_trans_{alloc,free}_tx_cmd. 808e705c121SKalle Valo * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 809e705c121SKalle Valo * starting the firmware, used for tracing 810e705c121SKalle Valo * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 811e705c121SKalle Valo * start of the 802.11 header in the @rx_mpdu_cmd 812e705c121SKalle Valo * @dflt_pwr_limit: default power limit fetched from the platform (ACPI) 813b7282643SLuca Coelho * @system_pm_mode: the system-wide power management mode in use. 814b7282643SLuca Coelho * This mode is set dynamically, depending on the WoWLAN values 815b7282643SLuca Coelho * configured from the userspace at runtime. 816e705c121SKalle Valo */ 817e705c121SKalle Valo struct iwl_trans { 818e705c121SKalle Valo const struct iwl_trans_ops *ops; 819e705c121SKalle Valo struct iwl_op_mode *op_mode; 820286ca8ebSLuca Coelho const struct iwl_cfg_trans_params *trans_cfg; 821e705c121SKalle Valo const struct iwl_cfg *cfg; 8226f482e37SSara Sharon struct iwl_drv *drv; 823e705c121SKalle Valo enum iwl_trans_state state; 824e705c121SKalle Valo unsigned long status; 825e705c121SKalle Valo 826e705c121SKalle Valo struct device *dev; 827e705c121SKalle Valo u32 max_skb_frags; 828e705c121SKalle Valo u32 hw_rev; 8291afb0ae4SHaim Dreyfuss u32 hw_rf_id; 830e705c121SKalle Valo u32 hw_id; 831e705c121SKalle Valo char hw_id_str[52]; 832e705c121SKalle Valo 833e705c121SKalle Valo u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 834e705c121SKalle Valo 835e705c121SKalle Valo bool pm_support; 836e705c121SKalle Valo bool ltr_enabled; 837e705c121SKalle Valo 83839bdb17eSSharon Dvir const struct iwl_hcmd_arr *command_groups; 83939bdb17eSSharon Dvir int command_groups_size; 8405b88792cSSara Sharon bool wide_cmd_header; 84139bdb17eSSharon Dvir 842e705c121SKalle Valo u8 num_rx_queues; 843e705c121SKalle Valo 844132db31cSGolan Ben-Ami size_t iml_len; 845132db31cSGolan Ben-Ami u8 *iml; 846132db31cSGolan Ben-Ami 847e705c121SKalle Valo /* The following fields are internal only */ 848e705c121SKalle Valo struct kmem_cache *dev_cmd_pool; 849e705c121SKalle Valo char dev_cmd_pool_name[50]; 850e705c121SKalle Valo 851e705c121SKalle Valo struct dentry *dbgfs_dir; 852e705c121SKalle Valo 853e705c121SKalle Valo #ifdef CONFIG_LOCKDEP 854e705c121SKalle Valo struct lockdep_map sync_cmd_lockdep_map; 855e705c121SKalle Valo #endif 856e705c121SKalle Valo 85791c28b83SShahar S Matityahu struct iwl_trans_debug dbg; 858505a00c0SShahar S Matityahu struct iwl_self_init_dram init_dram; 859e705c121SKalle Valo 860b7282643SLuca Coelho enum iwl_plat_pm_mode system_pm_mode; 861700b3799SShahar S Matityahu 8620b295a1eSLuca Coelho const char *name; 8630b295a1eSLuca Coelho 864e705c121SKalle Valo /* pointer to trans specific struct */ 865e705c121SKalle Valo /*Ensure that this pointer will always be aligned to sizeof pointer */ 866e705c121SKalle Valo char trans_specific[0] __aligned(sizeof(void *)); 867e705c121SKalle Valo }; 868e705c121SKalle Valo 86939bdb17eSSharon Dvir const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 87039bdb17eSSharon Dvir int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans); 87139bdb17eSSharon Dvir 872e705c121SKalle Valo static inline void iwl_trans_configure(struct iwl_trans *trans, 873e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 874e705c121SKalle Valo { 875e705c121SKalle Valo trans->op_mode = trans_cfg->op_mode; 876e705c121SKalle Valo 877e705c121SKalle Valo trans->ops->configure(trans, trans_cfg); 87839bdb17eSSharon Dvir WARN_ON(iwl_cmd_groups_verify_sorted(trans_cfg)); 879e705c121SKalle Valo } 880e705c121SKalle Valo 881bab3cb92SEmmanuel Grumbach static inline int iwl_trans_start_hw(struct iwl_trans *trans) 882e705c121SKalle Valo { 883e705c121SKalle Valo might_sleep(); 884e705c121SKalle Valo 885bab3cb92SEmmanuel Grumbach return trans->ops->start_hw(trans); 886e705c121SKalle Valo } 887e705c121SKalle Valo 888e705c121SKalle Valo static inline void iwl_trans_op_mode_leave(struct iwl_trans *trans) 889e705c121SKalle Valo { 890e705c121SKalle Valo might_sleep(); 891e705c121SKalle Valo 892e705c121SKalle Valo if (trans->ops->op_mode_leave) 893e705c121SKalle Valo trans->ops->op_mode_leave(trans); 894e705c121SKalle Valo 895e705c121SKalle Valo trans->op_mode = NULL; 896e705c121SKalle Valo 897e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 898e705c121SKalle Valo } 899e705c121SKalle Valo 900e705c121SKalle Valo static inline void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr) 901e705c121SKalle Valo { 902e705c121SKalle Valo might_sleep(); 903e705c121SKalle Valo 904e705c121SKalle Valo trans->state = IWL_TRANS_FW_ALIVE; 905e705c121SKalle Valo 906e705c121SKalle Valo trans->ops->fw_alive(trans, scd_addr); 907e705c121SKalle Valo } 908e705c121SKalle Valo 909e705c121SKalle Valo static inline int iwl_trans_start_fw(struct iwl_trans *trans, 910e705c121SKalle Valo const struct fw_img *fw, 911e705c121SKalle Valo bool run_in_rfkill) 912e705c121SKalle Valo { 913e705c121SKalle Valo might_sleep(); 914e705c121SKalle Valo 915e705c121SKalle Valo WARN_ON_ONCE(!trans->rx_mpdu_cmd); 916e705c121SKalle Valo 917e705c121SKalle Valo clear_bit(STATUS_FW_ERROR, &trans->status); 918e705c121SKalle Valo return trans->ops->start_fw(trans, fw, run_in_rfkill); 919e705c121SKalle Valo } 920e705c121SKalle Valo 921bab3cb92SEmmanuel Grumbach static inline void iwl_trans_stop_device(struct iwl_trans *trans) 922e705c121SKalle Valo { 923e705c121SKalle Valo might_sleep(); 924e705c121SKalle Valo 925bab3cb92SEmmanuel Grumbach trans->ops->stop_device(trans); 926e705c121SKalle Valo 927e705c121SKalle Valo trans->state = IWL_TRANS_NO_FW; 928e705c121SKalle Valo } 929e705c121SKalle Valo 930e5f3f215SHaim Dreyfuss static inline int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, 93123ae6128SMatti Gottlieb bool reset) 932e705c121SKalle Valo { 933e705c121SKalle Valo might_sleep(); 934e5f3f215SHaim Dreyfuss if (!trans->ops->d3_suspend) 935e5f3f215SHaim Dreyfuss return 0; 936e5f3f215SHaim Dreyfuss 937e5f3f215SHaim Dreyfuss return trans->ops->d3_suspend(trans, test, reset); 938e705c121SKalle Valo } 939e705c121SKalle Valo 940e705c121SKalle Valo static inline int iwl_trans_d3_resume(struct iwl_trans *trans, 941e705c121SKalle Valo enum iwl_d3_status *status, 94223ae6128SMatti Gottlieb bool test, bool reset) 943e705c121SKalle Valo { 944e705c121SKalle Valo might_sleep(); 945e705c121SKalle Valo if (!trans->ops->d3_resume) 946e705c121SKalle Valo return 0; 947e705c121SKalle Valo 94823ae6128SMatti Gottlieb return trans->ops->d3_resume(trans, status, test, reset); 949e705c121SKalle Valo } 950e705c121SKalle Valo 951e705c121SKalle Valo static inline int iwl_trans_suspend(struct iwl_trans *trans) 952e705c121SKalle Valo { 953e705c121SKalle Valo if (!trans->ops->suspend) 954e705c121SKalle Valo return 0; 955e705c121SKalle Valo 956e705c121SKalle Valo return trans->ops->suspend(trans); 957e705c121SKalle Valo } 958e705c121SKalle Valo 959e705c121SKalle Valo static inline void iwl_trans_resume(struct iwl_trans *trans) 960e705c121SKalle Valo { 961e705c121SKalle Valo if (trans->ops->resume) 962e705c121SKalle Valo trans->ops->resume(trans); 963e705c121SKalle Valo } 964e705c121SKalle Valo 965e705c121SKalle Valo static inline struct iwl_trans_dump_data * 96679f033f6SSara Sharon iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask) 967e705c121SKalle Valo { 968e705c121SKalle Valo if (!trans->ops->dump_data) 969e705c121SKalle Valo return NULL; 97079f033f6SSara Sharon return trans->ops->dump_data(trans, dump_mask); 971e705c121SKalle Valo } 972e705c121SKalle Valo 973e705c121SKalle Valo static inline struct iwl_device_cmd * 974e705c121SKalle Valo iwl_trans_alloc_tx_cmd(struct iwl_trans *trans) 975e705c121SKalle Valo { 9760ae0bb3fSLuca Coelho return kmem_cache_alloc(trans->dev_cmd_pool, GFP_ATOMIC); 977e705c121SKalle Valo } 978e705c121SKalle Valo 97992fe8343SEmmanuel Grumbach int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 98092fe8343SEmmanuel Grumbach 981e705c121SKalle Valo static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 982e705c121SKalle Valo struct iwl_device_cmd *dev_cmd) 983e705c121SKalle Valo { 9841ea423b0SLuca Coelho kmem_cache_free(trans->dev_cmd_pool, dev_cmd); 985e705c121SKalle Valo } 986e705c121SKalle Valo 987e705c121SKalle Valo static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 988e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int queue) 989e705c121SKalle Valo { 990e705c121SKalle Valo if (unlikely(test_bit(STATUS_FW_ERROR, &trans->status))) 991e705c121SKalle Valo return -EIO; 992e705c121SKalle Valo 993e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 994e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 995e5d15cb5SEliad Peller return -EIO; 996e5d15cb5SEliad Peller } 997e705c121SKalle Valo 998e705c121SKalle Valo return trans->ops->tx(trans, skb, dev_cmd, queue); 999e705c121SKalle Valo } 1000e705c121SKalle Valo 1001e705c121SKalle Valo static inline void iwl_trans_reclaim(struct iwl_trans *trans, int queue, 1002e705c121SKalle Valo int ssn, struct sk_buff_head *skbs) 1003e705c121SKalle Valo { 1004e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1005e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1006e5d15cb5SEliad Peller return; 1007e5d15cb5SEliad Peller } 1008e705c121SKalle Valo 1009e705c121SKalle Valo trans->ops->reclaim(trans, queue, ssn, skbs); 1010e705c121SKalle Valo } 1011e705c121SKalle Valo 1012ba7136f3SAlex Malamud static inline void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, 1013ba7136f3SAlex Malamud int ptr) 1014ba7136f3SAlex Malamud { 1015ba7136f3SAlex Malamud if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1016ba7136f3SAlex Malamud IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1017ba7136f3SAlex Malamud return; 1018ba7136f3SAlex Malamud } 1019ba7136f3SAlex Malamud 1020ba7136f3SAlex Malamud trans->ops->set_q_ptrs(trans, queue, ptr); 1021ba7136f3SAlex Malamud } 1022ba7136f3SAlex Malamud 1023e705c121SKalle Valo static inline void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 1024e705c121SKalle Valo bool configure_scd) 1025e705c121SKalle Valo { 1026e705c121SKalle Valo trans->ops->txq_disable(trans, queue, configure_scd); 1027e705c121SKalle Valo } 1028e705c121SKalle Valo 1029dcfbd67bSEmmanuel Grumbach static inline bool 1030e705c121SKalle Valo iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 1031e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1032e705c121SKalle Valo unsigned int queue_wdg_timeout) 1033e705c121SKalle Valo { 1034e705c121SKalle Valo might_sleep(); 1035e705c121SKalle Valo 1036e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1037e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1038dcfbd67bSEmmanuel Grumbach return false; 1039e5d15cb5SEliad Peller } 1040e705c121SKalle Valo 1041dcfbd67bSEmmanuel Grumbach return trans->ops->txq_enable(trans, queue, ssn, 1042dcfbd67bSEmmanuel Grumbach cfg, queue_wdg_timeout); 1043e705c121SKalle Valo } 1044e705c121SKalle Valo 104592536c96SSara Sharon static inline int 104692536c96SSara Sharon iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 104792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 104892536c96SSara Sharon { 104992536c96SSara Sharon if (WARN_ON_ONCE(!trans->ops->rxq_dma_data)) 105092536c96SSara Sharon return -ENOTSUPP; 105192536c96SSara Sharon 105292536c96SSara Sharon return trans->ops->rxq_dma_data(trans, queue, data); 105392536c96SSara Sharon } 105492536c96SSara Sharon 10556b35ff91SSara Sharon static inline void 10566b35ff91SSara Sharon iwl_trans_txq_free(struct iwl_trans *trans, int queue) 10576b35ff91SSara Sharon { 10586b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_free)) 10596b35ff91SSara Sharon return; 10606b35ff91SSara Sharon 10616b35ff91SSara Sharon trans->ops->txq_free(trans, queue); 10626b35ff91SSara Sharon } 10636b35ff91SSara Sharon 10646b35ff91SSara Sharon static inline int 10656b35ff91SSara Sharon iwl_trans_txq_alloc(struct iwl_trans *trans, 10661169310fSGolan Ben Ami __le16 flags, u8 sta_id, u8 tid, 10675369774cSSara Sharon int cmd_id, int size, 10685369774cSSara Sharon unsigned int wdg_timeout) 10696b35ff91SSara Sharon { 10706b35ff91SSara Sharon might_sleep(); 10716b35ff91SSara Sharon 10726b35ff91SSara Sharon if (WARN_ON_ONCE(!trans->ops->txq_alloc)) 10736b35ff91SSara Sharon return -ENOTSUPP; 10746b35ff91SSara Sharon 10756b35ff91SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 10766b35ff91SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 10776b35ff91SSara Sharon return -EIO; 10786b35ff91SSara Sharon } 10796b35ff91SSara Sharon 10801169310fSGolan Ben Ami return trans->ops->txq_alloc(trans, flags, sta_id, tid, 10811169310fSGolan Ben Ami cmd_id, size, wdg_timeout); 10826b35ff91SSara Sharon } 10836b35ff91SSara Sharon 108442db09c1SLiad Kaufman static inline void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 108542db09c1SLiad Kaufman int queue, bool shared_mode) 108642db09c1SLiad Kaufman { 108742db09c1SLiad Kaufman if (trans->ops->txq_set_shared_mode) 108842db09c1SLiad Kaufman trans->ops->txq_set_shared_mode(trans, queue, shared_mode); 108942db09c1SLiad Kaufman } 109042db09c1SLiad Kaufman 1091e705c121SKalle Valo static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 1092e705c121SKalle Valo int fifo, int sta_id, int tid, 1093e705c121SKalle Valo int frame_limit, u16 ssn, 1094e705c121SKalle Valo unsigned int queue_wdg_timeout) 1095e705c121SKalle Valo { 1096e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1097e705c121SKalle Valo .fifo = fifo, 1098e705c121SKalle Valo .sta_id = sta_id, 1099e705c121SKalle Valo .tid = tid, 1100e705c121SKalle Valo .frame_limit = frame_limit, 1101e705c121SKalle Valo .aggregate = sta_id >= 0, 1102e705c121SKalle Valo }; 1103e705c121SKalle Valo 1104e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 1105e705c121SKalle Valo } 1106e705c121SKalle Valo 1107e705c121SKalle Valo static inline 1108e705c121SKalle Valo void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 1109e705c121SKalle Valo unsigned int queue_wdg_timeout) 1110e705c121SKalle Valo { 1111e705c121SKalle Valo struct iwl_trans_txq_scd_cfg cfg = { 1112e705c121SKalle Valo .fifo = fifo, 1113e705c121SKalle Valo .sta_id = -1, 1114e705c121SKalle Valo .tid = IWL_MAX_TID_COUNT, 1115e705c121SKalle Valo .frame_limit = IWL_FRAME_LIMIT, 1116e705c121SKalle Valo .aggregate = false, 1117e705c121SKalle Valo }; 1118e705c121SKalle Valo 1119e705c121SKalle Valo iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1120e705c121SKalle Valo } 1121e705c121SKalle Valo 1122e705c121SKalle Valo static inline void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1123e705c121SKalle Valo unsigned long txqs, 1124e705c121SKalle Valo bool freeze) 1125e705c121SKalle Valo { 1126e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1127e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1128e5d15cb5SEliad Peller return; 1129e5d15cb5SEliad Peller } 1130e705c121SKalle Valo 1131e705c121SKalle Valo if (trans->ops->freeze_txq_timer) 1132e705c121SKalle Valo trans->ops->freeze_txq_timer(trans, txqs, freeze); 1133e705c121SKalle Valo } 1134e705c121SKalle Valo 11350cd58eaaSEmmanuel Grumbach static inline void iwl_trans_block_txq_ptrs(struct iwl_trans *trans, 11360cd58eaaSEmmanuel Grumbach bool block) 11370cd58eaaSEmmanuel Grumbach { 1138e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 11390cd58eaaSEmmanuel Grumbach IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1140e5d15cb5SEliad Peller return; 1141e5d15cb5SEliad Peller } 11420cd58eaaSEmmanuel Grumbach 11430cd58eaaSEmmanuel Grumbach if (trans->ops->block_txq_ptrs) 11440cd58eaaSEmmanuel Grumbach trans->ops->block_txq_ptrs(trans, block); 11450cd58eaaSEmmanuel Grumbach } 11460cd58eaaSEmmanuel Grumbach 1147a1a57877SSara Sharon static inline int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, 1148e705c121SKalle Valo u32 txqs) 1149e705c121SKalle Valo { 1150d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_tx_queues_empty)) 1151d6d517b7SSara Sharon return -ENOTSUPP; 1152d6d517b7SSara Sharon 1153e5d15cb5SEliad Peller if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1154e705c121SKalle Valo IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1155e5d15cb5SEliad Peller return -EIO; 1156e5d15cb5SEliad Peller } 1157e705c121SKalle Valo 1158a1a57877SSara Sharon return trans->ops->wait_tx_queues_empty(trans, txqs); 1159e705c121SKalle Valo } 1160e705c121SKalle Valo 1161d6d517b7SSara Sharon static inline int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue) 1162d6d517b7SSara Sharon { 1163d6d517b7SSara Sharon if (WARN_ON_ONCE(!trans->ops->wait_txq_empty)) 1164d6d517b7SSara Sharon return -ENOTSUPP; 1165d6d517b7SSara Sharon 1166d6d517b7SSara Sharon if (WARN_ON_ONCE(trans->state != IWL_TRANS_FW_ALIVE)) { 1167d6d517b7SSara Sharon IWL_ERR(trans, "%s bad state = %d\n", __func__, trans->state); 1168d6d517b7SSara Sharon return -EIO; 1169d6d517b7SSara Sharon } 1170d6d517b7SSara Sharon 1171d6d517b7SSara Sharon return trans->ops->wait_txq_empty(trans, queue); 1172d6d517b7SSara Sharon } 1173d6d517b7SSara Sharon 1174e705c121SKalle Valo static inline void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1175e705c121SKalle Valo { 1176e705c121SKalle Valo trans->ops->write8(trans, ofs, val); 1177e705c121SKalle Valo } 1178e705c121SKalle Valo 1179e705c121SKalle Valo static inline void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1180e705c121SKalle Valo { 1181e705c121SKalle Valo trans->ops->write32(trans, ofs, val); 1182e705c121SKalle Valo } 1183e705c121SKalle Valo 1184e705c121SKalle Valo static inline u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs) 1185e705c121SKalle Valo { 1186e705c121SKalle Valo return trans->ops->read32(trans, ofs); 1187e705c121SKalle Valo } 1188e705c121SKalle Valo 1189e705c121SKalle Valo static inline u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs) 1190e705c121SKalle Valo { 1191e705c121SKalle Valo return trans->ops->read_prph(trans, ofs); 1192e705c121SKalle Valo } 1193e705c121SKalle Valo 1194e705c121SKalle Valo static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, 1195e705c121SKalle Valo u32 val) 1196e705c121SKalle Valo { 1197e705c121SKalle Valo return trans->ops->write_prph(trans, ofs, val); 1198e705c121SKalle Valo } 1199e705c121SKalle Valo 1200e705c121SKalle Valo static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1201e705c121SKalle Valo void *buf, int dwords) 1202e705c121SKalle Valo { 1203e705c121SKalle Valo return trans->ops->read_mem(trans, addr, buf, dwords); 1204e705c121SKalle Valo } 1205e705c121SKalle Valo 1206e705c121SKalle Valo #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1207e705c121SKalle Valo do { \ 1208e705c121SKalle Valo if (__builtin_constant_p(bufsize)) \ 1209e705c121SKalle Valo BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1210e705c121SKalle Valo iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ 1211e705c121SKalle Valo } while (0) 1212e705c121SKalle Valo 1213e705c121SKalle Valo static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1214e705c121SKalle Valo { 1215e705c121SKalle Valo u32 value; 1216e705c121SKalle Valo 1217e705c121SKalle Valo if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) 1218e705c121SKalle Valo return 0xa5a5a5a5; 1219e705c121SKalle Valo 1220e705c121SKalle Valo return value; 1221e705c121SKalle Valo } 1222e705c121SKalle Valo 1223e705c121SKalle Valo static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1224e705c121SKalle Valo const void *buf, int dwords) 1225e705c121SKalle Valo { 1226e705c121SKalle Valo return trans->ops->write_mem(trans, addr, buf, dwords); 1227e705c121SKalle Valo } 1228e705c121SKalle Valo 1229e705c121SKalle Valo static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1230e705c121SKalle Valo u32 val) 1231e705c121SKalle Valo { 1232e705c121SKalle Valo return iwl_trans_write_mem(trans, addr, &val, 1); 1233e705c121SKalle Valo } 1234e705c121SKalle Valo 1235e705c121SKalle Valo static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) 1236e705c121SKalle Valo { 1237e705c121SKalle Valo if (trans->ops->set_pmi) 1238e705c121SKalle Valo trans->ops->set_pmi(trans, state); 1239e705c121SKalle Valo } 1240e705c121SKalle Valo 1241870c2a11SGolan Ben Ami static inline void iwl_trans_sw_reset(struct iwl_trans *trans) 1242870c2a11SGolan Ben Ami { 1243870c2a11SGolan Ben Ami if (trans->ops->sw_reset) 1244870c2a11SGolan Ben Ami trans->ops->sw_reset(trans); 1245870c2a11SGolan Ben Ami } 1246870c2a11SGolan Ben Ami 1247e705c121SKalle Valo static inline void 1248e705c121SKalle Valo iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) 1249e705c121SKalle Valo { 1250e705c121SKalle Valo trans->ops->set_bits_mask(trans, reg, mask, value); 1251e705c121SKalle Valo } 1252e705c121SKalle Valo 125323ba9340SEmmanuel Grumbach #define iwl_trans_grab_nic_access(trans, flags) \ 1254e705c121SKalle Valo __cond_lock(nic_access, \ 125523ba9340SEmmanuel Grumbach likely((trans)->ops->grab_nic_access(trans, flags))) 1256e705c121SKalle Valo 1257e705c121SKalle Valo static inline void __releases(nic_access) 1258e705c121SKalle Valo iwl_trans_release_nic_access(struct iwl_trans *trans, unsigned long *flags) 1259e705c121SKalle Valo { 1260e705c121SKalle Valo trans->ops->release_nic_access(trans, flags); 1261e705c121SKalle Valo __release(nic_access); 1262e705c121SKalle Valo } 1263e705c121SKalle Valo 1264e705c121SKalle Valo static inline void iwl_trans_fw_error(struct iwl_trans *trans) 1265e705c121SKalle Valo { 1266e705c121SKalle Valo if (WARN_ON_ONCE(!trans->op_mode)) 1267e705c121SKalle Valo return; 1268e705c121SKalle Valo 1269e705c121SKalle Valo /* prevent double restarts due to the same erroneous FW */ 1270e705c121SKalle Valo if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) 1271e705c121SKalle Valo iwl_op_mode_nic_error(trans->op_mode); 1272e705c121SKalle Valo } 1273e705c121SKalle Valo 1274068893b7SShahar S Matityahu static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1275068893b7SShahar S Matityahu { 1276068893b7SShahar S Matityahu return trans->state == IWL_TRANS_FW_ALIVE; 1277068893b7SShahar S Matityahu } 1278068893b7SShahar S Matityahu 1279d1967ce6SShahar S Matityahu static inline void iwl_trans_sync_nmi(struct iwl_trans *trans) 1280d1967ce6SShahar S Matityahu { 1281d1967ce6SShahar S Matityahu if (trans->ops->sync_nmi) 1282d1967ce6SShahar S Matityahu trans->ops->sync_nmi(trans); 1283d1967ce6SShahar S Matityahu } 1284d1967ce6SShahar S Matityahu 1285a1af4c48SShahar S Matityahu static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1286a1af4c48SShahar S Matityahu { 1287341bd290SShahar S Matityahu return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1288341bd290SShahar S Matityahu trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1289a1af4c48SShahar S Matityahu } 1290a1af4c48SShahar S Matityahu 1291e705c121SKalle Valo /***************************************************** 1292e705c121SKalle Valo * transport helper functions 1293e705c121SKalle Valo *****************************************************/ 1294e705c121SKalle Valo struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1295e705c121SKalle Valo struct device *dev, 12961ea423b0SLuca Coelho const struct iwl_trans_ops *ops); 1297e705c121SKalle Valo void iwl_trans_free(struct iwl_trans *trans); 1298e705c121SKalle Valo 1299e705c121SKalle Valo /***************************************************** 1300e705c121SKalle Valo * driver (transport) register/unregister functions 1301e705c121SKalle Valo ******************************************************/ 1302e705c121SKalle Valo int __must_check iwl_pci_register_driver(void); 1303e705c121SKalle Valo void iwl_pci_unregister_driver(void); 1304e705c121SKalle Valo 1305e705c121SKalle Valo #endif /* __iwl_trans_h__ */ 1306