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4  * redistributing this file, you may do so under either license.
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6  * GPL LICENSE SUMMARY
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8  * Copyright(c) 2014 Intel Mobile Communications GmbH
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11  * it under the terms of version 2 of the GNU General Public License as
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15  * WITHOUT ANY WARRANTY; without even the implied warranty of
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24  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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57  *****************************************************************************/
58 
59 #ifndef __iwl_scd_h__
60 #define __iwl_scd_h__
61 
62 #include "iwl-trans.h"
63 #include "iwl-io.h"
64 #include "iwl-prph.h"
65 
66 
67 static inline void iwl_scd_txq_set_chain(struct iwl_trans *trans,
68 					 u16 txq_id)
69 {
70 	iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
71 }
72 
73 static inline void iwl_scd_txq_enable_agg(struct iwl_trans *trans,
74 					  u16 txq_id)
75 {
76 	iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
77 }
78 
79 static inline void iwl_scd_txq_disable_agg(struct iwl_trans *trans,
80 					   u16 txq_id)
81 {
82 	iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
83 }
84 
85 static inline void iwl_scd_disable_agg(struct iwl_trans *trans)
86 {
87 	iwl_set_bits_prph(trans, SCD_AGGR_SEL, 0);
88 }
89 
90 static inline void iwl_scd_activate_fifos(struct iwl_trans *trans)
91 {
92 	iwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7));
93 }
94 
95 static inline void iwl_scd_deactivate_fifos(struct iwl_trans *trans)
96 {
97 	iwl_write_prph(trans, SCD_TXFACT, 0);
98 }
99 
100 static inline void iwl_scd_enable_set_active(struct iwl_trans *trans,
101 					     u32 value)
102 {
103 	iwl_write_prph(trans, SCD_EN_CTRL, value);
104 }
105 
106 static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
107 {
108 	if (chnl < 20)
109 		return SCD_BASE + 0x18 + chnl * 4;
110 	WARN_ON_ONCE(chnl >= 32);
111 	return SCD_BASE + 0x284 + (chnl - 20) * 4;
112 }
113 
114 static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
115 {
116 	if (chnl < 20)
117 		return SCD_BASE + 0x68 + chnl * 4;
118 	WARN_ON_ONCE(chnl >= 32);
119 	return SCD_BASE + 0x2B4 + chnl * 4;
120 }
121 
122 static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
123 {
124 	if (chnl < 20)
125 		return SCD_BASE + 0x10c + chnl * 4;
126 	WARN_ON_ONCE(chnl >= 32);
127 	return SCD_BASE + 0x334 + chnl * 4;
128 }
129 
130 static inline void iwl_scd_txq_set_inactive(struct iwl_trans *trans,
131 					    u16 txq_id)
132 {
133 	iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
134 		       (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
135 		       (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
136 }
137 
138 #endif
139