1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 *****************************************************************************/ 63 #include <linux/types.h> 64 #include <linux/slab.h> 65 #include <linux/export.h> 66 #include <linux/etherdevice.h> 67 #include <linux/pci.h> 68 #include <linux/firmware.h> 69 70 #include "iwl-drv.h" 71 #include "iwl-modparams.h" 72 #include "iwl-nvm-parse.h" 73 #include "iwl-prph.h" 74 #include "iwl-io.h" 75 #include "iwl-csr.h" 76 #include "fw/acpi.h" 77 #include "fw/api/nvm-reg.h" 78 #include "fw/api/commands.h" 79 #include "fw/api/cmdhdr.h" 80 #include "fw/img.h" 81 82 /* NVM offsets (in words) definitions */ 83 enum nvm_offsets { 84 /* NVM HW-Section offset (in words) definitions */ 85 SUBSYSTEM_ID = 0x0A, 86 HW_ADDR = 0x15, 87 88 /* NVM SW-Section offset (in words) definitions */ 89 NVM_SW_SECTION = 0x1C0, 90 NVM_VERSION = 0, 91 RADIO_CFG = 1, 92 SKU = 2, 93 N_HW_ADDRS = 3, 94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 95 96 /* NVM calibration section offset (in words) definitions */ 97 NVM_CALIB_SECTION = 0x2B8, 98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 99 100 /* NVM REGULATORY -Section offset (in words) definitions */ 101 NVM_CHANNELS_SDP = 0, 102 }; 103 104 enum ext_nvm_offsets { 105 /* NVM HW-Section offset (in words) definitions */ 106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 107 108 /* NVM SW-Section offset (in words) definitions */ 109 NVM_VERSION_EXT_NVM = 0, 110 RADIO_CFG_FAMILY_EXT_NVM = 0, 111 SKU_FAMILY_8000 = 2, 112 N_HW_ADDRS_FAMILY_8000 = 3, 113 114 /* NVM REGULATORY -Section offset (in words) definitions */ 115 NVM_CHANNELS_EXTENDED = 0, 116 NVM_LAR_OFFSET_OLD = 0x4C7, 117 NVM_LAR_OFFSET = 0x507, 118 NVM_LAR_ENABLED = 0x7, 119 }; 120 121 /* SKU Capabilities (actual values from NVM definition) */ 122 enum nvm_sku_bits { 123 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 124 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 125 NVM_SKU_CAP_11N_ENABLE = BIT(2), 126 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 128 }; 129 130 /* 131 * These are the channel numbers in the order that they are stored in the NVM 132 */ 133 static const u8 iwl_nvm_channels[] = { 134 /* 2.4 GHz */ 135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 136 /* 5 GHz */ 137 36, 40, 44 , 48, 52, 56, 60, 64, 138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 139 149, 153, 157, 161, 165 140 }; 141 142 static const u8 iwl_ext_nvm_channels[] = { 143 /* 2.4 GHz */ 144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 145 /* 5 GHz */ 146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148 149, 153, 157, 161, 165, 169, 173, 177, 181 149 }; 150 151 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 152 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 153 #define NUM_2GHZ_CHANNELS 14 154 #define NUM_2GHZ_CHANNELS_EXT 14 155 #define FIRST_2GHZ_HT_MINUS 5 156 #define LAST_2GHZ_HT_PLUS 9 157 #define LAST_5GHZ_HT 165 158 #define LAST_5GHZ_HT_FAMILY_8000 181 159 #define N_HW_ADDR_MASK 0xF 160 161 /* rate data (static) */ 162 static struct ieee80211_rate iwl_cfg80211_rates[] = { 163 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 164 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 165 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 166 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 167 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 168 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 169 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 170 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 171 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 172 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 173 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 174 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 175 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 176 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 177 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 178 }; 179 #define RATES_24_OFFS 0 180 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 181 #define RATES_52_OFFS 4 182 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 183 184 /** 185 * enum iwl_nvm_channel_flags - channel flags in NVM 186 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 187 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 188 * @NVM_CHANNEL_ACTIVE: active scanning allowed 189 * @NVM_CHANNEL_RADAR: radar detection required 190 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 191 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 192 * on same channel on 2.4 or same UNII band on 5.2 193 * @NVM_CHANNEL_UNIFORM: uniform spreading required 194 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 195 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 196 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 197 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 198 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 199 */ 200 enum iwl_nvm_channel_flags { 201 NVM_CHANNEL_VALID = BIT(0), 202 NVM_CHANNEL_IBSS = BIT(1), 203 NVM_CHANNEL_ACTIVE = BIT(3), 204 NVM_CHANNEL_RADAR = BIT(4), 205 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 206 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 207 NVM_CHANNEL_UNIFORM = BIT(7), 208 NVM_CHANNEL_20MHZ = BIT(8), 209 NVM_CHANNEL_40MHZ = BIT(9), 210 NVM_CHANNEL_80MHZ = BIT(10), 211 NVM_CHANNEL_160MHZ = BIT(11), 212 NVM_CHANNEL_DC_HIGH = BIT(12), 213 }; 214 215 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 216 int chan, u16 flags) 217 { 218 #define CHECK_AND_PRINT_I(x) \ 219 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 220 221 if (!(flags & NVM_CHANNEL_VALID)) { 222 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 223 chan, flags); 224 return; 225 } 226 227 /* Note: already can print up to 101 characters, 110 is the limit! */ 228 IWL_DEBUG_DEV(dev, level, 229 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 230 chan, flags, 231 CHECK_AND_PRINT_I(VALID), 232 CHECK_AND_PRINT_I(IBSS), 233 CHECK_AND_PRINT_I(ACTIVE), 234 CHECK_AND_PRINT_I(RADAR), 235 CHECK_AND_PRINT_I(INDOOR_ONLY), 236 CHECK_AND_PRINT_I(GO_CONCURRENT), 237 CHECK_AND_PRINT_I(UNIFORM), 238 CHECK_AND_PRINT_I(20MHZ), 239 CHECK_AND_PRINT_I(40MHZ), 240 CHECK_AND_PRINT_I(80MHZ), 241 CHECK_AND_PRINT_I(160MHZ), 242 CHECK_AND_PRINT_I(DC_HIGH)); 243 #undef CHECK_AND_PRINT_I 244 } 245 246 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz, 247 u16 nvm_flags, const struct iwl_cfg *cfg) 248 { 249 u32 flags = IEEE80211_CHAN_NO_HT40; 250 u32 last_5ghz_ht = LAST_5GHZ_HT; 251 252 if (cfg->nvm_type == IWL_NVM_EXT) 253 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 254 255 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) { 256 if (ch_num <= LAST_2GHZ_HT_PLUS) 257 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 258 if (ch_num >= FIRST_2GHZ_HT_MINUS) 259 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 260 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) { 261 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 262 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 263 else 264 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 265 } 266 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 267 flags |= IEEE80211_CHAN_NO_80MHZ; 268 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 269 flags |= IEEE80211_CHAN_NO_160MHZ; 270 271 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 272 flags |= IEEE80211_CHAN_NO_IR; 273 274 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 275 flags |= IEEE80211_CHAN_NO_IR; 276 277 if (nvm_flags & NVM_CHANNEL_RADAR) 278 flags |= IEEE80211_CHAN_RADAR; 279 280 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 281 flags |= IEEE80211_CHAN_INDOOR_ONLY; 282 283 /* Set the GO concurrent flag only in case that NO_IR is set. 284 * Otherwise it is meaningless 285 */ 286 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 287 (flags & IEEE80211_CHAN_NO_IR)) 288 flags |= IEEE80211_CHAN_IR_CONCURRENT; 289 290 return flags; 291 } 292 293 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 294 struct iwl_nvm_data *data, 295 const __le16 * const nvm_ch_flags, 296 u32 sbands_flags) 297 { 298 int ch_idx; 299 int n_channels = 0; 300 struct ieee80211_channel *channel; 301 u16 ch_flags; 302 int num_of_ch, num_2ghz_channels; 303 const u8 *nvm_chan; 304 305 if (cfg->nvm_type != IWL_NVM_EXT) { 306 num_of_ch = IWL_NVM_NUM_CHANNELS; 307 nvm_chan = &iwl_nvm_channels[0]; 308 num_2ghz_channels = NUM_2GHZ_CHANNELS; 309 } else { 310 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 311 nvm_chan = &iwl_ext_nvm_channels[0]; 312 num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT; 313 } 314 315 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 316 bool is_5ghz = (ch_idx >= num_2ghz_channels); 317 318 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx); 319 320 if (is_5ghz && !data->sku_cap_band_52ghz_enable) 321 continue; 322 323 /* workaround to disable wide channels in 5GHz */ 324 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 325 is_5ghz) { 326 ch_flags &= ~(NVM_CHANNEL_40MHZ | 327 NVM_CHANNEL_80MHZ | 328 NVM_CHANNEL_160MHZ); 329 } 330 331 if (ch_flags & NVM_CHANNEL_160MHZ) 332 data->vht160_supported = true; 333 334 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 335 !(ch_flags & NVM_CHANNEL_VALID)) { 336 /* 337 * Channels might become valid later if lar is 338 * supported, hence we still want to add them to 339 * the list of supported channels to cfg80211. 340 */ 341 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 342 nvm_chan[ch_idx], ch_flags); 343 continue; 344 } 345 346 channel = &data->channels[n_channels]; 347 n_channels++; 348 349 channel->hw_value = nvm_chan[ch_idx]; 350 channel->band = is_5ghz ? 351 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ; 352 channel->center_freq = 353 ieee80211_channel_to_frequency( 354 channel->hw_value, channel->band); 355 356 /* Initialize regulatory-based run-time data */ 357 358 /* 359 * Default value - highest tx power value. max_power 360 * is not used in mvm, and is used for backwards compatibility 361 */ 362 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 363 364 /* don't put limitations in case we're using LAR */ 365 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 366 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 367 ch_idx, is_5ghz, 368 ch_flags, cfg); 369 else 370 channel->flags = 0; 371 372 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 373 channel->hw_value, ch_flags); 374 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 375 channel->hw_value, channel->max_power); 376 } 377 378 return n_channels; 379 } 380 381 static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg, 382 struct iwl_nvm_data *data, 383 struct ieee80211_sta_vht_cap *vht_cap, 384 u8 tx_chains, u8 rx_chains) 385 { 386 int num_rx_ants = num_of_ant(rx_chains); 387 int num_tx_ants = num_of_ant(tx_chains); 388 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?: 389 IEEE80211_VHT_MAX_AMPDU_1024K); 390 391 vht_cap->vht_supported = true; 392 393 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 394 IEEE80211_VHT_CAP_RXSTBC_1 | 395 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 396 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 397 max_ampdu_exponent << 398 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 399 400 if (data->vht160_supported) 401 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 402 IEEE80211_VHT_CAP_SHORT_GI_160; 403 404 if (cfg->vht_mu_mimo_supported) 405 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 406 407 if (cfg->ht_params->ldpc) 408 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 409 410 if (data->sku_cap_mimo_disabled) { 411 num_rx_ants = 1; 412 num_tx_ants = 1; 413 } 414 415 if (num_tx_ants > 1) 416 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 417 else 418 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 419 420 switch (iwlwifi_mod_params.amsdu_size) { 421 case IWL_AMSDU_DEF: 422 if (cfg->mq_rx_supported) 423 vht_cap->cap |= 424 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 425 else 426 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 427 break; 428 case IWL_AMSDU_2K: 429 if (cfg->mq_rx_supported) 430 vht_cap->cap |= 431 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 432 else 433 WARN(1, "RB size of 2K is not supported by this device\n"); 434 break; 435 case IWL_AMSDU_4K: 436 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 437 break; 438 case IWL_AMSDU_8K: 439 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 440 break; 441 case IWL_AMSDU_12K: 442 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 443 break; 444 default: 445 break; 446 } 447 448 vht_cap->vht_mcs.rx_mcs_map = 449 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 450 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 451 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 452 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 453 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 454 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 455 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 456 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 457 458 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 459 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 460 /* this works because NOT_SUPPORTED == 3 */ 461 vht_cap->vht_mcs.rx_mcs_map |= 462 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 463 } 464 465 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 466 } 467 468 static struct ieee80211_sband_iftype_data iwl_he_capa[] = { 469 { 470 .types_mask = BIT(NL80211_IFTYPE_STATION), 471 .he_cap = { 472 .has_he = true, 473 .he_cap_elem = { 474 .mac_cap_info[0] = 475 IEEE80211_HE_MAC_CAP0_HTC_HE | 476 IEEE80211_HE_MAC_CAP0_TWT_REQ, 477 .mac_cap_info[1] = 478 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 479 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 480 .mac_cap_info[2] = 481 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP | 482 IEEE80211_HE_MAC_CAP2_MU_CASCADING | 483 IEEE80211_HE_MAC_CAP2_ACK_EN, 484 .mac_cap_info[3] = 485 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 486 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 487 .mac_cap_info[4] = 488 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU | 489 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 490 .mac_cap_info[5] = 491 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 492 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 493 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU, 494 .phy_cap_info[0] = 495 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 496 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 497 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 498 .phy_cap_info[1] = 499 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 500 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 501 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 502 IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS, 503 .phy_cap_info[2] = 504 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 505 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 506 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 507 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 508 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO, 509 .phy_cap_info[3] = 510 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 511 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 512 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 513 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 514 .phy_cap_info[4] = 515 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 516 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 517 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 518 .phy_cap_info[5] = 519 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 520 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2 | 521 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 522 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK, 523 .phy_cap_info[6] = 524 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 525 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 526 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB | 527 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB | 528 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 529 IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO | 530 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 531 .phy_cap_info[7] = 532 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR | 533 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 534 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 535 .phy_cap_info[8] = 536 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 537 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 538 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 539 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 540 IEEE80211_HE_PHY_CAP8_DCM_MAX_BW_160_OR_80P80_MHZ, 541 .phy_cap_info[9] = 542 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 543 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 544 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB, 545 }, 546 /* 547 * Set default Tx/Rx HE MCS NSS Support field. 548 * Indicate support for up to 2 spatial streams and all 549 * MCS, without any special cases 550 */ 551 .he_mcs_nss_supp = { 552 .rx_mcs_80 = cpu_to_le16(0xfffa), 553 .tx_mcs_80 = cpu_to_le16(0xfffa), 554 .rx_mcs_160 = cpu_to_le16(0xfffa), 555 .tx_mcs_160 = cpu_to_le16(0xfffa), 556 .rx_mcs_80p80 = cpu_to_le16(0xffff), 557 .tx_mcs_80p80 = cpu_to_le16(0xffff), 558 }, 559 /* 560 * Set default PPE thresholds, with PPET16 set to 0, 561 * PPET8 set to 7 562 */ 563 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 564 }, 565 }, 566 { 567 .types_mask = BIT(NL80211_IFTYPE_AP), 568 .he_cap = { 569 .has_he = true, 570 .he_cap_elem = { 571 .mac_cap_info[0] = 572 IEEE80211_HE_MAC_CAP0_HTC_HE | 573 IEEE80211_HE_MAC_CAP0_TWT_RES, 574 .mac_cap_info[1] = 575 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 576 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 577 .mac_cap_info[2] = 578 IEEE80211_HE_MAC_CAP2_BSR | 579 IEEE80211_HE_MAC_CAP2_MU_CASCADING | 580 IEEE80211_HE_MAC_CAP2_ACK_EN, 581 .mac_cap_info[3] = 582 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 583 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 584 .mac_cap_info[4] = 585 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU, 586 .phy_cap_info[0] = 587 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 588 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 589 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 590 .phy_cap_info[1] = 591 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 592 IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS, 593 .phy_cap_info[2] = 594 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 595 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 596 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 597 .phy_cap_info[3] = 598 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 599 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 600 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 601 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 602 .phy_cap_info[4] = 603 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 604 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 605 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 606 .phy_cap_info[5] = 607 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 608 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2 | 609 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 610 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK, 611 .phy_cap_info[6] = 612 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 613 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 614 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 615 .phy_cap_info[7] = 616 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 617 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 618 .phy_cap_info[8] = 619 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 620 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 621 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 622 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 623 IEEE80211_HE_PHY_CAP8_DCM_MAX_BW_160_OR_80P80_MHZ, 624 .phy_cap_info[9] = 625 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 626 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB, 627 }, 628 /* 629 * Set default Tx/Rx HE MCS NSS Support field. 630 * Indicate support for up to 2 spatial streams and all 631 * MCS, without any special cases 632 */ 633 .he_mcs_nss_supp = { 634 .rx_mcs_80 = cpu_to_le16(0xfffa), 635 .tx_mcs_80 = cpu_to_le16(0xfffa), 636 .rx_mcs_160 = cpu_to_le16(0xfffa), 637 .tx_mcs_160 = cpu_to_le16(0xfffa), 638 .rx_mcs_80p80 = cpu_to_le16(0xffff), 639 .tx_mcs_80p80 = cpu_to_le16(0xffff), 640 }, 641 /* 642 * Set default PPE thresholds, with PPET16 set to 0, 643 * PPET8 set to 7 644 */ 645 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 646 }, 647 }, 648 }; 649 650 static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband, 651 u8 tx_chains, u8 rx_chains) 652 { 653 if (sband->band == NL80211_BAND_2GHZ || 654 sband->band == NL80211_BAND_5GHZ) 655 sband->iftype_data = iwl_he_capa; 656 else 657 return; 658 659 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa); 660 661 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */ 662 if ((tx_chains & rx_chains) != ANT_AB) { 663 int i; 664 665 for (i = 0; i < sband->n_iftype_data; i++) { 666 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &= 667 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 668 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &= 669 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 670 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &= 671 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 672 } 673 } 674 } 675 676 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg, 677 struct iwl_nvm_data *data, 678 const __le16 *nvm_ch_flags, u8 tx_chains, 679 u8 rx_chains, u32 sbands_flags) 680 { 681 int n_channels; 682 int n_used = 0; 683 struct ieee80211_supported_band *sband; 684 685 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 686 sbands_flags); 687 sband = &data->bands[NL80211_BAND_2GHZ]; 688 sband->band = NL80211_BAND_2GHZ; 689 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 690 sband->n_bitrates = N_RATES_24; 691 n_used += iwl_init_sband_channels(data, sband, n_channels, 692 NL80211_BAND_2GHZ); 693 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ, 694 tx_chains, rx_chains); 695 696 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 697 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 698 699 sband = &data->bands[NL80211_BAND_5GHZ]; 700 sband->band = NL80211_BAND_5GHZ; 701 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 702 sband->n_bitrates = N_RATES_52; 703 n_used += iwl_init_sband_channels(data, sband, n_channels, 704 NL80211_BAND_5GHZ); 705 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ, 706 tx_chains, rx_chains); 707 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 708 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap, 709 tx_chains, rx_chains); 710 711 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 712 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 713 714 if (n_channels != n_used) 715 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 716 n_used, n_channels); 717 } 718 719 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 720 const __le16 *phy_sku) 721 { 722 if (cfg->nvm_type != IWL_NVM_EXT) 723 return le16_to_cpup(nvm_sw + SKU); 724 725 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 726 } 727 728 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 729 { 730 if (cfg->nvm_type != IWL_NVM_EXT) 731 return le16_to_cpup(nvm_sw + NVM_VERSION); 732 else 733 return le32_to_cpup((__le32 *)(nvm_sw + 734 NVM_VERSION_EXT_NVM)); 735 } 736 737 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 738 const __le16 *phy_sku) 739 { 740 if (cfg->nvm_type != IWL_NVM_EXT) 741 return le16_to_cpup(nvm_sw + RADIO_CFG); 742 743 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 744 745 } 746 747 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 748 { 749 int n_hw_addr; 750 751 if (cfg->nvm_type != IWL_NVM_EXT) 752 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 753 754 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 755 756 return n_hw_addr & N_HW_ADDR_MASK; 757 } 758 759 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 760 struct iwl_nvm_data *data, 761 u32 radio_cfg) 762 { 763 if (cfg->nvm_type != IWL_NVM_EXT) { 764 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 765 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 766 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 767 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 768 return; 769 } 770 771 /* set the radio configuration for family 8000 */ 772 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 773 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 774 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 775 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 776 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 777 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 778 } 779 780 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 781 { 782 const u8 *hw_addr; 783 784 hw_addr = (const u8 *)&mac_addr0; 785 dest[0] = hw_addr[3]; 786 dest[1] = hw_addr[2]; 787 dest[2] = hw_addr[1]; 788 dest[3] = hw_addr[0]; 789 790 hw_addr = (const u8 *)&mac_addr1; 791 dest[4] = hw_addr[1]; 792 dest[5] = hw_addr[0]; 793 } 794 795 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 796 struct iwl_nvm_data *data) 797 { 798 __le32 mac_addr0 = 799 cpu_to_le32(iwl_read32(trans, 800 trans->cfg->csr->mac_addr0_strap)); 801 __le32 mac_addr1 = 802 cpu_to_le32(iwl_read32(trans, 803 trans->cfg->csr->mac_addr1_strap)); 804 805 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 806 /* 807 * If the OEM fused a valid address, use it instead of the one in the 808 * OTP 809 */ 810 if (is_valid_ether_addr(data->hw_addr)) 811 return; 812 813 mac_addr0 = cpu_to_le32(iwl_read32(trans, 814 trans->cfg->csr->mac_addr0_otp)); 815 mac_addr1 = cpu_to_le32(iwl_read32(trans, 816 trans->cfg->csr->mac_addr1_otp)); 817 818 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 819 } 820 821 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 822 const struct iwl_cfg *cfg, 823 struct iwl_nvm_data *data, 824 const __le16 *mac_override, 825 const __be16 *nvm_hw) 826 { 827 const u8 *hw_addr; 828 829 if (mac_override) { 830 static const u8 reserved_mac[] = { 831 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 832 }; 833 834 hw_addr = (const u8 *)(mac_override + 835 MAC_ADDRESS_OVERRIDE_EXT_NVM); 836 837 /* 838 * Store the MAC address from MAO section. 839 * No byte swapping is required in MAO section 840 */ 841 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 842 843 /* 844 * Force the use of the OTP MAC address in case of reserved MAC 845 * address in the NVM, or if address is given but invalid. 846 */ 847 if (is_valid_ether_addr(data->hw_addr) && 848 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 849 return; 850 851 IWL_ERR(trans, 852 "mac address from nvm override section is not valid\n"); 853 } 854 855 if (nvm_hw) { 856 /* read the mac address from WFMP registers */ 857 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 858 WFMP_MAC_ADDR_0)); 859 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 860 WFMP_MAC_ADDR_1)); 861 862 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 863 864 return; 865 } 866 867 IWL_ERR(trans, "mac address is not found\n"); 868 } 869 870 static int iwl_set_hw_address(struct iwl_trans *trans, 871 const struct iwl_cfg *cfg, 872 struct iwl_nvm_data *data, const __be16 *nvm_hw, 873 const __le16 *mac_override) 874 { 875 if (cfg->mac_addr_from_csr) { 876 iwl_set_hw_address_from_csr(trans, data); 877 } else if (cfg->nvm_type != IWL_NVM_EXT) { 878 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 879 880 /* The byte order is little endian 16 bit, meaning 214365 */ 881 data->hw_addr[0] = hw_addr[1]; 882 data->hw_addr[1] = hw_addr[0]; 883 data->hw_addr[2] = hw_addr[3]; 884 data->hw_addr[3] = hw_addr[2]; 885 data->hw_addr[4] = hw_addr[5]; 886 data->hw_addr[5] = hw_addr[4]; 887 } else { 888 iwl_set_hw_address_family_8000(trans, cfg, data, 889 mac_override, nvm_hw); 890 } 891 892 if (!is_valid_ether_addr(data->hw_addr)) { 893 IWL_ERR(trans, "no valid mac address was found\n"); 894 return -EINVAL; 895 } 896 897 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 898 899 return 0; 900 } 901 902 static bool 903 iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg, 904 const __be16 *nvm_hw) 905 { 906 /* 907 * Workaround a bug in Indonesia SKUs where the regulatory in 908 * some 7000-family OTPs erroneously allow wide channels in 909 * 5GHz. To check for Indonesia, we take the SKU value from 910 * bits 1-4 in the subsystem ID and check if it is either 5 or 911 * 9. In those cases, we need to force-disable wide channels 912 * in 5GHz otherwise the FW will throw a sysassert when we try 913 * to use them. 914 */ 915 if (cfg->device_family == IWL_DEVICE_FAMILY_7000) { 916 /* 917 * Unlike the other sections in the NVM, the hw 918 * section uses big-endian. 919 */ 920 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 921 u8 sku = (subsystem_id & 0x1e) >> 1; 922 923 if (sku == 5 || sku == 9) { 924 IWL_DEBUG_EEPROM(dev, 925 "disabling wide channels in 5GHz (0x%0x %d)\n", 926 subsystem_id, sku); 927 return true; 928 } 929 } 930 931 return false; 932 } 933 934 struct iwl_nvm_data * 935 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 936 const __be16 *nvm_hw, const __le16 *nvm_sw, 937 const __le16 *nvm_calib, const __le16 *regulatory, 938 const __le16 *mac_override, const __le16 *phy_sku, 939 u8 tx_chains, u8 rx_chains, bool lar_fw_supported) 940 { 941 struct device *dev = trans->dev; 942 struct iwl_nvm_data *data; 943 bool lar_enabled; 944 u32 sku, radio_cfg; 945 u32 sbands_flags = 0; 946 u16 lar_config; 947 const __le16 *ch_section; 948 949 if (cfg->nvm_type != IWL_NVM_EXT) 950 data = kzalloc(sizeof(*data) + 951 sizeof(struct ieee80211_channel) * 952 IWL_NVM_NUM_CHANNELS, 953 GFP_KERNEL); 954 else 955 data = kzalloc(sizeof(*data) + 956 sizeof(struct ieee80211_channel) * 957 IWL_NVM_NUM_CHANNELS_EXT, 958 GFP_KERNEL); 959 if (!data) 960 return NULL; 961 962 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 963 964 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 965 iwl_set_radio_cfg(cfg, data, radio_cfg); 966 if (data->valid_tx_ant) 967 tx_chains &= data->valid_tx_ant; 968 if (data->valid_rx_ant) 969 rx_chains &= data->valid_rx_ant; 970 971 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 972 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 973 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 974 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 975 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 976 data->sku_cap_11n_enable = false; 977 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 978 (sku & NVM_SKU_CAP_11AC_ENABLE); 979 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 980 981 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 982 983 if (cfg->nvm_type != IWL_NVM_EXT) { 984 /* Checking for required sections */ 985 if (!nvm_calib) { 986 IWL_ERR(trans, 987 "Can't parse empty Calib NVM sections\n"); 988 kfree(data); 989 return NULL; 990 } 991 992 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 993 ®ulatory[NVM_CHANNELS_SDP] : 994 &nvm_sw[NVM_CHANNELS]; 995 996 /* in family 8000 Xtal calibration values moved to OTP */ 997 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 998 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 999 lar_enabled = true; 1000 } else { 1001 u16 lar_offset = data->nvm_version < 0xE39 ? 1002 NVM_LAR_OFFSET_OLD : 1003 NVM_LAR_OFFSET; 1004 1005 lar_config = le16_to_cpup(regulatory + lar_offset); 1006 data->lar_enabled = !!(lar_config & 1007 NVM_LAR_ENABLED); 1008 lar_enabled = data->lar_enabled; 1009 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1010 } 1011 1012 /* If no valid mac address was found - bail out */ 1013 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1014 kfree(data); 1015 return NULL; 1016 } 1017 1018 if (lar_fw_supported && lar_enabled) 1019 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1020 1021 if (iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw)) 1022 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1023 1024 iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains, 1025 sbands_flags); 1026 data->calib_version = 255; 1027 1028 return data; 1029 } 1030 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1031 1032 static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan, 1033 int ch_idx, u16 nvm_flags, 1034 const struct iwl_cfg *cfg) 1035 { 1036 u32 flags = NL80211_RRF_NO_HT40; 1037 u32 last_5ghz_ht = LAST_5GHZ_HT; 1038 1039 if (cfg->nvm_type == IWL_NVM_EXT) 1040 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 1041 1042 if (ch_idx < NUM_2GHZ_CHANNELS && 1043 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1044 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1045 flags &= ~NL80211_RRF_NO_HT40PLUS; 1046 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1047 flags &= ~NL80211_RRF_NO_HT40MINUS; 1048 } else if (nvm_chan[ch_idx] <= last_5ghz_ht && 1049 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1050 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1051 flags &= ~NL80211_RRF_NO_HT40PLUS; 1052 else 1053 flags &= ~NL80211_RRF_NO_HT40MINUS; 1054 } 1055 1056 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1057 flags |= NL80211_RRF_NO_80MHZ; 1058 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1059 flags |= NL80211_RRF_NO_160MHZ; 1060 1061 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1062 flags |= NL80211_RRF_NO_IR; 1063 1064 if (nvm_flags & NVM_CHANNEL_RADAR) 1065 flags |= NL80211_RRF_DFS; 1066 1067 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1068 flags |= NL80211_RRF_NO_OUTDOOR; 1069 1070 /* Set the GO concurrent flag only in case that NO_IR is set. 1071 * Otherwise it is meaningless 1072 */ 1073 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1074 (flags & NL80211_RRF_NO_IR)) 1075 flags |= NL80211_RRF_GO_CONCURRENT; 1076 1077 return flags; 1078 } 1079 1080 struct regdb_ptrs { 1081 struct ieee80211_wmm_rule *rule; 1082 u32 token; 1083 }; 1084 1085 struct ieee80211_regdomain * 1086 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1087 int num_of_ch, __le32 *channels, u16 fw_mcc, 1088 u16 geo_info) 1089 { 1090 int ch_idx; 1091 u16 ch_flags; 1092 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1093 const u8 *nvm_chan = cfg->nvm_type == IWL_NVM_EXT ? 1094 iwl_ext_nvm_channels : iwl_nvm_channels; 1095 struct ieee80211_regdomain *regd, *copy_rd; 1096 int size_of_regd, regd_to_copy; 1097 struct ieee80211_reg_rule *rule; 1098 struct regdb_ptrs *regdb_ptrs; 1099 enum nl80211_band band; 1100 int center_freq, prev_center_freq = 0; 1101 int valid_rules = 0; 1102 bool new_rule; 1103 int max_num_ch = cfg->nvm_type == IWL_NVM_EXT ? 1104 IWL_NVM_NUM_CHANNELS_EXT : IWL_NVM_NUM_CHANNELS; 1105 1106 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1107 return ERR_PTR(-EINVAL); 1108 1109 if (WARN_ON(num_of_ch > max_num_ch)) 1110 num_of_ch = max_num_ch; 1111 1112 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1113 num_of_ch); 1114 1115 /* build a regdomain rule for every valid channel */ 1116 size_of_regd = 1117 sizeof(struct ieee80211_regdomain) + 1118 num_of_ch * sizeof(struct ieee80211_reg_rule); 1119 1120 regd = kzalloc(size_of_regd, GFP_KERNEL); 1121 if (!regd) 1122 return ERR_PTR(-ENOMEM); 1123 1124 regdb_ptrs = kcalloc(num_of_ch, sizeof(*regdb_ptrs), GFP_KERNEL); 1125 if (!regdb_ptrs) { 1126 copy_rd = ERR_PTR(-ENOMEM); 1127 goto out; 1128 } 1129 1130 /* set alpha2 from FW. */ 1131 regd->alpha2[0] = fw_mcc >> 8; 1132 regd->alpha2[1] = fw_mcc & 0xff; 1133 1134 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1135 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1136 band = (ch_idx < NUM_2GHZ_CHANNELS) ? 1137 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1138 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1139 band); 1140 new_rule = false; 1141 1142 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1143 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1144 nvm_chan[ch_idx], ch_flags); 1145 continue; 1146 } 1147 1148 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1149 ch_flags, cfg); 1150 1151 /* we can't continue the same rule */ 1152 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1153 center_freq - prev_center_freq > 20) { 1154 valid_rules++; 1155 new_rule = true; 1156 } 1157 1158 rule = ®d->reg_rules[valid_rules - 1]; 1159 1160 if (new_rule) 1161 rule->freq_range.start_freq_khz = 1162 MHZ_TO_KHZ(center_freq - 10); 1163 1164 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1165 1166 /* this doesn't matter - not used by FW */ 1167 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1168 rule->power_rule.max_eirp = 1169 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1170 1171 rule->flags = reg_rule_flags; 1172 1173 /* rely on auto-calculation to merge BW of contiguous chans */ 1174 rule->flags |= NL80211_RRF_AUTO_BW; 1175 rule->freq_range.max_bandwidth_khz = 0; 1176 1177 prev_center_freq = center_freq; 1178 prev_reg_rule_flags = reg_rule_flags; 1179 1180 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1181 nvm_chan[ch_idx], ch_flags); 1182 1183 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1184 band == NL80211_BAND_2GHZ) 1185 continue; 1186 1187 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1188 } 1189 1190 regd->n_reg_rules = valid_rules; 1191 1192 /* 1193 * Narrow down regdom for unused regulatory rules to prevent hole 1194 * between reg rules to wmm rules. 1195 */ 1196 regd_to_copy = sizeof(struct ieee80211_regdomain) + 1197 valid_rules * sizeof(struct ieee80211_reg_rule); 1198 1199 copy_rd = kzalloc(regd_to_copy, GFP_KERNEL); 1200 if (!copy_rd) { 1201 copy_rd = ERR_PTR(-ENOMEM); 1202 goto out; 1203 } 1204 1205 memcpy(copy_rd, regd, regd_to_copy); 1206 1207 out: 1208 kfree(regdb_ptrs); 1209 kfree(regd); 1210 return copy_rd; 1211 } 1212 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1213 1214 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1215 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1216 #define MAX_NVM_FILE_LEN 16384 1217 1218 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1219 unsigned int len) 1220 { 1221 #define IWL_4165_DEVICE_ID 0x5501 1222 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1223 1224 if (section == NVM_SECTION_TYPE_PHY_SKU && 1225 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1226 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1227 /* OTP 0x52 bug work around: it's a 1x1 device */ 1228 data[3] = ANT_B | (ANT_B << 4); 1229 } 1230 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1231 1232 /* 1233 * Reads external NVM from a file into mvm->nvm_sections 1234 * 1235 * HOW TO CREATE THE NVM FILE FORMAT: 1236 * ------------------------------ 1237 * 1. create hex file, format: 1238 * 3800 -> header 1239 * 0000 -> header 1240 * 5a40 -> data 1241 * 1242 * rev - 6 bit (word1) 1243 * len - 10 bit (word1) 1244 * id - 4 bit (word2) 1245 * rsv - 12 bit (word2) 1246 * 1247 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1248 * 1249 * 3. create binary file from the hex file 1250 * 1251 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1252 */ 1253 int iwl_read_external_nvm(struct iwl_trans *trans, 1254 const char *nvm_file_name, 1255 struct iwl_nvm_section *nvm_sections) 1256 { 1257 int ret, section_size; 1258 u16 section_id; 1259 const struct firmware *fw_entry; 1260 const struct { 1261 __le16 word1; 1262 __le16 word2; 1263 u8 data[]; 1264 } *file_sec; 1265 const u8 *eof; 1266 u8 *temp; 1267 int max_section_size; 1268 const __le32 *dword_buff; 1269 1270 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1271 #define NVM_WORD2_ID(x) (x >> 12) 1272 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1273 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1274 #define NVM_HEADER_0 (0x2A504C54) 1275 #define NVM_HEADER_1 (0x4E564D2A) 1276 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1277 1278 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1279 1280 /* Maximal size depends on NVM version */ 1281 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1282 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1283 else 1284 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1285 1286 /* 1287 * Obtain NVM image via request_firmware. Since we already used 1288 * request_firmware_nowait() for the firmware binary load and only 1289 * get here after that we assume the NVM request can be satisfied 1290 * synchronously. 1291 */ 1292 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1293 if (ret) { 1294 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1295 nvm_file_name, ret); 1296 return ret; 1297 } 1298 1299 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1300 nvm_file_name, fw_entry->size); 1301 1302 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1303 IWL_ERR(trans, "NVM file too large\n"); 1304 ret = -EINVAL; 1305 goto out; 1306 } 1307 1308 eof = fw_entry->data + fw_entry->size; 1309 dword_buff = (__le32 *)fw_entry->data; 1310 1311 /* some NVM file will contain a header. 1312 * The header is identified by 2 dwords header as follow: 1313 * dword[0] = 0x2A504C54 1314 * dword[1] = 0x4E564D2A 1315 * 1316 * This header must be skipped when providing the NVM data to the FW. 1317 */ 1318 if (fw_entry->size > NVM_HEADER_SIZE && 1319 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1320 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1321 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1322 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1323 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1324 le32_to_cpu(dword_buff[3])); 1325 1326 /* nvm file validation, dword_buff[2] holds the file version */ 1327 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1328 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP && 1329 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1330 ret = -EFAULT; 1331 goto out; 1332 } 1333 } else { 1334 file_sec = (void *)fw_entry->data; 1335 } 1336 1337 while (true) { 1338 if (file_sec->data > eof) { 1339 IWL_ERR(trans, 1340 "ERROR - NVM file too short for section header\n"); 1341 ret = -EINVAL; 1342 break; 1343 } 1344 1345 /* check for EOF marker */ 1346 if (!file_sec->word1 && !file_sec->word2) { 1347 ret = 0; 1348 break; 1349 } 1350 1351 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1352 section_size = 1353 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1354 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1355 } else { 1356 section_size = 2 * EXT_NVM_WORD2_LEN( 1357 le16_to_cpu(file_sec->word2)); 1358 section_id = EXT_NVM_WORD1_ID( 1359 le16_to_cpu(file_sec->word1)); 1360 } 1361 1362 if (section_size > max_section_size) { 1363 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1364 section_size); 1365 ret = -EINVAL; 1366 break; 1367 } 1368 1369 if (!section_size) { 1370 IWL_ERR(trans, "ERROR - section empty\n"); 1371 ret = -EINVAL; 1372 break; 1373 } 1374 1375 if (file_sec->data + section_size > eof) { 1376 IWL_ERR(trans, 1377 "ERROR - NVM file too short for section (%d bytes)\n", 1378 section_size); 1379 ret = -EINVAL; 1380 break; 1381 } 1382 1383 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1384 "Invalid NVM section ID %d\n", section_id)) { 1385 ret = -EINVAL; 1386 break; 1387 } 1388 1389 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1390 if (!temp) { 1391 ret = -ENOMEM; 1392 break; 1393 } 1394 1395 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1396 1397 kfree(nvm_sections[section_id].data); 1398 nvm_sections[section_id].data = temp; 1399 nvm_sections[section_id].length = section_size; 1400 1401 /* advance to the next section */ 1402 file_sec = (void *)(file_sec->data + section_size); 1403 } 1404 out: 1405 release_firmware(fw_entry); 1406 return ret; 1407 } 1408 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1409 1410 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1411 const struct iwl_fw *fw) 1412 { 1413 struct iwl_nvm_get_info cmd = {}; 1414 struct iwl_nvm_get_info_rsp *rsp; 1415 struct iwl_nvm_data *nvm; 1416 struct iwl_host_cmd hcmd = { 1417 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1418 .data = { &cmd, }, 1419 .len = { sizeof(cmd) }, 1420 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1421 }; 1422 int ret; 1423 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable && 1424 fw_has_capa(&fw->ucode_capa, 1425 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 1426 bool empty_otp; 1427 u32 mac_flags; 1428 u32 sbands_flags = 0; 1429 1430 ret = iwl_trans_send_cmd(trans, &hcmd); 1431 if (ret) 1432 return ERR_PTR(ret); 1433 1434 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp), 1435 "Invalid payload len in NVM response from FW %d", 1436 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1437 ret = -EINVAL; 1438 goto out; 1439 } 1440 1441 rsp = (void *)hcmd.resp_pkt->data; 1442 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1443 NVM_GENERAL_FLAGS_EMPTY_OTP); 1444 if (empty_otp) 1445 IWL_INFO(trans, "OTP is empty\n"); 1446 1447 nvm = kzalloc(sizeof(*nvm) + 1448 sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS, 1449 GFP_KERNEL); 1450 if (!nvm) { 1451 ret = -ENOMEM; 1452 goto out; 1453 } 1454 1455 iwl_set_hw_address_from_csr(trans, nvm); 1456 /* TODO: if platform NVM has MAC address - override it here */ 1457 1458 if (!is_valid_ether_addr(nvm->hw_addr)) { 1459 IWL_ERR(trans, "no valid mac address was found\n"); 1460 ret = -EINVAL; 1461 goto err_free; 1462 } 1463 1464 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1465 1466 /* Initialize general data */ 1467 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1468 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1469 if (nvm->n_hw_addrs == 0) 1470 IWL_WARN(trans, 1471 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1472 empty_otp); 1473 1474 /* Initialize MAC sku data */ 1475 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1476 nvm->sku_cap_11ac_enable = 1477 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1478 nvm->sku_cap_11n_enable = 1479 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1480 nvm->sku_cap_11ax_enable = 1481 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1482 nvm->sku_cap_band_24ghz_enable = 1483 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1484 nvm->sku_cap_band_52ghz_enable = 1485 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1486 nvm->sku_cap_mimo_disabled = 1487 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1488 1489 /* Initialize PHY sku data */ 1490 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1491 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1492 1493 if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) { 1494 nvm->lar_enabled = true; 1495 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1496 } 1497 1498 iwl_init_sbands(trans->dev, trans->cfg, nvm, 1499 rsp->regulatory.channel_profile, 1500 nvm->valid_tx_ant & fw->valid_tx_ant, 1501 nvm->valid_rx_ant & fw->valid_rx_ant, 1502 sbands_flags); 1503 1504 iwl_free_resp(&hcmd); 1505 return nvm; 1506 1507 err_free: 1508 kfree(nvm); 1509 out: 1510 iwl_free_resp(&hcmd); 1511 return ERR_PTR(ret); 1512 } 1513 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1514