1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <linuxwifi@intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 38 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 39 * Copyright(c) 2018 Intel Corporation 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 46 * * Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * * Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in 50 * the documentation and/or other materials provided with the 51 * distribution. 52 * * Neither the name Intel Corporation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 57 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 59 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 60 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 61 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 62 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 66 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 *****************************************************************************/ 68 #include <linux/types.h> 69 #include <linux/slab.h> 70 #include <linux/export.h> 71 #include <linux/etherdevice.h> 72 #include <linux/pci.h> 73 #include <linux/firmware.h> 74 75 #include "iwl-drv.h" 76 #include "iwl-modparams.h" 77 #include "iwl-nvm-parse.h" 78 #include "iwl-prph.h" 79 #include "iwl-io.h" 80 #include "iwl-csr.h" 81 #include "fw/acpi.h" 82 #include "fw/api/nvm-reg.h" 83 #include "fw/api/commands.h" 84 #include "fw/api/cmdhdr.h" 85 #include "fw/img.h" 86 87 /* NVM offsets (in words) definitions */ 88 enum nvm_offsets { 89 /* NVM HW-Section offset (in words) definitions */ 90 SUBSYSTEM_ID = 0x0A, 91 HW_ADDR = 0x15, 92 93 /* NVM SW-Section offset (in words) definitions */ 94 NVM_SW_SECTION = 0x1C0, 95 NVM_VERSION = 0, 96 RADIO_CFG = 1, 97 SKU = 2, 98 N_HW_ADDRS = 3, 99 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 100 101 /* NVM calibration section offset (in words) definitions */ 102 NVM_CALIB_SECTION = 0x2B8, 103 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 104 105 /* NVM REGULATORY -Section offset (in words) definitions */ 106 NVM_CHANNELS_SDP = 0, 107 }; 108 109 enum ext_nvm_offsets { 110 /* NVM HW-Section offset (in words) definitions */ 111 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 112 113 /* NVM SW-Section offset (in words) definitions */ 114 NVM_VERSION_EXT_NVM = 0, 115 RADIO_CFG_FAMILY_EXT_NVM = 0, 116 SKU_FAMILY_8000 = 2, 117 N_HW_ADDRS_FAMILY_8000 = 3, 118 119 /* NVM REGULATORY -Section offset (in words) definitions */ 120 NVM_CHANNELS_EXTENDED = 0, 121 NVM_LAR_OFFSET_OLD = 0x4C7, 122 NVM_LAR_OFFSET = 0x507, 123 NVM_LAR_ENABLED = 0x7, 124 }; 125 126 /* SKU Capabilities (actual values from NVM definition) */ 127 enum nvm_sku_bits { 128 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 129 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 130 NVM_SKU_CAP_11N_ENABLE = BIT(2), 131 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 132 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 133 }; 134 135 /* 136 * These are the channel numbers in the order that they are stored in the NVM 137 */ 138 static const u8 iwl_nvm_channels[] = { 139 /* 2.4 GHz */ 140 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 141 /* 5 GHz */ 142 36, 40, 44 , 48, 52, 56, 60, 64, 143 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 144 149, 153, 157, 161, 165 145 }; 146 147 static const u8 iwl_ext_nvm_channels[] = { 148 /* 2.4 GHz */ 149 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 150 /* 5 GHz */ 151 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 152 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 153 149, 153, 157, 161, 165, 169, 173, 177, 181 154 }; 155 156 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 157 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 158 #define NUM_2GHZ_CHANNELS 14 159 #define NUM_2GHZ_CHANNELS_EXT 14 160 #define FIRST_2GHZ_HT_MINUS 5 161 #define LAST_2GHZ_HT_PLUS 9 162 #define LAST_5GHZ_HT 165 163 #define LAST_5GHZ_HT_FAMILY_8000 181 164 #define N_HW_ADDR_MASK 0xF 165 166 /* rate data (static) */ 167 static struct ieee80211_rate iwl_cfg80211_rates[] = { 168 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 169 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 170 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 171 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 172 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 173 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 174 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 175 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 176 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 177 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 178 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 179 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 180 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 181 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 182 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 183 }; 184 #define RATES_24_OFFS 0 185 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 186 #define RATES_52_OFFS 4 187 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 188 189 /** 190 * enum iwl_nvm_channel_flags - channel flags in NVM 191 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 192 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 193 * @NVM_CHANNEL_ACTIVE: active scanning allowed 194 * @NVM_CHANNEL_RADAR: radar detection required 195 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 196 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 197 * on same channel on 2.4 or same UNII band on 5.2 198 * @NVM_CHANNEL_UNIFORM: uniform spreading required 199 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 200 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 201 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 202 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 203 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 204 */ 205 enum iwl_nvm_channel_flags { 206 NVM_CHANNEL_VALID = BIT(0), 207 NVM_CHANNEL_IBSS = BIT(1), 208 NVM_CHANNEL_ACTIVE = BIT(3), 209 NVM_CHANNEL_RADAR = BIT(4), 210 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 211 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 212 NVM_CHANNEL_UNIFORM = BIT(7), 213 NVM_CHANNEL_20MHZ = BIT(8), 214 NVM_CHANNEL_40MHZ = BIT(9), 215 NVM_CHANNEL_80MHZ = BIT(10), 216 NVM_CHANNEL_160MHZ = BIT(11), 217 NVM_CHANNEL_DC_HIGH = BIT(12), 218 }; 219 220 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 221 int chan, u16 flags) 222 { 223 #define CHECK_AND_PRINT_I(x) \ 224 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 225 226 if (!(flags & NVM_CHANNEL_VALID)) { 227 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 228 chan, flags); 229 return; 230 } 231 232 /* Note: already can print up to 101 characters, 110 is the limit! */ 233 IWL_DEBUG_DEV(dev, level, 234 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 235 chan, flags, 236 CHECK_AND_PRINT_I(VALID), 237 CHECK_AND_PRINT_I(IBSS), 238 CHECK_AND_PRINT_I(ACTIVE), 239 CHECK_AND_PRINT_I(RADAR), 240 CHECK_AND_PRINT_I(INDOOR_ONLY), 241 CHECK_AND_PRINT_I(GO_CONCURRENT), 242 CHECK_AND_PRINT_I(UNIFORM), 243 CHECK_AND_PRINT_I(20MHZ), 244 CHECK_AND_PRINT_I(40MHZ), 245 CHECK_AND_PRINT_I(80MHZ), 246 CHECK_AND_PRINT_I(160MHZ), 247 CHECK_AND_PRINT_I(DC_HIGH)); 248 #undef CHECK_AND_PRINT_I 249 } 250 251 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz, 252 u16 nvm_flags, const struct iwl_cfg *cfg) 253 { 254 u32 flags = IEEE80211_CHAN_NO_HT40; 255 u32 last_5ghz_ht = LAST_5GHZ_HT; 256 257 if (cfg->nvm_type == IWL_NVM_EXT) 258 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 259 260 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) { 261 if (ch_num <= LAST_2GHZ_HT_PLUS) 262 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 263 if (ch_num >= FIRST_2GHZ_HT_MINUS) 264 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 265 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) { 266 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 267 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 268 else 269 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 270 } 271 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 272 flags |= IEEE80211_CHAN_NO_80MHZ; 273 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 274 flags |= IEEE80211_CHAN_NO_160MHZ; 275 276 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 277 flags |= IEEE80211_CHAN_NO_IR; 278 279 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 280 flags |= IEEE80211_CHAN_NO_IR; 281 282 if (nvm_flags & NVM_CHANNEL_RADAR) 283 flags |= IEEE80211_CHAN_RADAR; 284 285 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 286 flags |= IEEE80211_CHAN_INDOOR_ONLY; 287 288 /* Set the GO concurrent flag only in case that NO_IR is set. 289 * Otherwise it is meaningless 290 */ 291 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 292 (flags & IEEE80211_CHAN_NO_IR)) 293 flags |= IEEE80211_CHAN_IR_CONCURRENT; 294 295 return flags; 296 } 297 298 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 299 struct iwl_nvm_data *data, 300 const __le16 * const nvm_ch_flags, 301 u32 sbands_flags) 302 { 303 int ch_idx; 304 int n_channels = 0; 305 struct ieee80211_channel *channel; 306 u16 ch_flags; 307 int num_of_ch, num_2ghz_channels; 308 const u8 *nvm_chan; 309 310 if (cfg->nvm_type != IWL_NVM_EXT) { 311 num_of_ch = IWL_NVM_NUM_CHANNELS; 312 nvm_chan = &iwl_nvm_channels[0]; 313 num_2ghz_channels = NUM_2GHZ_CHANNELS; 314 } else { 315 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 316 nvm_chan = &iwl_ext_nvm_channels[0]; 317 num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT; 318 } 319 320 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 321 bool is_5ghz = (ch_idx >= num_2ghz_channels); 322 323 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx); 324 325 if (is_5ghz && !data->sku_cap_band_52ghz_enable) 326 continue; 327 328 /* workaround to disable wide channels in 5GHz */ 329 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 330 is_5ghz) { 331 ch_flags &= ~(NVM_CHANNEL_40MHZ | 332 NVM_CHANNEL_80MHZ | 333 NVM_CHANNEL_160MHZ); 334 } 335 336 if (ch_flags & NVM_CHANNEL_160MHZ) 337 data->vht160_supported = true; 338 339 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 340 !(ch_flags & NVM_CHANNEL_VALID)) { 341 /* 342 * Channels might become valid later if lar is 343 * supported, hence we still want to add them to 344 * the list of supported channels to cfg80211. 345 */ 346 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 347 nvm_chan[ch_idx], ch_flags); 348 continue; 349 } 350 351 channel = &data->channels[n_channels]; 352 n_channels++; 353 354 channel->hw_value = nvm_chan[ch_idx]; 355 channel->band = is_5ghz ? 356 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ; 357 channel->center_freq = 358 ieee80211_channel_to_frequency( 359 channel->hw_value, channel->band); 360 361 /* Initialize regulatory-based run-time data */ 362 363 /* 364 * Default value - highest tx power value. max_power 365 * is not used in mvm, and is used for backwards compatibility 366 */ 367 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 368 369 /* don't put limitations in case we're using LAR */ 370 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 371 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 372 ch_idx, is_5ghz, 373 ch_flags, cfg); 374 else 375 channel->flags = 0; 376 377 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 378 channel->hw_value, ch_flags); 379 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 380 channel->hw_value, channel->max_power); 381 } 382 383 return n_channels; 384 } 385 386 static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg, 387 struct iwl_nvm_data *data, 388 struct ieee80211_sta_vht_cap *vht_cap, 389 u8 tx_chains, u8 rx_chains) 390 { 391 int num_rx_ants = num_of_ant(rx_chains); 392 int num_tx_ants = num_of_ant(tx_chains); 393 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?: 394 IEEE80211_VHT_MAX_AMPDU_1024K); 395 396 vht_cap->vht_supported = true; 397 398 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 399 IEEE80211_VHT_CAP_RXSTBC_1 | 400 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 401 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 402 max_ampdu_exponent << 403 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 404 405 if (data->vht160_supported) 406 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 407 IEEE80211_VHT_CAP_SHORT_GI_160; 408 409 if (cfg->vht_mu_mimo_supported) 410 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 411 412 if (cfg->ht_params->ldpc) 413 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 414 415 if (data->sku_cap_mimo_disabled) { 416 num_rx_ants = 1; 417 num_tx_ants = 1; 418 } 419 420 if (num_tx_ants > 1) 421 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 422 else 423 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 424 425 switch (iwlwifi_mod_params.amsdu_size) { 426 case IWL_AMSDU_DEF: 427 if (cfg->mq_rx_supported) 428 vht_cap->cap |= 429 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 430 else 431 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 432 break; 433 case IWL_AMSDU_2K: 434 if (cfg->mq_rx_supported) 435 vht_cap->cap |= 436 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 437 else 438 WARN(1, "RB size of 2K is not supported by this device\n"); 439 break; 440 case IWL_AMSDU_4K: 441 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 442 break; 443 case IWL_AMSDU_8K: 444 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 445 break; 446 case IWL_AMSDU_12K: 447 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 448 break; 449 default: 450 break; 451 } 452 453 vht_cap->vht_mcs.rx_mcs_map = 454 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 455 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 456 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 457 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 458 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 459 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 460 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 461 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 462 463 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 464 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 465 /* this works because NOT_SUPPORTED == 3 */ 466 vht_cap->vht_mcs.rx_mcs_map |= 467 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 468 } 469 470 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 471 } 472 473 static struct ieee80211_sband_iftype_data iwl_he_capa = { 474 .types_mask = BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP), 475 .he_cap = { 476 .has_he = true, 477 .he_cap_elem = { 478 .mac_cap_info[0] = 479 IEEE80211_HE_MAC_CAP0_HTC_HE | 480 IEEE80211_HE_MAC_CAP0_TWT_REQ, 481 .mac_cap_info[1] = 482 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 483 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 484 .mac_cap_info[2] = 485 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP | 486 IEEE80211_HE_MAC_CAP2_MU_CASCADING | 487 IEEE80211_HE_MAC_CAP2_ACK_EN, 488 .mac_cap_info[3] = 489 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 490 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 491 .mac_cap_info[4] = 492 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU | 493 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 494 .mac_cap_info[5] = 495 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 496 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 497 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU, 498 .phy_cap_info[0] = 499 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 500 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 501 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 502 .phy_cap_info[1] = 503 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 504 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 505 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 506 IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS, 507 .phy_cap_info[2] = 508 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 509 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 510 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 511 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 512 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO, 513 .phy_cap_info[3] = 514 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 515 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 516 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 517 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 518 .phy_cap_info[4] = 519 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 520 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 521 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 522 .phy_cap_info[5] = 523 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 524 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2 | 525 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 526 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK, 527 .phy_cap_info[6] = 528 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 529 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 530 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB | 531 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB | 532 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 533 IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO | 534 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 535 .phy_cap_info[7] = 536 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR | 537 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 538 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 539 .phy_cap_info[8] = 540 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 541 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 542 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 543 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 544 IEEE80211_HE_PHY_CAP8_DCM_MAX_BW_160_OR_80P80_MHZ, 545 .phy_cap_info[9] = 546 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 547 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 548 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB, 549 }, 550 /* 551 * Set default Tx/Rx HE MCS NSS Support field. Indicate support 552 * for up to 2 spatial streams and all MCS, without any special 553 * cases 554 */ 555 .he_mcs_nss_supp = { 556 .rx_mcs_80 = cpu_to_le16(0xfffa), 557 .tx_mcs_80 = cpu_to_le16(0xfffa), 558 .rx_mcs_160 = cpu_to_le16(0xfffa), 559 .tx_mcs_160 = cpu_to_le16(0xfffa), 560 .rx_mcs_80p80 = cpu_to_le16(0xffff), 561 .tx_mcs_80p80 = cpu_to_le16(0xffff), 562 }, 563 /* 564 * Set default PPE thresholds, with PPET16 set to 0, PPET8 set 565 * to 7 566 */ 567 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 568 }, 569 }; 570 571 static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband, 572 u8 tx_chains, u8 rx_chains) 573 { 574 if (sband->band == NL80211_BAND_2GHZ || 575 sband->band == NL80211_BAND_5GHZ) 576 sband->iftype_data = &iwl_he_capa; 577 else 578 return; 579 580 sband->n_iftype_data = 1; 581 582 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */ 583 if ((tx_chains & rx_chains) != ANT_AB) { 584 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[1] &= 585 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 586 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[2] &= 587 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 588 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[7] &= 589 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 590 } 591 } 592 593 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg, 594 struct iwl_nvm_data *data, 595 const __le16 *nvm_ch_flags, u8 tx_chains, 596 u8 rx_chains, u32 sbands_flags) 597 { 598 int n_channels; 599 int n_used = 0; 600 struct ieee80211_supported_band *sband; 601 602 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 603 sbands_flags); 604 sband = &data->bands[NL80211_BAND_2GHZ]; 605 sband->band = NL80211_BAND_2GHZ; 606 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 607 sband->n_bitrates = N_RATES_24; 608 n_used += iwl_init_sband_channels(data, sband, n_channels, 609 NL80211_BAND_2GHZ); 610 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ, 611 tx_chains, rx_chains); 612 613 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 614 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 615 616 sband = &data->bands[NL80211_BAND_5GHZ]; 617 sband->band = NL80211_BAND_5GHZ; 618 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 619 sband->n_bitrates = N_RATES_52; 620 n_used += iwl_init_sband_channels(data, sband, n_channels, 621 NL80211_BAND_5GHZ); 622 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ, 623 tx_chains, rx_chains); 624 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 625 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap, 626 tx_chains, rx_chains); 627 628 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 629 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 630 631 if (n_channels != n_used) 632 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 633 n_used, n_channels); 634 } 635 636 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 637 const __le16 *phy_sku) 638 { 639 if (cfg->nvm_type != IWL_NVM_EXT) 640 return le16_to_cpup(nvm_sw + SKU); 641 642 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 643 } 644 645 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 646 { 647 if (cfg->nvm_type != IWL_NVM_EXT) 648 return le16_to_cpup(nvm_sw + NVM_VERSION); 649 else 650 return le32_to_cpup((__le32 *)(nvm_sw + 651 NVM_VERSION_EXT_NVM)); 652 } 653 654 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 655 const __le16 *phy_sku) 656 { 657 if (cfg->nvm_type != IWL_NVM_EXT) 658 return le16_to_cpup(nvm_sw + RADIO_CFG); 659 660 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 661 662 } 663 664 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 665 { 666 int n_hw_addr; 667 668 if (cfg->nvm_type != IWL_NVM_EXT) 669 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 670 671 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 672 673 return n_hw_addr & N_HW_ADDR_MASK; 674 } 675 676 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 677 struct iwl_nvm_data *data, 678 u32 radio_cfg) 679 { 680 if (cfg->nvm_type != IWL_NVM_EXT) { 681 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 682 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 683 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 684 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 685 return; 686 } 687 688 /* set the radio configuration for family 8000 */ 689 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 690 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 691 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 692 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 693 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 694 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 695 } 696 697 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 698 { 699 const u8 *hw_addr; 700 701 hw_addr = (const u8 *)&mac_addr0; 702 dest[0] = hw_addr[3]; 703 dest[1] = hw_addr[2]; 704 dest[2] = hw_addr[1]; 705 dest[3] = hw_addr[0]; 706 707 hw_addr = (const u8 *)&mac_addr1; 708 dest[4] = hw_addr[1]; 709 dest[5] = hw_addr[0]; 710 } 711 712 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 713 struct iwl_nvm_data *data) 714 { 715 __le32 mac_addr0 = 716 cpu_to_le32(iwl_read32(trans, 717 trans->cfg->csr->mac_addr0_strap)); 718 __le32 mac_addr1 = 719 cpu_to_le32(iwl_read32(trans, 720 trans->cfg->csr->mac_addr1_strap)); 721 722 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 723 /* 724 * If the OEM fused a valid address, use it instead of the one in the 725 * OTP 726 */ 727 if (is_valid_ether_addr(data->hw_addr)) 728 return; 729 730 mac_addr0 = cpu_to_le32(iwl_read32(trans, 731 trans->cfg->csr->mac_addr0_otp)); 732 mac_addr1 = cpu_to_le32(iwl_read32(trans, 733 trans->cfg->csr->mac_addr1_otp)); 734 735 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 736 } 737 738 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 739 const struct iwl_cfg *cfg, 740 struct iwl_nvm_data *data, 741 const __le16 *mac_override, 742 const __be16 *nvm_hw) 743 { 744 const u8 *hw_addr; 745 746 if (mac_override) { 747 static const u8 reserved_mac[] = { 748 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 749 }; 750 751 hw_addr = (const u8 *)(mac_override + 752 MAC_ADDRESS_OVERRIDE_EXT_NVM); 753 754 /* 755 * Store the MAC address from MAO section. 756 * No byte swapping is required in MAO section 757 */ 758 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 759 760 /* 761 * Force the use of the OTP MAC address in case of reserved MAC 762 * address in the NVM, or if address is given but invalid. 763 */ 764 if (is_valid_ether_addr(data->hw_addr) && 765 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 766 return; 767 768 IWL_ERR(trans, 769 "mac address from nvm override section is not valid\n"); 770 } 771 772 if (nvm_hw) { 773 /* read the mac address from WFMP registers */ 774 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 775 WFMP_MAC_ADDR_0)); 776 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 777 WFMP_MAC_ADDR_1)); 778 779 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 780 781 return; 782 } 783 784 IWL_ERR(trans, "mac address is not found\n"); 785 } 786 787 static int iwl_set_hw_address(struct iwl_trans *trans, 788 const struct iwl_cfg *cfg, 789 struct iwl_nvm_data *data, const __be16 *nvm_hw, 790 const __le16 *mac_override) 791 { 792 if (cfg->mac_addr_from_csr) { 793 iwl_set_hw_address_from_csr(trans, data); 794 } else if (cfg->nvm_type != IWL_NVM_EXT) { 795 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 796 797 /* The byte order is little endian 16 bit, meaning 214365 */ 798 data->hw_addr[0] = hw_addr[1]; 799 data->hw_addr[1] = hw_addr[0]; 800 data->hw_addr[2] = hw_addr[3]; 801 data->hw_addr[3] = hw_addr[2]; 802 data->hw_addr[4] = hw_addr[5]; 803 data->hw_addr[5] = hw_addr[4]; 804 } else { 805 iwl_set_hw_address_family_8000(trans, cfg, data, 806 mac_override, nvm_hw); 807 } 808 809 if (!is_valid_ether_addr(data->hw_addr)) { 810 IWL_ERR(trans, "no valid mac address was found\n"); 811 return -EINVAL; 812 } 813 814 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 815 816 return 0; 817 } 818 819 static bool 820 iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg, 821 const __be16 *nvm_hw) 822 { 823 /* 824 * Workaround a bug in Indonesia SKUs where the regulatory in 825 * some 7000-family OTPs erroneously allow wide channels in 826 * 5GHz. To check for Indonesia, we take the SKU value from 827 * bits 1-4 in the subsystem ID and check if it is either 5 or 828 * 9. In those cases, we need to force-disable wide channels 829 * in 5GHz otherwise the FW will throw a sysassert when we try 830 * to use them. 831 */ 832 if (cfg->device_family == IWL_DEVICE_FAMILY_7000) { 833 /* 834 * Unlike the other sections in the NVM, the hw 835 * section uses big-endian. 836 */ 837 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 838 u8 sku = (subsystem_id & 0x1e) >> 1; 839 840 if (sku == 5 || sku == 9) { 841 IWL_DEBUG_EEPROM(dev, 842 "disabling wide channels in 5GHz (0x%0x %d)\n", 843 subsystem_id, sku); 844 return true; 845 } 846 } 847 848 return false; 849 } 850 851 struct iwl_nvm_data * 852 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 853 const __be16 *nvm_hw, const __le16 *nvm_sw, 854 const __le16 *nvm_calib, const __le16 *regulatory, 855 const __le16 *mac_override, const __le16 *phy_sku, 856 u8 tx_chains, u8 rx_chains, bool lar_fw_supported) 857 { 858 struct device *dev = trans->dev; 859 struct iwl_nvm_data *data; 860 bool lar_enabled; 861 u32 sku, radio_cfg; 862 u32 sbands_flags = 0; 863 u16 lar_config; 864 const __le16 *ch_section; 865 866 if (cfg->nvm_type != IWL_NVM_EXT) 867 data = kzalloc(sizeof(*data) + 868 sizeof(struct ieee80211_channel) * 869 IWL_NVM_NUM_CHANNELS, 870 GFP_KERNEL); 871 else 872 data = kzalloc(sizeof(*data) + 873 sizeof(struct ieee80211_channel) * 874 IWL_NVM_NUM_CHANNELS_EXT, 875 GFP_KERNEL); 876 if (!data) 877 return NULL; 878 879 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 880 881 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 882 iwl_set_radio_cfg(cfg, data, radio_cfg); 883 if (data->valid_tx_ant) 884 tx_chains &= data->valid_tx_ant; 885 if (data->valid_rx_ant) 886 rx_chains &= data->valid_rx_ant; 887 888 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 889 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 890 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 891 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 892 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 893 data->sku_cap_11n_enable = false; 894 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 895 (sku & NVM_SKU_CAP_11AC_ENABLE); 896 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 897 898 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 899 900 if (cfg->nvm_type != IWL_NVM_EXT) { 901 /* Checking for required sections */ 902 if (!nvm_calib) { 903 IWL_ERR(trans, 904 "Can't parse empty Calib NVM sections\n"); 905 kfree(data); 906 return NULL; 907 } 908 909 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 910 ®ulatory[NVM_CHANNELS_SDP] : 911 &nvm_sw[NVM_CHANNELS]; 912 913 /* in family 8000 Xtal calibration values moved to OTP */ 914 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 915 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 916 lar_enabled = true; 917 } else { 918 u16 lar_offset = data->nvm_version < 0xE39 ? 919 NVM_LAR_OFFSET_OLD : 920 NVM_LAR_OFFSET; 921 922 lar_config = le16_to_cpup(regulatory + lar_offset); 923 data->lar_enabled = !!(lar_config & 924 NVM_LAR_ENABLED); 925 lar_enabled = data->lar_enabled; 926 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 927 } 928 929 /* If no valid mac address was found - bail out */ 930 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 931 kfree(data); 932 return NULL; 933 } 934 935 if (lar_fw_supported && lar_enabled) 936 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 937 938 if (iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw)) 939 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 940 941 iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains, 942 sbands_flags); 943 data->calib_version = 255; 944 945 return data; 946 } 947 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 948 949 static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan, 950 int ch_idx, u16 nvm_flags, 951 const struct iwl_cfg *cfg) 952 { 953 u32 flags = NL80211_RRF_NO_HT40; 954 u32 last_5ghz_ht = LAST_5GHZ_HT; 955 956 if (cfg->nvm_type == IWL_NVM_EXT) 957 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 958 959 if (ch_idx < NUM_2GHZ_CHANNELS && 960 (nvm_flags & NVM_CHANNEL_40MHZ)) { 961 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 962 flags &= ~NL80211_RRF_NO_HT40PLUS; 963 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 964 flags &= ~NL80211_RRF_NO_HT40MINUS; 965 } else if (nvm_chan[ch_idx] <= last_5ghz_ht && 966 (nvm_flags & NVM_CHANNEL_40MHZ)) { 967 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 968 flags &= ~NL80211_RRF_NO_HT40PLUS; 969 else 970 flags &= ~NL80211_RRF_NO_HT40MINUS; 971 } 972 973 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 974 flags |= NL80211_RRF_NO_80MHZ; 975 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 976 flags |= NL80211_RRF_NO_160MHZ; 977 978 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 979 flags |= NL80211_RRF_NO_IR; 980 981 if (nvm_flags & NVM_CHANNEL_RADAR) 982 flags |= NL80211_RRF_DFS; 983 984 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 985 flags |= NL80211_RRF_NO_OUTDOOR; 986 987 /* Set the GO concurrent flag only in case that NO_IR is set. 988 * Otherwise it is meaningless 989 */ 990 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 991 (flags & NL80211_RRF_NO_IR)) 992 flags |= NL80211_RRF_GO_CONCURRENT; 993 994 return flags; 995 } 996 997 struct regdb_ptrs { 998 struct ieee80211_wmm_rule *rule; 999 u32 token; 1000 }; 1001 1002 struct ieee80211_regdomain * 1003 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1004 int num_of_ch, __le32 *channels, u16 fw_mcc, 1005 u16 geo_info) 1006 { 1007 int ch_idx; 1008 u16 ch_flags; 1009 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1010 const u8 *nvm_chan = cfg->nvm_type == IWL_NVM_EXT ? 1011 iwl_ext_nvm_channels : iwl_nvm_channels; 1012 struct ieee80211_regdomain *regd, *copy_rd; 1013 int size_of_regd, regd_to_copy; 1014 struct ieee80211_reg_rule *rule; 1015 struct regdb_ptrs *regdb_ptrs; 1016 enum nl80211_band band; 1017 int center_freq, prev_center_freq = 0; 1018 int valid_rules = 0; 1019 bool new_rule; 1020 int max_num_ch = cfg->nvm_type == IWL_NVM_EXT ? 1021 IWL_NVM_NUM_CHANNELS_EXT : IWL_NVM_NUM_CHANNELS; 1022 1023 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1024 return ERR_PTR(-EINVAL); 1025 1026 if (WARN_ON(num_of_ch > max_num_ch)) 1027 num_of_ch = max_num_ch; 1028 1029 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1030 num_of_ch); 1031 1032 /* build a regdomain rule for every valid channel */ 1033 size_of_regd = 1034 sizeof(struct ieee80211_regdomain) + 1035 num_of_ch * sizeof(struct ieee80211_reg_rule); 1036 1037 regd = kzalloc(size_of_regd, GFP_KERNEL); 1038 if (!regd) 1039 return ERR_PTR(-ENOMEM); 1040 1041 regdb_ptrs = kcalloc(num_of_ch, sizeof(*regdb_ptrs), GFP_KERNEL); 1042 if (!regdb_ptrs) { 1043 copy_rd = ERR_PTR(-ENOMEM); 1044 goto out; 1045 } 1046 1047 /* set alpha2 from FW. */ 1048 regd->alpha2[0] = fw_mcc >> 8; 1049 regd->alpha2[1] = fw_mcc & 0xff; 1050 1051 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1052 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1053 band = (ch_idx < NUM_2GHZ_CHANNELS) ? 1054 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1055 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1056 band); 1057 new_rule = false; 1058 1059 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1060 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1061 nvm_chan[ch_idx], ch_flags); 1062 continue; 1063 } 1064 1065 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1066 ch_flags, cfg); 1067 1068 /* we can't continue the same rule */ 1069 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1070 center_freq - prev_center_freq > 20) { 1071 valid_rules++; 1072 new_rule = true; 1073 } 1074 1075 rule = ®d->reg_rules[valid_rules - 1]; 1076 1077 if (new_rule) 1078 rule->freq_range.start_freq_khz = 1079 MHZ_TO_KHZ(center_freq - 10); 1080 1081 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1082 1083 /* this doesn't matter - not used by FW */ 1084 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1085 rule->power_rule.max_eirp = 1086 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1087 1088 rule->flags = reg_rule_flags; 1089 1090 /* rely on auto-calculation to merge BW of contiguous chans */ 1091 rule->flags |= NL80211_RRF_AUTO_BW; 1092 rule->freq_range.max_bandwidth_khz = 0; 1093 1094 prev_center_freq = center_freq; 1095 prev_reg_rule_flags = reg_rule_flags; 1096 1097 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1098 nvm_chan[ch_idx], ch_flags); 1099 1100 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1101 band == NL80211_BAND_2GHZ) 1102 continue; 1103 1104 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1105 } 1106 1107 regd->n_reg_rules = valid_rules; 1108 1109 /* 1110 * Narrow down regdom for unused regulatory rules to prevent hole 1111 * between reg rules to wmm rules. 1112 */ 1113 regd_to_copy = sizeof(struct ieee80211_regdomain) + 1114 valid_rules * sizeof(struct ieee80211_reg_rule); 1115 1116 copy_rd = kzalloc(regd_to_copy, GFP_KERNEL); 1117 if (!copy_rd) { 1118 copy_rd = ERR_PTR(-ENOMEM); 1119 goto out; 1120 } 1121 1122 memcpy(copy_rd, regd, regd_to_copy); 1123 1124 out: 1125 kfree(regdb_ptrs); 1126 kfree(regd); 1127 return copy_rd; 1128 } 1129 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1130 1131 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1132 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1133 #define MAX_NVM_FILE_LEN 16384 1134 1135 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1136 unsigned int len) 1137 { 1138 #define IWL_4165_DEVICE_ID 0x5501 1139 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1140 1141 if (section == NVM_SECTION_TYPE_PHY_SKU && 1142 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1143 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1144 /* OTP 0x52 bug work around: it's a 1x1 device */ 1145 data[3] = ANT_B | (ANT_B << 4); 1146 } 1147 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1148 1149 /* 1150 * Reads external NVM from a file into mvm->nvm_sections 1151 * 1152 * HOW TO CREATE THE NVM FILE FORMAT: 1153 * ------------------------------ 1154 * 1. create hex file, format: 1155 * 3800 -> header 1156 * 0000 -> header 1157 * 5a40 -> data 1158 * 1159 * rev - 6 bit (word1) 1160 * len - 10 bit (word1) 1161 * id - 4 bit (word2) 1162 * rsv - 12 bit (word2) 1163 * 1164 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1165 * 1166 * 3. create binary file from the hex file 1167 * 1168 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1169 */ 1170 int iwl_read_external_nvm(struct iwl_trans *trans, 1171 const char *nvm_file_name, 1172 struct iwl_nvm_section *nvm_sections) 1173 { 1174 int ret, section_size; 1175 u16 section_id; 1176 const struct firmware *fw_entry; 1177 const struct { 1178 __le16 word1; 1179 __le16 word2; 1180 u8 data[]; 1181 } *file_sec; 1182 const u8 *eof; 1183 u8 *temp; 1184 int max_section_size; 1185 const __le32 *dword_buff; 1186 1187 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1188 #define NVM_WORD2_ID(x) (x >> 12) 1189 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1190 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1191 #define NVM_HEADER_0 (0x2A504C54) 1192 #define NVM_HEADER_1 (0x4E564D2A) 1193 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1194 1195 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1196 1197 /* Maximal size depends on NVM version */ 1198 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1199 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1200 else 1201 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1202 1203 /* 1204 * Obtain NVM image via request_firmware. Since we already used 1205 * request_firmware_nowait() for the firmware binary load and only 1206 * get here after that we assume the NVM request can be satisfied 1207 * synchronously. 1208 */ 1209 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1210 if (ret) { 1211 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1212 nvm_file_name, ret); 1213 return ret; 1214 } 1215 1216 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1217 nvm_file_name, fw_entry->size); 1218 1219 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1220 IWL_ERR(trans, "NVM file too large\n"); 1221 ret = -EINVAL; 1222 goto out; 1223 } 1224 1225 eof = fw_entry->data + fw_entry->size; 1226 dword_buff = (__le32 *)fw_entry->data; 1227 1228 /* some NVM file will contain a header. 1229 * The header is identified by 2 dwords header as follow: 1230 * dword[0] = 0x2A504C54 1231 * dword[1] = 0x4E564D2A 1232 * 1233 * This header must be skipped when providing the NVM data to the FW. 1234 */ 1235 if (fw_entry->size > NVM_HEADER_SIZE && 1236 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1237 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1238 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1239 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1240 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1241 le32_to_cpu(dword_buff[3])); 1242 1243 /* nvm file validation, dword_buff[2] holds the file version */ 1244 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1245 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP && 1246 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1247 ret = -EFAULT; 1248 goto out; 1249 } 1250 } else { 1251 file_sec = (void *)fw_entry->data; 1252 } 1253 1254 while (true) { 1255 if (file_sec->data > eof) { 1256 IWL_ERR(trans, 1257 "ERROR - NVM file too short for section header\n"); 1258 ret = -EINVAL; 1259 break; 1260 } 1261 1262 /* check for EOF marker */ 1263 if (!file_sec->word1 && !file_sec->word2) { 1264 ret = 0; 1265 break; 1266 } 1267 1268 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1269 section_size = 1270 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1271 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1272 } else { 1273 section_size = 2 * EXT_NVM_WORD2_LEN( 1274 le16_to_cpu(file_sec->word2)); 1275 section_id = EXT_NVM_WORD1_ID( 1276 le16_to_cpu(file_sec->word1)); 1277 } 1278 1279 if (section_size > max_section_size) { 1280 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1281 section_size); 1282 ret = -EINVAL; 1283 break; 1284 } 1285 1286 if (!section_size) { 1287 IWL_ERR(trans, "ERROR - section empty\n"); 1288 ret = -EINVAL; 1289 break; 1290 } 1291 1292 if (file_sec->data + section_size > eof) { 1293 IWL_ERR(trans, 1294 "ERROR - NVM file too short for section (%d bytes)\n", 1295 section_size); 1296 ret = -EINVAL; 1297 break; 1298 } 1299 1300 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1301 "Invalid NVM section ID %d\n", section_id)) { 1302 ret = -EINVAL; 1303 break; 1304 } 1305 1306 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1307 if (!temp) { 1308 ret = -ENOMEM; 1309 break; 1310 } 1311 1312 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1313 1314 kfree(nvm_sections[section_id].data); 1315 nvm_sections[section_id].data = temp; 1316 nvm_sections[section_id].length = section_size; 1317 1318 /* advance to the next section */ 1319 file_sec = (void *)(file_sec->data + section_size); 1320 } 1321 out: 1322 release_firmware(fw_entry); 1323 return ret; 1324 } 1325 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1326 1327 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1328 const struct iwl_fw *fw) 1329 { 1330 struct iwl_nvm_get_info cmd = {}; 1331 struct iwl_nvm_get_info_rsp *rsp; 1332 struct iwl_nvm_data *nvm; 1333 struct iwl_host_cmd hcmd = { 1334 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1335 .data = { &cmd, }, 1336 .len = { sizeof(cmd) }, 1337 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1338 }; 1339 int ret; 1340 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable && 1341 fw_has_capa(&fw->ucode_capa, 1342 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 1343 u32 mac_flags; 1344 u32 sbands_flags = 0; 1345 1346 ret = iwl_trans_send_cmd(trans, &hcmd); 1347 if (ret) 1348 return ERR_PTR(ret); 1349 1350 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp), 1351 "Invalid payload len in NVM response from FW %d", 1352 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1353 ret = -EINVAL; 1354 goto out; 1355 } 1356 1357 rsp = (void *)hcmd.resp_pkt->data; 1358 if (le32_to_cpu(rsp->general.flags) & NVM_GENERAL_FLAGS_EMPTY_OTP) 1359 IWL_INFO(trans, "OTP is empty\n"); 1360 1361 nvm = kzalloc(sizeof(*nvm) + 1362 sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS, 1363 GFP_KERNEL); 1364 if (!nvm) { 1365 ret = -ENOMEM; 1366 goto out; 1367 } 1368 1369 iwl_set_hw_address_from_csr(trans, nvm); 1370 /* TODO: if platform NVM has MAC address - override it here */ 1371 1372 if (!is_valid_ether_addr(nvm->hw_addr)) { 1373 IWL_ERR(trans, "no valid mac address was found\n"); 1374 ret = -EINVAL; 1375 goto err_free; 1376 } 1377 1378 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1379 1380 /* Initialize general data */ 1381 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1382 1383 /* Initialize MAC sku data */ 1384 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1385 nvm->sku_cap_11ac_enable = 1386 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1387 nvm->sku_cap_11n_enable = 1388 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1389 nvm->sku_cap_11ax_enable = 1390 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1391 nvm->sku_cap_band_24ghz_enable = 1392 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1393 nvm->sku_cap_band_52ghz_enable = 1394 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1395 nvm->sku_cap_mimo_disabled = 1396 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1397 1398 /* Initialize PHY sku data */ 1399 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1400 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1401 1402 if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) { 1403 nvm->lar_enabled = true; 1404 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1405 } 1406 1407 iwl_init_sbands(trans->dev, trans->cfg, nvm, 1408 rsp->regulatory.channel_profile, 1409 nvm->valid_tx_ant & fw->valid_tx_ant, 1410 nvm->valid_rx_ant & fw->valid_rx_ant, 1411 sbands_flags); 1412 1413 iwl_free_resp(&hcmd); 1414 return nvm; 1415 1416 err_free: 1417 kfree(nvm); 1418 out: 1419 iwl_free_resp(&hcmd); 1420 return ERR_PTR(ret); 1421 } 1422 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1423