1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2022 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/types.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/etherdevice.h> 11 #include <linux/pci.h> 12 #include <linux/firmware.h> 13 14 #include "iwl-drv.h" 15 #include "iwl-modparams.h" 16 #include "iwl-nvm-parse.h" 17 #include "iwl-prph.h" 18 #include "iwl-io.h" 19 #include "iwl-csr.h" 20 #include "fw/acpi.h" 21 #include "fw/api/nvm-reg.h" 22 #include "fw/api/commands.h" 23 #include "fw/api/cmdhdr.h" 24 #include "fw/img.h" 25 #include "mei/iwl-mei.h" 26 27 /* NVM offsets (in words) definitions */ 28 enum nvm_offsets { 29 /* NVM HW-Section offset (in words) definitions */ 30 SUBSYSTEM_ID = 0x0A, 31 HW_ADDR = 0x15, 32 33 /* NVM SW-Section offset (in words) definitions */ 34 NVM_SW_SECTION = 0x1C0, 35 NVM_VERSION = 0, 36 RADIO_CFG = 1, 37 SKU = 2, 38 N_HW_ADDRS = 3, 39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 40 41 /* NVM calibration section offset (in words) definitions */ 42 NVM_CALIB_SECTION = 0x2B8, 43 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 44 45 /* NVM REGULATORY -Section offset (in words) definitions */ 46 NVM_CHANNELS_SDP = 0, 47 }; 48 49 enum ext_nvm_offsets { 50 /* NVM HW-Section offset (in words) definitions */ 51 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 52 53 /* NVM SW-Section offset (in words) definitions */ 54 NVM_VERSION_EXT_NVM = 0, 55 N_HW_ADDRS_FAMILY_8000 = 3, 56 57 /* NVM PHY_SKU-Section offset (in words) definitions */ 58 RADIO_CFG_FAMILY_EXT_NVM = 0, 59 SKU_FAMILY_8000 = 2, 60 61 /* NVM REGULATORY -Section offset (in words) definitions */ 62 NVM_CHANNELS_EXTENDED = 0, 63 NVM_LAR_OFFSET_OLD = 0x4C7, 64 NVM_LAR_OFFSET = 0x507, 65 NVM_LAR_ENABLED = 0x7, 66 }; 67 68 /* SKU Capabilities (actual values from NVM definition) */ 69 enum nvm_sku_bits { 70 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 71 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 72 NVM_SKU_CAP_11N_ENABLE = BIT(2), 73 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 74 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 75 }; 76 77 /* 78 * These are the channel numbers in the order that they are stored in the NVM 79 */ 80 static const u16 iwl_nvm_channels[] = { 81 /* 2.4 GHz */ 82 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 83 /* 5 GHz */ 84 36, 40, 44, 48, 52, 56, 60, 64, 85 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 86 149, 153, 157, 161, 165 87 }; 88 89 static const u16 iwl_ext_nvm_channels[] = { 90 /* 2.4 GHz */ 91 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 92 /* 5 GHz */ 93 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 94 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 95 149, 153, 157, 161, 165, 169, 173, 177, 181 96 }; 97 98 static const u16 iwl_uhb_nvm_channels[] = { 99 /* 2.4 GHz */ 100 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 101 /* 5 GHz */ 102 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 103 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 104 149, 153, 157, 161, 165, 169, 173, 177, 181, 105 /* 6-7 GHz */ 106 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 107 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 108 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 109 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 110 }; 111 112 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 113 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 114 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 115 #define NUM_2GHZ_CHANNELS 14 116 #define NUM_5GHZ_CHANNELS 37 117 #define FIRST_2GHZ_HT_MINUS 5 118 #define LAST_2GHZ_HT_PLUS 9 119 #define N_HW_ADDR_MASK 0xF 120 121 /* rate data (static) */ 122 static struct ieee80211_rate iwl_cfg80211_rates[] = { 123 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 124 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 125 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 126 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 127 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 128 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 130 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 131 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 132 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 133 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 134 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 135 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 136 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 137 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 138 }; 139 #define RATES_24_OFFS 0 140 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 141 #define RATES_52_OFFS 4 142 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 143 144 /** 145 * enum iwl_nvm_channel_flags - channel flags in NVM 146 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 147 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 148 * @NVM_CHANNEL_ACTIVE: active scanning allowed 149 * @NVM_CHANNEL_RADAR: radar detection required 150 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 151 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 152 * on same channel on 2.4 or same UNII band on 5.2 153 * @NVM_CHANNEL_UNIFORM: uniform spreading required 154 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 155 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 156 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 157 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 158 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 159 */ 160 enum iwl_nvm_channel_flags { 161 NVM_CHANNEL_VALID = BIT(0), 162 NVM_CHANNEL_IBSS = BIT(1), 163 NVM_CHANNEL_ACTIVE = BIT(3), 164 NVM_CHANNEL_RADAR = BIT(4), 165 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 166 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 167 NVM_CHANNEL_UNIFORM = BIT(7), 168 NVM_CHANNEL_20MHZ = BIT(8), 169 NVM_CHANNEL_40MHZ = BIT(9), 170 NVM_CHANNEL_80MHZ = BIT(10), 171 NVM_CHANNEL_160MHZ = BIT(11), 172 NVM_CHANNEL_DC_HIGH = BIT(12), 173 }; 174 175 /** 176 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory 177 * domain. 178 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 179 * 2.4Ghz band is allowed. 180 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 181 * 5Ghz band is allowed. 182 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 183 * for this regulatory domain (valid only in 5Ghz). 184 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 185 * for this regulatory domain (valid only in 5Ghz). 186 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 187 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 188 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden 189 * for this regulatory domain (valid only in 5Ghz). 190 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed. 191 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 192 */ 193 enum iwl_reg_capa_flags { 194 REG_CAPA_BF_CCD_LOW_BAND = BIT(0), 195 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1), 196 REG_CAPA_160MHZ_ALLOWED = BIT(2), 197 REG_CAPA_80MHZ_ALLOWED = BIT(3), 198 REG_CAPA_MCS_8_ALLOWED = BIT(4), 199 REG_CAPA_MCS_9_ALLOWED = BIT(5), 200 REG_CAPA_40MHZ_FORBIDDEN = BIT(7), 201 REG_CAPA_DC_HIGH_ENABLED = BIT(9), 202 REG_CAPA_11AX_DISABLED = BIT(10), 203 }; 204 205 /** 206 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory 207 * domain (version 2). 208 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are 209 * disabled. 210 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 211 * 2.4Ghz band is allowed. 212 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 213 * 5Ghz band is allowed. 214 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 215 * for this regulatory domain (valid only in 5Ghz). 216 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 217 * for this regulatory domain (valid only in 5Ghz). 218 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 219 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 220 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118, 221 * 126, 122) are disabled. 222 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed 223 * for this regulatory domain (uvalid only in 5Ghz). 224 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 225 */ 226 enum iwl_reg_capa_flags_v2 { 227 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0), 228 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1), 229 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2), 230 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3), 231 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4), 232 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5), 233 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6), 234 REG_CAPA_V2_WEATHER_DISABLED = BIT(7), 235 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8), 236 REG_CAPA_V2_11AX_DISABLED = BIT(10), 237 }; 238 239 /* 240 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the 241 * MCC update command response. 242 */ 243 #define REG_CAPA_V2_RESP_VER 6 244 245 /** 246 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for 247 * handling the different APIs of reg_capa_flags. 248 * 249 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed 250 * for this regulatory domain (valid only in 5Ghz). 251 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed 252 * for this regulatory domain (valid only in 5Ghz). 253 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed 254 * for this regulatory domain (valid only in 5Ghz). 255 * @disable_11ax: 11ax is forbidden for this regulatory domain. 256 */ 257 struct iwl_reg_capa { 258 u16 allow_40mhz; 259 u16 allow_80mhz; 260 u16 allow_160mhz; 261 u16 disable_11ax; 262 }; 263 264 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 265 int chan, u32 flags) 266 { 267 #define CHECK_AND_PRINT_I(x) \ 268 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 269 270 if (!(flags & NVM_CHANNEL_VALID)) { 271 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 272 chan, flags); 273 return; 274 } 275 276 /* Note: already can print up to 101 characters, 110 is the limit! */ 277 IWL_DEBUG_DEV(dev, level, 278 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 279 chan, flags, 280 CHECK_AND_PRINT_I(VALID), 281 CHECK_AND_PRINT_I(IBSS), 282 CHECK_AND_PRINT_I(ACTIVE), 283 CHECK_AND_PRINT_I(RADAR), 284 CHECK_AND_PRINT_I(INDOOR_ONLY), 285 CHECK_AND_PRINT_I(GO_CONCURRENT), 286 CHECK_AND_PRINT_I(UNIFORM), 287 CHECK_AND_PRINT_I(20MHZ), 288 CHECK_AND_PRINT_I(40MHZ), 289 CHECK_AND_PRINT_I(80MHZ), 290 CHECK_AND_PRINT_I(160MHZ), 291 CHECK_AND_PRINT_I(DC_HIGH)); 292 #undef CHECK_AND_PRINT_I 293 } 294 295 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 296 u32 nvm_flags, const struct iwl_cfg *cfg) 297 { 298 u32 flags = IEEE80211_CHAN_NO_HT40; 299 300 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 301 if (ch_num <= LAST_2GHZ_HT_PLUS) 302 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 303 if (ch_num >= FIRST_2GHZ_HT_MINUS) 304 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 305 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 306 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 307 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 308 else 309 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 310 } 311 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 312 flags |= IEEE80211_CHAN_NO_80MHZ; 313 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 314 flags |= IEEE80211_CHAN_NO_160MHZ; 315 316 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 317 flags |= IEEE80211_CHAN_NO_IR; 318 319 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 320 flags |= IEEE80211_CHAN_NO_IR; 321 322 if (nvm_flags & NVM_CHANNEL_RADAR) 323 flags |= IEEE80211_CHAN_RADAR; 324 325 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 326 flags |= IEEE80211_CHAN_INDOOR_ONLY; 327 328 /* Set the GO concurrent flag only in case that NO_IR is set. 329 * Otherwise it is meaningless 330 */ 331 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 332 (flags & IEEE80211_CHAN_NO_IR)) 333 flags |= IEEE80211_CHAN_IR_CONCURRENT; 334 335 return flags; 336 } 337 338 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 339 { 340 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) { 341 return NL80211_BAND_6GHZ; 342 } 343 344 if (ch_idx >= NUM_2GHZ_CHANNELS) 345 return NL80211_BAND_5GHZ; 346 return NL80211_BAND_2GHZ; 347 } 348 349 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 350 struct iwl_nvm_data *data, 351 const void * const nvm_ch_flags, 352 u32 sbands_flags, bool v4) 353 { 354 int ch_idx; 355 int n_channels = 0; 356 struct ieee80211_channel *channel; 357 u32 ch_flags; 358 int num_of_ch; 359 const u16 *nvm_chan; 360 361 if (cfg->uhb_supported) { 362 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 363 nvm_chan = iwl_uhb_nvm_channels; 364 } else if (cfg->nvm_type == IWL_NVM_EXT) { 365 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 366 nvm_chan = iwl_ext_nvm_channels; 367 } else { 368 num_of_ch = IWL_NVM_NUM_CHANNELS; 369 nvm_chan = iwl_nvm_channels; 370 } 371 372 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 373 enum nl80211_band band = 374 iwl_nl80211_band_from_channel_idx(ch_idx); 375 376 if (v4) 377 ch_flags = 378 __le32_to_cpup((const __le32 *)nvm_ch_flags + ch_idx); 379 else 380 ch_flags = 381 __le16_to_cpup((const __le16 *)nvm_ch_flags + ch_idx); 382 383 if (band == NL80211_BAND_5GHZ && 384 !data->sku_cap_band_52ghz_enable) 385 continue; 386 387 /* workaround to disable wide channels in 5GHz */ 388 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 389 band == NL80211_BAND_5GHZ) { 390 ch_flags &= ~(NVM_CHANNEL_40MHZ | 391 NVM_CHANNEL_80MHZ | 392 NVM_CHANNEL_160MHZ); 393 } 394 395 if (ch_flags & NVM_CHANNEL_160MHZ) 396 data->vht160_supported = true; 397 398 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 399 !(ch_flags & NVM_CHANNEL_VALID)) { 400 /* 401 * Channels might become valid later if lar is 402 * supported, hence we still want to add them to 403 * the list of supported channels to cfg80211. 404 */ 405 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 406 nvm_chan[ch_idx], ch_flags); 407 continue; 408 } 409 410 channel = &data->channels[n_channels]; 411 n_channels++; 412 413 channel->hw_value = nvm_chan[ch_idx]; 414 channel->band = band; 415 channel->center_freq = 416 ieee80211_channel_to_frequency( 417 channel->hw_value, channel->band); 418 419 /* Initialize regulatory-based run-time data */ 420 421 /* 422 * Default value - highest tx power value. max_power 423 * is not used in mvm, and is used for backwards compatibility 424 */ 425 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 426 427 /* don't put limitations in case we're using LAR */ 428 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 429 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 430 ch_idx, band, 431 ch_flags, cfg); 432 else 433 channel->flags = 0; 434 435 /* TODO: Don't put limitations on UHB devices as we still don't 436 * have NVM for them 437 */ 438 if (cfg->uhb_supported) 439 channel->flags = 0; 440 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 441 channel->hw_value, ch_flags); 442 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 443 channel->hw_value, channel->max_power); 444 } 445 446 return n_channels; 447 } 448 449 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 450 struct iwl_nvm_data *data, 451 struct ieee80211_sta_vht_cap *vht_cap, 452 u8 tx_chains, u8 rx_chains) 453 { 454 const struct iwl_cfg *cfg = trans->cfg; 455 int num_rx_ants = num_of_ant(rx_chains); 456 int num_tx_ants = num_of_ant(tx_chains); 457 458 vht_cap->vht_supported = true; 459 460 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 461 IEEE80211_VHT_CAP_RXSTBC_1 | 462 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 463 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 464 IEEE80211_VHT_MAX_AMPDU_1024K << 465 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 466 467 if (!trans->cfg->ht_params->stbc) 468 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK; 469 470 if (data->vht160_supported) 471 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 472 IEEE80211_VHT_CAP_SHORT_GI_160; 473 474 if (cfg->vht_mu_mimo_supported) 475 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 476 477 if (cfg->ht_params->ldpc) 478 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 479 480 if (data->sku_cap_mimo_disabled) { 481 num_rx_ants = 1; 482 num_tx_ants = 1; 483 } 484 485 if (num_tx_ants > 1) 486 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 487 else 488 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 489 490 switch (iwlwifi_mod_params.amsdu_size) { 491 case IWL_AMSDU_DEF: 492 if (trans->trans_cfg->mq_rx_supported) 493 vht_cap->cap |= 494 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 495 else 496 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 497 break; 498 case IWL_AMSDU_2K: 499 if (trans->trans_cfg->mq_rx_supported) 500 vht_cap->cap |= 501 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 502 else 503 WARN(1, "RB size of 2K is not supported by this device\n"); 504 break; 505 case IWL_AMSDU_4K: 506 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 507 break; 508 case IWL_AMSDU_8K: 509 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 510 break; 511 case IWL_AMSDU_12K: 512 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 513 break; 514 default: 515 break; 516 } 517 518 vht_cap->vht_mcs.rx_mcs_map = 519 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 520 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 523 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 524 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 525 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 526 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 527 528 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 529 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 530 /* this works because NOT_SUPPORTED == 3 */ 531 vht_cap->vht_mcs.rx_mcs_map |= 532 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 533 } 534 535 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 536 537 vht_cap->vht_mcs.tx_highest |= 538 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 539 } 540 541 static const u8 iwl_vendor_caps[] = { 542 0xdd, /* vendor element */ 543 0x06, /* length */ 544 0x00, 0x17, 0x35, /* Intel OUI */ 545 0x08, /* type (Intel Capabilities) */ 546 /* followed by 16 bits of capabilities */ 547 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0) 548 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE, 549 0x00 550 }; 551 552 static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = { 553 { 554 .types_mask = BIT(NL80211_IFTYPE_STATION), 555 .he_cap = { 556 .has_he = true, 557 .he_cap_elem = { 558 .mac_cap_info[0] = 559 IEEE80211_HE_MAC_CAP0_HTC_HE, 560 .mac_cap_info[1] = 561 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 562 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 563 .mac_cap_info[2] = 564 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP, 565 .mac_cap_info[3] = 566 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 567 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS, 568 .mac_cap_info[4] = 569 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU | 570 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 571 .mac_cap_info[5] = 572 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 573 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 574 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 575 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 576 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 577 .phy_cap_info[1] = 578 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 579 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 580 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 581 .phy_cap_info[2] = 582 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 583 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 584 .phy_cap_info[3] = 585 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 586 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 587 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 588 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 589 .phy_cap_info[4] = 590 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 591 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 592 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 593 .phy_cap_info[6] = 594 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 595 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB | 596 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 597 .phy_cap_info[7] = 598 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 599 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 600 .phy_cap_info[8] = 601 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 602 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 603 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 604 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 605 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 606 .phy_cap_info[9] = 607 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 608 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 609 (IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED << 610 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS), 611 .phy_cap_info[10] = 612 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF, 613 }, 614 /* 615 * Set default Tx/Rx HE MCS NSS Support field. 616 * Indicate support for up to 2 spatial streams and all 617 * MCS, without any special cases 618 */ 619 .he_mcs_nss_supp = { 620 .rx_mcs_80 = cpu_to_le16(0xfffa), 621 .tx_mcs_80 = cpu_to_le16(0xfffa), 622 .rx_mcs_160 = cpu_to_le16(0xfffa), 623 .tx_mcs_160 = cpu_to_le16(0xfffa), 624 .rx_mcs_80p80 = cpu_to_le16(0xffff), 625 .tx_mcs_80p80 = cpu_to_le16(0xffff), 626 }, 627 /* 628 * Set default PPE thresholds, with PPET16 set to 0, 629 * PPET8 set to 7 630 */ 631 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 632 }, 633 .eht_cap = { 634 .has_eht = true, 635 .eht_cap_elem = { 636 .mac_cap_info[0] = 637 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 638 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 639 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 640 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2, 641 .phy_cap_info[0] = 642 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ | 643 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 644 IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO | 645 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE | 646 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK, 647 .phy_cap_info[1] = 648 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK | 649 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK | 650 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK, 651 .phy_cap_info[3] = 652 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 653 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 654 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 655 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 656 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 657 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | 658 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK, 659 660 .phy_cap_info[4] = 661 IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO | 662 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 663 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI, 664 .phy_cap_info[5] = 665 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | 666 IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP | 667 IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP | 668 IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT, 669 .phy_cap_info[6] = 670 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK | 671 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP, 672 .phy_cap_info[8] = 673 IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA | 674 IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA, 675 }, 676 677 /* For all MCS and bandwidth, set 2 NSS for both Tx and 678 * Rx - note we don't set the only_20mhz, but due to this 679 * being a union, it gets set correctly anyway. 680 */ 681 .eht_mcs_nss_supp = { 682 .bw._80 = { 683 .rx_tx_mcs9_max_nss = 0x22, 684 .rx_tx_mcs11_max_nss = 0x22, 685 .rx_tx_mcs13_max_nss = 0x22, 686 }, 687 .bw._160 = { 688 .rx_tx_mcs9_max_nss = 0x22, 689 .rx_tx_mcs11_max_nss = 0x22, 690 .rx_tx_mcs13_max_nss = 0x22, 691 }, 692 .bw._320 = { 693 .rx_tx_mcs9_max_nss = 0x22, 694 .rx_tx_mcs11_max_nss = 0x22, 695 .rx_tx_mcs13_max_nss = 0x22, 696 }, 697 }, 698 699 /* 700 * PPE thresholds for NSS = 2, and RU index bitmap set 701 * to 0xc. 702 */ 703 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 } 704 }, 705 }, 706 { 707 .types_mask = BIT(NL80211_IFTYPE_AP), 708 .he_cap = { 709 .has_he = true, 710 .he_cap_elem = { 711 .mac_cap_info[0] = 712 IEEE80211_HE_MAC_CAP0_HTC_HE, 713 .mac_cap_info[1] = 714 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 715 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 716 .mac_cap_info[3] = 717 IEEE80211_HE_MAC_CAP3_OMI_CONTROL, 718 .phy_cap_info[1] = 719 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 720 .phy_cap_info[2] = 721 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 722 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 723 .phy_cap_info[3] = 724 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 725 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 726 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 727 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 728 .phy_cap_info[6] = 729 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 730 .phy_cap_info[7] = 731 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 732 .phy_cap_info[8] = 733 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 734 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 735 .phy_cap_info[9] = 736 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED 737 << IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS, 738 }, 739 /* 740 * Set default Tx/Rx HE MCS NSS Support field. 741 * Indicate support for up to 2 spatial streams and all 742 * MCS, without any special cases 743 */ 744 .he_mcs_nss_supp = { 745 .rx_mcs_80 = cpu_to_le16(0xfffa), 746 .tx_mcs_80 = cpu_to_le16(0xfffa), 747 .rx_mcs_160 = cpu_to_le16(0xfffa), 748 .tx_mcs_160 = cpu_to_le16(0xfffa), 749 .rx_mcs_80p80 = cpu_to_le16(0xffff), 750 .tx_mcs_80p80 = cpu_to_le16(0xffff), 751 }, 752 /* 753 * Set default PPE thresholds, with PPET16 set to 0, 754 * PPET8 set to 7 755 */ 756 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 757 }, 758 .eht_cap = { 759 .has_eht = true, 760 .eht_cap_elem = { 761 .mac_cap_info[0] = 762 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 763 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 764 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 765 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2, 766 .phy_cap_info[0] = 767 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ | 768 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI, 769 .phy_cap_info[5] = 770 IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT, 771 }, 772 773 /* For all MCS and bandwidth, set 2 NSS for both Tx and 774 * Rx - note we don't set the only_20mhz, but due to this 775 * being a union, it gets set correctly anyway. 776 */ 777 .eht_mcs_nss_supp = { 778 .bw._80 = { 779 .rx_tx_mcs9_max_nss = 0x22, 780 .rx_tx_mcs11_max_nss = 0x22, 781 .rx_tx_mcs13_max_nss = 0x22, 782 }, 783 .bw._160 = { 784 .rx_tx_mcs9_max_nss = 0x22, 785 .rx_tx_mcs11_max_nss = 0x22, 786 .rx_tx_mcs13_max_nss = 0x22, 787 }, 788 .bw._320 = { 789 .rx_tx_mcs9_max_nss = 0x22, 790 .rx_tx_mcs11_max_nss = 0x22, 791 .rx_tx_mcs13_max_nss = 0x22, 792 }, 793 }, 794 795 /* 796 * PPE thresholds for NSS = 2, and RU index bitmap set 797 * to 0xc. 798 */ 799 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 } 800 }, 801 }, 802 }; 803 804 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans, 805 struct iwl_nvm_data *data, 806 struct ieee80211_supported_band *sband, 807 u8 tx_chains, u8 rx_chains) 808 { 809 struct ieee80211_sta_ht_cap ht_cap; 810 struct ieee80211_sta_vht_cap vht_cap = {}; 811 struct ieee80211_sband_iftype_data *iftype_data; 812 u16 he_6ghz_capa = 0; 813 u32 exp; 814 int i; 815 816 if (sband->band != NL80211_BAND_6GHZ) 817 return; 818 819 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */ 820 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ, 821 tx_chains, rx_chains); 822 WARN_ON(!ht_cap.ht_supported); 823 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains); 824 WARN_ON(!vht_cap.vht_supported); 825 826 he_6ghz_capa |= 827 u16_encode_bits(ht_cap.ampdu_density, 828 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START); 829 exp = u32_get_bits(vht_cap.cap, 830 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK); 831 he_6ghz_capa |= 832 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP); 833 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK); 834 he_6ghz_capa |= 835 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 836 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */ 837 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN) 838 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS; 839 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN) 840 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 841 842 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa); 843 844 /* we know it's writable - we set it before ourselves */ 845 iftype_data = (void *)(uintptr_t)sband->iftype_data; 846 for (i = 0; i < sband->n_iftype_data; i++) 847 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa); 848 } 849 850 static void 851 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, 852 struct iwl_nvm_data *data, 853 struct ieee80211_supported_band *sband, 854 struct ieee80211_sband_iftype_data *iftype_data, 855 u8 tx_chains, u8 rx_chains, 856 const struct iwl_fw *fw) 857 { 858 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP); 859 860 if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be) 861 iftype_data->eht_cap.has_eht = false; 862 863 /* Advertise an A-MPDU exponent extension based on 864 * operating band 865 */ 866 if (sband->band == NL80211_BAND_6GHZ && iftype_data->eht_cap.has_eht) 867 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 868 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 869 else if (sband->band != NL80211_BAND_2GHZ) 870 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 871 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1; 872 else 873 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 874 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 875 876 switch (sband->band) { 877 case NL80211_BAND_2GHZ: 878 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 879 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 880 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] |= 881 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 882 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 883 break; 884 case NL80211_BAND_6GHZ: 885 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |= 886 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 887 fallthrough; 888 case NL80211_BAND_5GHZ: 889 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 890 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 891 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 892 break; 893 default: 894 WARN_ON(1); 895 break; 896 } 897 898 if ((tx_chains & rx_chains) == ANT_AB) { 899 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 900 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ; 901 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |= 902 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 903 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2; 904 if (!is_ap) { 905 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 906 IEEE80211_HE_PHY_CAP7_MAX_NC_2; 907 908 if (iftype_data->eht_cap.has_eht) { 909 /* 910 * Set the number of sounding dimensions for each 911 * bandwidth to 1 to indicate the maximal supported 912 * value of TXVECTOR parameter NUM_STS of 2 913 */ 914 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] |= 0x49; 915 916 /* 917 * Set the MAX NC to 1 to indicate sounding feedback of 918 * 2 supported by the beamfomee. 919 */ 920 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] |= 0x10; 921 } 922 } 923 } else { 924 if (iftype_data->eht_cap.has_eht) { 925 struct ieee80211_eht_mcs_nss_supp *mcs_nss = 926 &iftype_data->eht_cap.eht_mcs_nss_supp; 927 928 memset(mcs_nss, 0x11, sizeof(*mcs_nss)); 929 } 930 931 if (!is_ap) { 932 /* If not 2x2, we need to indicate 1x1 in the 933 * Midamble RX Max NSTS - but not for AP mode 934 */ 935 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &= 936 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 937 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 938 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 939 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 940 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 941 } 942 } 943 944 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210 && !is_ap) 945 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 946 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 947 948 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 949 case IWL_CFG_RF_TYPE_GF: 950 case IWL_CFG_RF_TYPE_MR: 951 case IWL_CFG_RF_TYPE_MS: 952 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 953 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 954 if (!is_ap) 955 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 956 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 957 break; 958 } 959 960 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL && 961 iftype_data->eht_cap.has_eht) { 962 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] &= 963 ~(IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 964 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 965 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2); 966 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[3] &= 967 ~(IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO | 968 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 969 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 970 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 971 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 972 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK); 973 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] &= 974 ~(IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO | 975 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP); 976 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] &= 977 ~IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK; 978 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &= 979 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK | 980 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP); 981 } 982 983 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT)) 984 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |= 985 IEEE80211_HE_MAC_CAP2_BCAST_TWT; 986 987 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 988 !is_ap) { 989 iftype_data->vendor_elems.data = iwl_vendor_caps; 990 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps); 991 } 992 993 if (!trans->cfg->ht_params->stbc) { 994 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 995 ~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 996 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &= 997 ~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 998 } 999 } 1000 1001 static void iwl_init_he_hw_capab(struct iwl_trans *trans, 1002 struct iwl_nvm_data *data, 1003 struct ieee80211_supported_band *sband, 1004 u8 tx_chains, u8 rx_chains, 1005 const struct iwl_fw *fw) 1006 { 1007 struct ieee80211_sband_iftype_data *iftype_data; 1008 int i; 1009 1010 /* should only initialize once */ 1011 if (WARN_ON(sband->iftype_data)) 1012 return; 1013 1014 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_eht_capa)); 1015 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_eht_capa)); 1016 BUILD_BUG_ON(sizeof(data->iftd.uhb) != sizeof(iwl_he_eht_capa)); 1017 1018 switch (sband->band) { 1019 case NL80211_BAND_2GHZ: 1020 iftype_data = data->iftd.low; 1021 break; 1022 case NL80211_BAND_5GHZ: 1023 iftype_data = data->iftd.high; 1024 break; 1025 case NL80211_BAND_6GHZ: 1026 iftype_data = data->iftd.uhb; 1027 break; 1028 default: 1029 WARN_ON(1); 1030 return; 1031 } 1032 1033 memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa)); 1034 1035 sband->iftype_data = iftype_data; 1036 sband->n_iftype_data = ARRAY_SIZE(iwl_he_eht_capa); 1037 1038 for (i = 0; i < sband->n_iftype_data; i++) 1039 iwl_nvm_fixup_sband_iftd(trans, data, sband, &iftype_data[i], 1040 tx_chains, rx_chains, fw); 1041 1042 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains); 1043 } 1044 1045 static void iwl_init_sbands(struct iwl_trans *trans, 1046 struct iwl_nvm_data *data, 1047 const void *nvm_ch_flags, u8 tx_chains, 1048 u8 rx_chains, u32 sbands_flags, bool v4, 1049 const struct iwl_fw *fw) 1050 { 1051 struct device *dev = trans->dev; 1052 const struct iwl_cfg *cfg = trans->cfg; 1053 int n_channels; 1054 int n_used = 0; 1055 struct ieee80211_supported_band *sband; 1056 1057 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 1058 sbands_flags, v4); 1059 sband = &data->bands[NL80211_BAND_2GHZ]; 1060 sband->band = NL80211_BAND_2GHZ; 1061 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 1062 sband->n_bitrates = N_RATES_24; 1063 n_used += iwl_init_sband_channels(data, sband, n_channels, 1064 NL80211_BAND_2GHZ); 1065 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 1066 tx_chains, rx_chains); 1067 1068 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1069 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1070 fw); 1071 1072 sband = &data->bands[NL80211_BAND_5GHZ]; 1073 sband->band = NL80211_BAND_5GHZ; 1074 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1075 sband->n_bitrates = N_RATES_52; 1076 n_used += iwl_init_sband_channels(data, sband, n_channels, 1077 NL80211_BAND_5GHZ); 1078 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 1079 tx_chains, rx_chains); 1080 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 1081 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 1082 tx_chains, rx_chains); 1083 1084 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1085 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1086 fw); 1087 1088 /* 6GHz band. */ 1089 sband = &data->bands[NL80211_BAND_6GHZ]; 1090 sband->band = NL80211_BAND_6GHZ; 1091 /* use the same rates as 5GHz band */ 1092 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1093 sband->n_bitrates = N_RATES_52; 1094 n_used += iwl_init_sband_channels(data, sband, n_channels, 1095 NL80211_BAND_6GHZ); 1096 1097 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1098 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1099 fw); 1100 else 1101 sband->n_channels = 0; 1102 if (n_channels != n_used) 1103 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 1104 n_used, n_channels); 1105 } 1106 1107 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 1108 const __le16 *phy_sku) 1109 { 1110 if (cfg->nvm_type != IWL_NVM_EXT) 1111 return le16_to_cpup(nvm_sw + SKU); 1112 1113 return le32_to_cpup((const __le32 *)(phy_sku + SKU_FAMILY_8000)); 1114 } 1115 1116 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 1117 { 1118 if (cfg->nvm_type != IWL_NVM_EXT) 1119 return le16_to_cpup(nvm_sw + NVM_VERSION); 1120 else 1121 return le32_to_cpup((const __le32 *)(nvm_sw + 1122 NVM_VERSION_EXT_NVM)); 1123 } 1124 1125 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 1126 const __le16 *phy_sku) 1127 { 1128 if (cfg->nvm_type != IWL_NVM_EXT) 1129 return le16_to_cpup(nvm_sw + RADIO_CFG); 1130 1131 return le32_to_cpup((const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 1132 1133 } 1134 1135 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 1136 { 1137 int n_hw_addr; 1138 1139 if (cfg->nvm_type != IWL_NVM_EXT) 1140 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 1141 1142 n_hw_addr = le32_to_cpup((const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 1143 1144 return n_hw_addr & N_HW_ADDR_MASK; 1145 } 1146 1147 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 1148 struct iwl_nvm_data *data, 1149 u32 radio_cfg) 1150 { 1151 if (cfg->nvm_type != IWL_NVM_EXT) { 1152 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 1153 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 1154 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 1155 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 1156 return; 1157 } 1158 1159 /* set the radio configuration for family 8000 */ 1160 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 1161 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 1162 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 1163 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 1164 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 1165 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 1166 } 1167 1168 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 1169 { 1170 const u8 *hw_addr; 1171 1172 hw_addr = (const u8 *)&mac_addr0; 1173 dest[0] = hw_addr[3]; 1174 dest[1] = hw_addr[2]; 1175 dest[2] = hw_addr[1]; 1176 dest[3] = hw_addr[0]; 1177 1178 hw_addr = (const u8 *)&mac_addr1; 1179 dest[4] = hw_addr[1]; 1180 dest[5] = hw_addr[0]; 1181 } 1182 1183 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 1184 struct iwl_nvm_data *data) 1185 { 1186 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, 1187 CSR_MAC_ADDR0_STRAP(trans))); 1188 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, 1189 CSR_MAC_ADDR1_STRAP(trans))); 1190 1191 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1192 /* 1193 * If the OEM fused a valid address, use it instead of the one in the 1194 * OTP 1195 */ 1196 if (is_valid_ether_addr(data->hw_addr)) 1197 return; 1198 1199 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); 1200 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); 1201 1202 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1203 } 1204 1205 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 1206 const struct iwl_cfg *cfg, 1207 struct iwl_nvm_data *data, 1208 const __le16 *mac_override, 1209 const __be16 *nvm_hw) 1210 { 1211 const u8 *hw_addr; 1212 1213 if (mac_override) { 1214 static const u8 reserved_mac[] = { 1215 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1216 }; 1217 1218 hw_addr = (const u8 *)(mac_override + 1219 MAC_ADDRESS_OVERRIDE_EXT_NVM); 1220 1221 /* 1222 * Store the MAC address from MAO section. 1223 * No byte swapping is required in MAO section 1224 */ 1225 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 1226 1227 /* 1228 * Force the use of the OTP MAC address in case of reserved MAC 1229 * address in the NVM, or if address is given but invalid. 1230 */ 1231 if (is_valid_ether_addr(data->hw_addr) && 1232 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 1233 return; 1234 1235 IWL_ERR(trans, 1236 "mac address from nvm override section is not valid\n"); 1237 } 1238 1239 if (nvm_hw) { 1240 /* read the mac address from WFMP registers */ 1241 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 1242 WFMP_MAC_ADDR_0)); 1243 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 1244 WFMP_MAC_ADDR_1)); 1245 1246 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1247 1248 return; 1249 } 1250 1251 IWL_ERR(trans, "mac address is not found\n"); 1252 } 1253 1254 static int iwl_set_hw_address(struct iwl_trans *trans, 1255 const struct iwl_cfg *cfg, 1256 struct iwl_nvm_data *data, const __be16 *nvm_hw, 1257 const __le16 *mac_override) 1258 { 1259 if (cfg->mac_addr_from_csr) { 1260 iwl_set_hw_address_from_csr(trans, data); 1261 } else if (cfg->nvm_type != IWL_NVM_EXT) { 1262 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 1263 1264 /* The byte order is little endian 16 bit, meaning 214365 */ 1265 data->hw_addr[0] = hw_addr[1]; 1266 data->hw_addr[1] = hw_addr[0]; 1267 data->hw_addr[2] = hw_addr[3]; 1268 data->hw_addr[3] = hw_addr[2]; 1269 data->hw_addr[4] = hw_addr[5]; 1270 data->hw_addr[5] = hw_addr[4]; 1271 } else { 1272 iwl_set_hw_address_family_8000(trans, cfg, data, 1273 mac_override, nvm_hw); 1274 } 1275 1276 if (!is_valid_ether_addr(data->hw_addr)) { 1277 IWL_ERR(trans, "no valid mac address was found\n"); 1278 return -EINVAL; 1279 } 1280 1281 if (!trans->csme_own) 1282 IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n", 1283 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR)); 1284 1285 return 0; 1286 } 1287 1288 static bool 1289 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1290 const __be16 *nvm_hw) 1291 { 1292 /* 1293 * Workaround a bug in Indonesia SKUs where the regulatory in 1294 * some 7000-family OTPs erroneously allow wide channels in 1295 * 5GHz. To check for Indonesia, we take the SKU value from 1296 * bits 1-4 in the subsystem ID and check if it is either 5 or 1297 * 9. In those cases, we need to force-disable wide channels 1298 * in 5GHz otherwise the FW will throw a sysassert when we try 1299 * to use them. 1300 */ 1301 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1302 /* 1303 * Unlike the other sections in the NVM, the hw 1304 * section uses big-endian. 1305 */ 1306 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 1307 u8 sku = (subsystem_id & 0x1e) >> 1; 1308 1309 if (sku == 5 || sku == 9) { 1310 IWL_DEBUG_EEPROM(trans->dev, 1311 "disabling wide channels in 5GHz (0x%0x %d)\n", 1312 subsystem_id, sku); 1313 return true; 1314 } 1315 } 1316 1317 return false; 1318 } 1319 1320 struct iwl_nvm_data * 1321 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1322 const struct iwl_mei_nvm *mei_nvm, 1323 const struct iwl_fw *fw) 1324 { 1325 struct iwl_nvm_data *data; 1326 u32 sbands_flags = 0; 1327 u8 rx_chains = fw->valid_rx_ant; 1328 u8 tx_chains = fw->valid_rx_ant; 1329 1330 if (cfg->uhb_supported) 1331 data = kzalloc(struct_size(data, channels, 1332 IWL_NVM_NUM_CHANNELS_UHB), 1333 GFP_KERNEL); 1334 else 1335 data = kzalloc(struct_size(data, channels, 1336 IWL_NVM_NUM_CHANNELS_EXT), 1337 GFP_KERNEL); 1338 if (!data) 1339 return NULL; 1340 1341 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) != 1342 IWL_NVM_NUM_CHANNELS_UHB); 1343 data->nvm_version = mei_nvm->nvm_version; 1344 1345 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg); 1346 if (data->valid_tx_ant) 1347 tx_chains &= data->valid_tx_ant; 1348 if (data->valid_rx_ant) 1349 rx_chains &= data->valid_rx_ant; 1350 1351 data->sku_cap_mimo_disabled = false; 1352 data->sku_cap_band_24ghz_enable = true; 1353 data->sku_cap_band_52ghz_enable = true; 1354 data->sku_cap_11n_enable = 1355 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL); 1356 data->sku_cap_11ac_enable = true; 1357 data->sku_cap_11ax_enable = 1358 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT; 1359 1360 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT; 1361 1362 data->n_hw_addrs = mei_nvm->n_hw_addrs; 1363 /* If no valid mac address was found - bail out */ 1364 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) { 1365 kfree(data); 1366 return NULL; 1367 } 1368 1369 if (data->lar_enabled && 1370 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1371 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1372 1373 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains, 1374 sbands_flags, true, fw); 1375 1376 return data; 1377 } 1378 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data); 1379 1380 struct iwl_nvm_data * 1381 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1382 const struct iwl_fw *fw, 1383 const __be16 *nvm_hw, const __le16 *nvm_sw, 1384 const __le16 *nvm_calib, const __le16 *regulatory, 1385 const __le16 *mac_override, const __le16 *phy_sku, 1386 u8 tx_chains, u8 rx_chains) 1387 { 1388 struct iwl_nvm_data *data; 1389 bool lar_enabled; 1390 u32 sku, radio_cfg; 1391 u32 sbands_flags = 0; 1392 u16 lar_config; 1393 const __le16 *ch_section; 1394 1395 if (cfg->uhb_supported) 1396 data = kzalloc(struct_size(data, channels, 1397 IWL_NVM_NUM_CHANNELS_UHB), 1398 GFP_KERNEL); 1399 else if (cfg->nvm_type != IWL_NVM_EXT) 1400 data = kzalloc(struct_size(data, channels, 1401 IWL_NVM_NUM_CHANNELS), 1402 GFP_KERNEL); 1403 else 1404 data = kzalloc(struct_size(data, channels, 1405 IWL_NVM_NUM_CHANNELS_EXT), 1406 GFP_KERNEL); 1407 if (!data) 1408 return NULL; 1409 1410 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 1411 1412 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 1413 iwl_set_radio_cfg(cfg, data, radio_cfg); 1414 if (data->valid_tx_ant) 1415 tx_chains &= data->valid_tx_ant; 1416 if (data->valid_rx_ant) 1417 rx_chains &= data->valid_rx_ant; 1418 1419 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 1420 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 1421 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 1422 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 1423 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1424 data->sku_cap_11n_enable = false; 1425 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 1426 (sku & NVM_SKU_CAP_11AC_ENABLE); 1427 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 1428 1429 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 1430 1431 if (cfg->nvm_type != IWL_NVM_EXT) { 1432 /* Checking for required sections */ 1433 if (!nvm_calib) { 1434 IWL_ERR(trans, 1435 "Can't parse empty Calib NVM sections\n"); 1436 kfree(data); 1437 return NULL; 1438 } 1439 1440 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1441 ®ulatory[NVM_CHANNELS_SDP] : 1442 &nvm_sw[NVM_CHANNELS]; 1443 1444 /* in family 8000 Xtal calibration values moved to OTP */ 1445 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 1446 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 1447 lar_enabled = true; 1448 } else { 1449 u16 lar_offset = data->nvm_version < 0xE39 ? 1450 NVM_LAR_OFFSET_OLD : 1451 NVM_LAR_OFFSET; 1452 1453 lar_config = le16_to_cpup(regulatory + lar_offset); 1454 data->lar_enabled = !!(lar_config & 1455 NVM_LAR_ENABLED); 1456 lar_enabled = data->lar_enabled; 1457 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1458 } 1459 1460 /* If no valid mac address was found - bail out */ 1461 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1462 kfree(data); 1463 return NULL; 1464 } 1465 1466 if (lar_enabled && 1467 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1468 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1469 1470 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1471 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1472 1473 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1474 sbands_flags, false, fw); 1475 data->calib_version = 255; 1476 1477 return data; 1478 } 1479 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1480 1481 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1482 int ch_idx, u16 nvm_flags, 1483 struct iwl_reg_capa reg_capa, 1484 const struct iwl_cfg *cfg) 1485 { 1486 u32 flags = NL80211_RRF_NO_HT40; 1487 1488 if (ch_idx < NUM_2GHZ_CHANNELS && 1489 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1490 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1491 flags &= ~NL80211_RRF_NO_HT40PLUS; 1492 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1493 flags &= ~NL80211_RRF_NO_HT40MINUS; 1494 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1495 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1496 flags &= ~NL80211_RRF_NO_HT40PLUS; 1497 else 1498 flags &= ~NL80211_RRF_NO_HT40MINUS; 1499 } 1500 1501 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1502 flags |= NL80211_RRF_NO_80MHZ; 1503 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1504 flags |= NL80211_RRF_NO_160MHZ; 1505 1506 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1507 flags |= NL80211_RRF_NO_IR; 1508 1509 if (nvm_flags & NVM_CHANNEL_RADAR) 1510 flags |= NL80211_RRF_DFS; 1511 1512 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1513 flags |= NL80211_RRF_NO_OUTDOOR; 1514 1515 /* Set the GO concurrent flag only in case that NO_IR is set. 1516 * Otherwise it is meaningless 1517 */ 1518 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1519 (flags & NL80211_RRF_NO_IR)) 1520 flags |= NL80211_RRF_GO_CONCURRENT; 1521 1522 /* 1523 * reg_capa is per regulatory domain so apply it for every channel 1524 */ 1525 if (ch_idx >= NUM_2GHZ_CHANNELS) { 1526 if (!reg_capa.allow_40mhz) 1527 flags |= NL80211_RRF_NO_HT40; 1528 1529 if (!reg_capa.allow_80mhz) 1530 flags |= NL80211_RRF_NO_80MHZ; 1531 1532 if (!reg_capa.allow_160mhz) 1533 flags |= NL80211_RRF_NO_160MHZ; 1534 } 1535 if (reg_capa.disable_11ax) 1536 flags |= NL80211_RRF_NO_HE; 1537 1538 return flags; 1539 } 1540 1541 static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver) 1542 { 1543 struct iwl_reg_capa reg_capa; 1544 1545 if (resp_ver >= REG_CAPA_V2_RESP_VER) { 1546 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED; 1547 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED; 1548 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED; 1549 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED; 1550 } else { 1551 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN); 1552 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED; 1553 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED; 1554 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED; 1555 } 1556 return reg_capa; 1557 } 1558 1559 struct ieee80211_regdomain * 1560 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1561 int num_of_ch, __le32 *channels, u16 fw_mcc, 1562 u16 geo_info, u16 cap, u8 resp_ver) 1563 { 1564 int ch_idx; 1565 u16 ch_flags; 1566 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1567 const u16 *nvm_chan; 1568 struct ieee80211_regdomain *regd, *copy_rd; 1569 struct ieee80211_reg_rule *rule; 1570 enum nl80211_band band; 1571 int center_freq, prev_center_freq = 0; 1572 int valid_rules = 0; 1573 bool new_rule; 1574 int max_num_ch; 1575 struct iwl_reg_capa reg_capa; 1576 1577 if (cfg->uhb_supported) { 1578 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1579 nvm_chan = iwl_uhb_nvm_channels; 1580 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1581 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1582 nvm_chan = iwl_ext_nvm_channels; 1583 } else { 1584 max_num_ch = IWL_NVM_NUM_CHANNELS; 1585 nvm_chan = iwl_nvm_channels; 1586 } 1587 1588 if (num_of_ch > max_num_ch) { 1589 IWL_DEBUG_DEV(dev, IWL_DL_LAR, 1590 "Num of channels (%d) is greater than expected. Truncating to %d\n", 1591 num_of_ch, max_num_ch); 1592 num_of_ch = max_num_ch; 1593 } 1594 1595 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1596 return ERR_PTR(-EINVAL); 1597 1598 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1599 num_of_ch); 1600 1601 /* build a regdomain rule for every valid channel */ 1602 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1603 if (!regd) 1604 return ERR_PTR(-ENOMEM); 1605 1606 /* set alpha2 from FW. */ 1607 regd->alpha2[0] = fw_mcc >> 8; 1608 regd->alpha2[1] = fw_mcc & 0xff; 1609 1610 /* parse regulatory capability flags */ 1611 reg_capa = iwl_get_reg_capa(cap, resp_ver); 1612 1613 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1614 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1615 band = iwl_nl80211_band_from_channel_idx(ch_idx); 1616 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1617 band); 1618 new_rule = false; 1619 1620 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1621 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1622 nvm_chan[ch_idx], ch_flags); 1623 continue; 1624 } 1625 1626 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1627 ch_flags, reg_capa, 1628 cfg); 1629 1630 /* we can't continue the same rule */ 1631 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1632 center_freq - prev_center_freq > 20) { 1633 valid_rules++; 1634 new_rule = true; 1635 } 1636 1637 rule = ®d->reg_rules[valid_rules - 1]; 1638 1639 if (new_rule) 1640 rule->freq_range.start_freq_khz = 1641 MHZ_TO_KHZ(center_freq - 10); 1642 1643 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1644 1645 /* this doesn't matter - not used by FW */ 1646 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1647 rule->power_rule.max_eirp = 1648 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1649 1650 rule->flags = reg_rule_flags; 1651 1652 /* rely on auto-calculation to merge BW of contiguous chans */ 1653 rule->flags |= NL80211_RRF_AUTO_BW; 1654 rule->freq_range.max_bandwidth_khz = 0; 1655 1656 prev_center_freq = center_freq; 1657 prev_reg_rule_flags = reg_rule_flags; 1658 1659 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1660 nvm_chan[ch_idx], ch_flags); 1661 1662 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1663 band == NL80211_BAND_2GHZ) 1664 continue; 1665 1666 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1667 } 1668 1669 /* 1670 * Certain firmware versions might report no valid channels 1671 * if booted in RF-kill, i.e. not all calibrations etc. are 1672 * running. We'll get out of this situation later when the 1673 * rfkill is removed and we update the regdomain again, but 1674 * since cfg80211 doesn't accept an empty regdomain, add a 1675 * dummy (unusable) rule here in this case so we can init. 1676 */ 1677 if (!valid_rules) { 1678 valid_rules = 1; 1679 rule = ®d->reg_rules[valid_rules - 1]; 1680 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412); 1681 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413); 1682 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1); 1683 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1684 rule->power_rule.max_eirp = 1685 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1686 } 1687 1688 regd->n_reg_rules = valid_rules; 1689 1690 /* 1691 * Narrow down regdom for unused regulatory rules to prevent hole 1692 * between reg rules to wmm rules. 1693 */ 1694 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1695 GFP_KERNEL); 1696 if (!copy_rd) 1697 copy_rd = ERR_PTR(-ENOMEM); 1698 1699 kfree(regd); 1700 return copy_rd; 1701 } 1702 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1703 1704 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1705 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1706 #define MAX_NVM_FILE_LEN 16384 1707 1708 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1709 unsigned int len) 1710 { 1711 #define IWL_4165_DEVICE_ID 0x5501 1712 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1713 1714 if (section == NVM_SECTION_TYPE_PHY_SKU && 1715 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1716 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1717 /* OTP 0x52 bug work around: it's a 1x1 device */ 1718 data[3] = ANT_B | (ANT_B << 4); 1719 } 1720 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1721 1722 /* 1723 * Reads external NVM from a file into mvm->nvm_sections 1724 * 1725 * HOW TO CREATE THE NVM FILE FORMAT: 1726 * ------------------------------ 1727 * 1. create hex file, format: 1728 * 3800 -> header 1729 * 0000 -> header 1730 * 5a40 -> data 1731 * 1732 * rev - 6 bit (word1) 1733 * len - 10 bit (word1) 1734 * id - 4 bit (word2) 1735 * rsv - 12 bit (word2) 1736 * 1737 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1738 * 1739 * 3. create binary file from the hex file 1740 * 1741 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1742 */ 1743 int iwl_read_external_nvm(struct iwl_trans *trans, 1744 const char *nvm_file_name, 1745 struct iwl_nvm_section *nvm_sections) 1746 { 1747 int ret, section_size; 1748 u16 section_id; 1749 const struct firmware *fw_entry; 1750 const struct { 1751 __le16 word1; 1752 __le16 word2; 1753 u8 data[]; 1754 } *file_sec; 1755 const u8 *eof; 1756 u8 *temp; 1757 int max_section_size; 1758 const __le32 *dword_buff; 1759 1760 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1761 #define NVM_WORD2_ID(x) (x >> 12) 1762 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1763 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1764 #define NVM_HEADER_0 (0x2A504C54) 1765 #define NVM_HEADER_1 (0x4E564D2A) 1766 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1767 1768 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1769 1770 /* Maximal size depends on NVM version */ 1771 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1772 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1773 else 1774 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1775 1776 /* 1777 * Obtain NVM image via request_firmware. Since we already used 1778 * request_firmware_nowait() for the firmware binary load and only 1779 * get here after that we assume the NVM request can be satisfied 1780 * synchronously. 1781 */ 1782 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1783 if (ret) { 1784 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1785 nvm_file_name, ret); 1786 return ret; 1787 } 1788 1789 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1790 nvm_file_name, fw_entry->size); 1791 1792 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1793 IWL_ERR(trans, "NVM file too large\n"); 1794 ret = -EINVAL; 1795 goto out; 1796 } 1797 1798 eof = fw_entry->data + fw_entry->size; 1799 dword_buff = (const __le32 *)fw_entry->data; 1800 1801 /* some NVM file will contain a header. 1802 * The header is identified by 2 dwords header as follow: 1803 * dword[0] = 0x2A504C54 1804 * dword[1] = 0x4E564D2A 1805 * 1806 * This header must be skipped when providing the NVM data to the FW. 1807 */ 1808 if (fw_entry->size > NVM_HEADER_SIZE && 1809 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1810 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1811 file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE); 1812 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1813 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1814 le32_to_cpu(dword_buff[3])); 1815 1816 /* nvm file validation, dword_buff[2] holds the file version */ 1817 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1818 trans->hw_rev_step == SILICON_C_STEP && 1819 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1820 ret = -EFAULT; 1821 goto out; 1822 } 1823 } else { 1824 file_sec = (const void *)fw_entry->data; 1825 } 1826 1827 while (true) { 1828 if (file_sec->data > eof) { 1829 IWL_ERR(trans, 1830 "ERROR - NVM file too short for section header\n"); 1831 ret = -EINVAL; 1832 break; 1833 } 1834 1835 /* check for EOF marker */ 1836 if (!file_sec->word1 && !file_sec->word2) { 1837 ret = 0; 1838 break; 1839 } 1840 1841 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1842 section_size = 1843 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1844 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1845 } else { 1846 section_size = 2 * EXT_NVM_WORD2_LEN( 1847 le16_to_cpu(file_sec->word2)); 1848 section_id = EXT_NVM_WORD1_ID( 1849 le16_to_cpu(file_sec->word1)); 1850 } 1851 1852 if (section_size > max_section_size) { 1853 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1854 section_size); 1855 ret = -EINVAL; 1856 break; 1857 } 1858 1859 if (!section_size) { 1860 IWL_ERR(trans, "ERROR - section empty\n"); 1861 ret = -EINVAL; 1862 break; 1863 } 1864 1865 if (file_sec->data + section_size > eof) { 1866 IWL_ERR(trans, 1867 "ERROR - NVM file too short for section (%d bytes)\n", 1868 section_size); 1869 ret = -EINVAL; 1870 break; 1871 } 1872 1873 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1874 "Invalid NVM section ID %d\n", section_id)) { 1875 ret = -EINVAL; 1876 break; 1877 } 1878 1879 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1880 if (!temp) { 1881 ret = -ENOMEM; 1882 break; 1883 } 1884 1885 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1886 1887 kfree(nvm_sections[section_id].data); 1888 nvm_sections[section_id].data = temp; 1889 nvm_sections[section_id].length = section_size; 1890 1891 /* advance to the next section */ 1892 file_sec = (const void *)(file_sec->data + section_size); 1893 } 1894 out: 1895 release_firmware(fw_entry); 1896 return ret; 1897 } 1898 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1899 1900 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1901 const struct iwl_fw *fw) 1902 { 1903 struct iwl_nvm_get_info cmd = {}; 1904 struct iwl_nvm_data *nvm; 1905 struct iwl_host_cmd hcmd = { 1906 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1907 .data = { &cmd, }, 1908 .len = { sizeof(cmd) }, 1909 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1910 }; 1911 int ret; 1912 bool empty_otp; 1913 u32 mac_flags; 1914 u32 sbands_flags = 0; 1915 /* 1916 * All the values in iwl_nvm_get_info_rsp v4 are the same as 1917 * in v3, except for the channel profile part of the 1918 * regulatory. So we can just access the new struct, with the 1919 * exception of the latter. 1920 */ 1921 struct iwl_nvm_get_info_rsp *rsp; 1922 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 1923 bool v4 = fw_has_api(&fw->ucode_capa, 1924 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 1925 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 1926 void *channel_profile; 1927 1928 ret = iwl_trans_send_cmd(trans, &hcmd); 1929 if (ret) 1930 return ERR_PTR(ret); 1931 1932 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 1933 "Invalid payload len in NVM response from FW %d", 1934 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1935 ret = -EINVAL; 1936 goto out; 1937 } 1938 1939 rsp = (void *)hcmd.resp_pkt->data; 1940 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1941 NVM_GENERAL_FLAGS_EMPTY_OTP); 1942 if (empty_otp) 1943 IWL_INFO(trans, "OTP is empty\n"); 1944 1945 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 1946 if (!nvm) { 1947 ret = -ENOMEM; 1948 goto out; 1949 } 1950 1951 iwl_set_hw_address_from_csr(trans, nvm); 1952 /* TODO: if platform NVM has MAC address - override it here */ 1953 1954 if (!is_valid_ether_addr(nvm->hw_addr)) { 1955 IWL_ERR(trans, "no valid mac address was found\n"); 1956 ret = -EINVAL; 1957 goto err_free; 1958 } 1959 1960 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1961 1962 /* Initialize general data */ 1963 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1964 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1965 if (nvm->n_hw_addrs == 0) 1966 IWL_WARN(trans, 1967 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1968 empty_otp); 1969 1970 /* Initialize MAC sku data */ 1971 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1972 nvm->sku_cap_11ac_enable = 1973 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1974 nvm->sku_cap_11n_enable = 1975 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1976 nvm->sku_cap_11ax_enable = 1977 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1978 nvm->sku_cap_band_24ghz_enable = 1979 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1980 nvm->sku_cap_band_52ghz_enable = 1981 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1982 nvm->sku_cap_mimo_disabled = 1983 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1984 if (CSR_HW_RFID_TYPE(trans->hw_rf_id) == IWL_CFG_RF_TYPE_FM) 1985 nvm->sku_cap_11be_enable = true; 1986 1987 /* Initialize PHY sku data */ 1988 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1989 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1990 1991 if (le32_to_cpu(rsp->regulatory.lar_enabled) && 1992 fw_has_capa(&fw->ucode_capa, 1993 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) { 1994 nvm->lar_enabled = true; 1995 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1996 } 1997 1998 rsp_v3 = (void *)rsp; 1999 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 2000 (void *)rsp_v3->regulatory.channel_profile; 2001 2002 iwl_init_sbands(trans, nvm, 2003 channel_profile, 2004 nvm->valid_tx_ant & fw->valid_tx_ant, 2005 nvm->valid_rx_ant & fw->valid_rx_ant, 2006 sbands_flags, v4, fw); 2007 2008 iwl_free_resp(&hcmd); 2009 return nvm; 2010 2011 err_free: 2012 kfree(nvm); 2013 out: 2014 iwl_free_resp(&hcmd); 2015 return ERR_PTR(ret); 2016 } 2017 IWL_EXPORT_SYMBOL(iwl_get_nvm); 2018