1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 *****************************************************************************/ 63 #include <linux/types.h> 64 #include <linux/slab.h> 65 #include <linux/export.h> 66 #include <linux/etherdevice.h> 67 #include <linux/pci.h> 68 #include <linux/firmware.h> 69 70 #include "iwl-drv.h" 71 #include "iwl-modparams.h" 72 #include "iwl-nvm-parse.h" 73 #include "iwl-prph.h" 74 #include "iwl-io.h" 75 #include "iwl-csr.h" 76 #include "fw/acpi.h" 77 #include "fw/api/nvm-reg.h" 78 #include "fw/api/commands.h" 79 #include "fw/api/cmdhdr.h" 80 #include "fw/img.h" 81 82 /* NVM offsets (in words) definitions */ 83 enum nvm_offsets { 84 /* NVM HW-Section offset (in words) definitions */ 85 SUBSYSTEM_ID = 0x0A, 86 HW_ADDR = 0x15, 87 88 /* NVM SW-Section offset (in words) definitions */ 89 NVM_SW_SECTION = 0x1C0, 90 NVM_VERSION = 0, 91 RADIO_CFG = 1, 92 SKU = 2, 93 N_HW_ADDRS = 3, 94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 95 96 /* NVM calibration section offset (in words) definitions */ 97 NVM_CALIB_SECTION = 0x2B8, 98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 99 100 /* NVM REGULATORY -Section offset (in words) definitions */ 101 NVM_CHANNELS_SDP = 0, 102 }; 103 104 enum ext_nvm_offsets { 105 /* NVM HW-Section offset (in words) definitions */ 106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 107 108 /* NVM SW-Section offset (in words) definitions */ 109 NVM_VERSION_EXT_NVM = 0, 110 RADIO_CFG_FAMILY_EXT_NVM = 0, 111 SKU_FAMILY_8000 = 2, 112 N_HW_ADDRS_FAMILY_8000 = 3, 113 114 /* NVM REGULATORY -Section offset (in words) definitions */ 115 NVM_CHANNELS_EXTENDED = 0, 116 NVM_LAR_OFFSET_OLD = 0x4C7, 117 NVM_LAR_OFFSET = 0x507, 118 NVM_LAR_ENABLED = 0x7, 119 }; 120 121 /* SKU Capabilities (actual values from NVM definition) */ 122 enum nvm_sku_bits { 123 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 124 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 125 NVM_SKU_CAP_11N_ENABLE = BIT(2), 126 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 128 }; 129 130 /* 131 * These are the channel numbers in the order that they are stored in the NVM 132 */ 133 static const u16 iwl_nvm_channels[] = { 134 /* 2.4 GHz */ 135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 136 /* 5 GHz */ 137 36, 40, 44 , 48, 52, 56, 60, 64, 138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 139 149, 153, 157, 161, 165 140 }; 141 142 static const u16 iwl_ext_nvm_channels[] = { 143 /* 2.4 GHz */ 144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 145 /* 5 GHz */ 146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148 149, 153, 157, 161, 165, 169, 173, 177, 181 149 }; 150 151 static const u16 iwl_uhb_nvm_channels[] = { 152 /* 2.4 GHz */ 153 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 154 /* 5 GHz */ 155 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 156 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 157 149, 153, 157, 161, 165, 169, 173, 177, 181, 158 /* 6-7 GHz */ 159 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 160 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 161 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 162 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 163 }; 164 165 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 166 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 167 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 168 #define NUM_2GHZ_CHANNELS 14 169 #define FIRST_2GHZ_HT_MINUS 5 170 #define LAST_2GHZ_HT_PLUS 9 171 #define N_HW_ADDR_MASK 0xF 172 173 /* rate data (static) */ 174 static struct ieee80211_rate iwl_cfg80211_rates[] = { 175 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 176 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 177 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 178 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 179 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 180 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 181 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 182 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 183 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 184 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 185 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 186 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 187 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 188 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 189 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 190 }; 191 #define RATES_24_OFFS 0 192 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 193 #define RATES_52_OFFS 4 194 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 195 196 /** 197 * enum iwl_nvm_channel_flags - channel flags in NVM 198 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 199 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 200 * @NVM_CHANNEL_ACTIVE: active scanning allowed 201 * @NVM_CHANNEL_RADAR: radar detection required 202 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 203 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 204 * on same channel on 2.4 or same UNII band on 5.2 205 * @NVM_CHANNEL_UNIFORM: uniform spreading required 206 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 207 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 208 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 209 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 210 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 211 */ 212 enum iwl_nvm_channel_flags { 213 NVM_CHANNEL_VALID = BIT(0), 214 NVM_CHANNEL_IBSS = BIT(1), 215 NVM_CHANNEL_ACTIVE = BIT(3), 216 NVM_CHANNEL_RADAR = BIT(4), 217 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 218 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 219 NVM_CHANNEL_UNIFORM = BIT(7), 220 NVM_CHANNEL_20MHZ = BIT(8), 221 NVM_CHANNEL_40MHZ = BIT(9), 222 NVM_CHANNEL_80MHZ = BIT(10), 223 NVM_CHANNEL_160MHZ = BIT(11), 224 NVM_CHANNEL_DC_HIGH = BIT(12), 225 }; 226 227 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 228 int chan, u32 flags) 229 { 230 #define CHECK_AND_PRINT_I(x) \ 231 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 232 233 if (!(flags & NVM_CHANNEL_VALID)) { 234 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 235 chan, flags); 236 return; 237 } 238 239 /* Note: already can print up to 101 characters, 110 is the limit! */ 240 IWL_DEBUG_DEV(dev, level, 241 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 242 chan, flags, 243 CHECK_AND_PRINT_I(VALID), 244 CHECK_AND_PRINT_I(IBSS), 245 CHECK_AND_PRINT_I(ACTIVE), 246 CHECK_AND_PRINT_I(RADAR), 247 CHECK_AND_PRINT_I(INDOOR_ONLY), 248 CHECK_AND_PRINT_I(GO_CONCURRENT), 249 CHECK_AND_PRINT_I(UNIFORM), 250 CHECK_AND_PRINT_I(20MHZ), 251 CHECK_AND_PRINT_I(40MHZ), 252 CHECK_AND_PRINT_I(80MHZ), 253 CHECK_AND_PRINT_I(160MHZ), 254 CHECK_AND_PRINT_I(DC_HIGH)); 255 #undef CHECK_AND_PRINT_I 256 } 257 258 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 259 u32 nvm_flags, const struct iwl_cfg *cfg) 260 { 261 u32 flags = IEEE80211_CHAN_NO_HT40; 262 263 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 264 if (ch_num <= LAST_2GHZ_HT_PLUS) 265 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 266 if (ch_num >= FIRST_2GHZ_HT_MINUS) 267 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 268 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 269 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 270 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 271 else 272 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 273 } 274 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 275 flags |= IEEE80211_CHAN_NO_80MHZ; 276 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 277 flags |= IEEE80211_CHAN_NO_160MHZ; 278 279 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 280 flags |= IEEE80211_CHAN_NO_IR; 281 282 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 283 flags |= IEEE80211_CHAN_NO_IR; 284 285 if (nvm_flags & NVM_CHANNEL_RADAR) 286 flags |= IEEE80211_CHAN_RADAR; 287 288 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 289 flags |= IEEE80211_CHAN_INDOOR_ONLY; 290 291 /* Set the GO concurrent flag only in case that NO_IR is set. 292 * Otherwise it is meaningless 293 */ 294 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 295 (flags & IEEE80211_CHAN_NO_IR)) 296 flags |= IEEE80211_CHAN_IR_CONCURRENT; 297 298 return flags; 299 } 300 301 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 302 { 303 if (ch_idx >= NUM_2GHZ_CHANNELS) 304 return NL80211_BAND_5GHZ; 305 return NL80211_BAND_2GHZ; 306 } 307 308 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 309 struct iwl_nvm_data *data, 310 const void * const nvm_ch_flags, 311 u32 sbands_flags, bool v4) 312 { 313 int ch_idx; 314 int n_channels = 0; 315 struct ieee80211_channel *channel; 316 u32 ch_flags; 317 int num_of_ch; 318 const u16 *nvm_chan; 319 320 if (cfg->uhb_supported) { 321 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 322 nvm_chan = iwl_uhb_nvm_channels; 323 } else if (cfg->nvm_type == IWL_NVM_EXT) { 324 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 325 nvm_chan = iwl_ext_nvm_channels; 326 } else { 327 num_of_ch = IWL_NVM_NUM_CHANNELS; 328 nvm_chan = iwl_nvm_channels; 329 } 330 331 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 332 enum nl80211_band band = 333 iwl_nl80211_band_from_channel_idx(ch_idx); 334 335 if (v4) 336 ch_flags = 337 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx); 338 else 339 ch_flags = 340 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx); 341 342 if (band == NL80211_BAND_5GHZ && 343 !data->sku_cap_band_52ghz_enable) 344 continue; 345 346 /* workaround to disable wide channels in 5GHz */ 347 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 348 band == NL80211_BAND_5GHZ) { 349 ch_flags &= ~(NVM_CHANNEL_40MHZ | 350 NVM_CHANNEL_80MHZ | 351 NVM_CHANNEL_160MHZ); 352 } 353 354 if (ch_flags & NVM_CHANNEL_160MHZ) 355 data->vht160_supported = true; 356 357 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 358 !(ch_flags & NVM_CHANNEL_VALID)) { 359 /* 360 * Channels might become valid later if lar is 361 * supported, hence we still want to add them to 362 * the list of supported channels to cfg80211. 363 */ 364 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 365 nvm_chan[ch_idx], ch_flags); 366 continue; 367 } 368 369 channel = &data->channels[n_channels]; 370 n_channels++; 371 372 channel->hw_value = nvm_chan[ch_idx]; 373 channel->band = band; 374 channel->center_freq = 375 ieee80211_channel_to_frequency( 376 channel->hw_value, channel->band); 377 378 /* Initialize regulatory-based run-time data */ 379 380 /* 381 * Default value - highest tx power value. max_power 382 * is not used in mvm, and is used for backwards compatibility 383 */ 384 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 385 386 /* don't put limitations in case we're using LAR */ 387 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 388 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 389 ch_idx, band, 390 ch_flags, cfg); 391 else 392 channel->flags = 0; 393 394 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 395 channel->hw_value, ch_flags); 396 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 397 channel->hw_value, channel->max_power); 398 } 399 400 return n_channels; 401 } 402 403 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 404 struct iwl_nvm_data *data, 405 struct ieee80211_sta_vht_cap *vht_cap, 406 u8 tx_chains, u8 rx_chains) 407 { 408 const struct iwl_cfg *cfg = trans->cfg; 409 int num_rx_ants = num_of_ant(rx_chains); 410 int num_tx_ants = num_of_ant(tx_chains); 411 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?: 412 IEEE80211_VHT_MAX_AMPDU_1024K); 413 414 vht_cap->vht_supported = true; 415 416 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 417 IEEE80211_VHT_CAP_RXSTBC_1 | 418 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 419 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 420 max_ampdu_exponent << 421 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 422 423 if (data->vht160_supported) 424 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 425 IEEE80211_VHT_CAP_SHORT_GI_160; 426 427 if (cfg->vht_mu_mimo_supported) 428 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 429 430 if (cfg->ht_params->ldpc) 431 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 432 433 if (data->sku_cap_mimo_disabled) { 434 num_rx_ants = 1; 435 num_tx_ants = 1; 436 } 437 438 if (num_tx_ants > 1) 439 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 440 else 441 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 442 443 switch (iwlwifi_mod_params.amsdu_size) { 444 case IWL_AMSDU_DEF: 445 if (trans->trans_cfg->mq_rx_supported) 446 vht_cap->cap |= 447 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 448 else 449 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 450 break; 451 case IWL_AMSDU_2K: 452 if (trans->trans_cfg->mq_rx_supported) 453 vht_cap->cap |= 454 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 455 else 456 WARN(1, "RB size of 2K is not supported by this device\n"); 457 break; 458 case IWL_AMSDU_4K: 459 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 460 break; 461 case IWL_AMSDU_8K: 462 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 463 break; 464 case IWL_AMSDU_12K: 465 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 466 break; 467 default: 468 break; 469 } 470 471 vht_cap->vht_mcs.rx_mcs_map = 472 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 473 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 474 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 475 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 476 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 477 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 478 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 479 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 480 481 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 482 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 483 /* this works because NOT_SUPPORTED == 3 */ 484 vht_cap->vht_mcs.rx_mcs_map |= 485 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 486 } 487 488 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 489 490 vht_cap->vht_mcs.tx_highest |= 491 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 492 } 493 494 static struct ieee80211_sband_iftype_data iwl_he_capa[] = { 495 { 496 .types_mask = BIT(NL80211_IFTYPE_STATION), 497 .he_cap = { 498 .has_he = true, 499 .he_cap_elem = { 500 .mac_cap_info[0] = 501 IEEE80211_HE_MAC_CAP0_HTC_HE | 502 IEEE80211_HE_MAC_CAP0_TWT_REQ, 503 .mac_cap_info[1] = 504 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 505 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 506 .mac_cap_info[2] = 507 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP | 508 IEEE80211_HE_MAC_CAP2_ACK_EN, 509 .mac_cap_info[3] = 510 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 511 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 512 .mac_cap_info[4] = 513 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU | 514 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 515 .mac_cap_info[5] = 516 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 517 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 518 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 519 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 520 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 521 .phy_cap_info[0] = 522 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 523 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 524 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 525 .phy_cap_info[1] = 526 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 527 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 528 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 529 .phy_cap_info[2] = 530 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 531 .phy_cap_info[3] = 532 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 533 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 534 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 535 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 536 .phy_cap_info[4] = 537 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 538 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 539 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 540 .phy_cap_info[5] = 541 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 542 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2, 543 .phy_cap_info[6] = 544 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 545 .phy_cap_info[7] = 546 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR | 547 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 548 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 549 .phy_cap_info[8] = 550 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 551 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 552 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 553 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 554 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996, 555 .phy_cap_info[9] = 556 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 557 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 558 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 559 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED, 560 }, 561 /* 562 * Set default Tx/Rx HE MCS NSS Support field. 563 * Indicate support for up to 2 spatial streams and all 564 * MCS, without any special cases 565 */ 566 .he_mcs_nss_supp = { 567 .rx_mcs_80 = cpu_to_le16(0xfffa), 568 .tx_mcs_80 = cpu_to_le16(0xfffa), 569 .rx_mcs_160 = cpu_to_le16(0xfffa), 570 .tx_mcs_160 = cpu_to_le16(0xfffa), 571 .rx_mcs_80p80 = cpu_to_le16(0xffff), 572 .tx_mcs_80p80 = cpu_to_le16(0xffff), 573 }, 574 /* 575 * Set default PPE thresholds, with PPET16 set to 0, 576 * PPET8 set to 7 577 */ 578 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 579 }, 580 }, 581 { 582 .types_mask = BIT(NL80211_IFTYPE_AP), 583 .he_cap = { 584 .has_he = true, 585 .he_cap_elem = { 586 .mac_cap_info[0] = 587 IEEE80211_HE_MAC_CAP0_HTC_HE, 588 .mac_cap_info[1] = 589 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 590 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 591 .mac_cap_info[2] = 592 IEEE80211_HE_MAC_CAP2_BSR | 593 IEEE80211_HE_MAC_CAP2_ACK_EN, 594 .mac_cap_info[3] = 595 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 596 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 597 .mac_cap_info[4] = 598 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU, 599 .mac_cap_info[5] = 600 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU, 601 .phy_cap_info[0] = 602 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 603 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 604 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 605 .phy_cap_info[1] = 606 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 607 .phy_cap_info[2] = 608 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 609 .phy_cap_info[3] = 610 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 611 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 612 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 613 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 614 .phy_cap_info[4] = 615 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 616 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 617 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 618 .phy_cap_info[5] = 619 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 620 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2, 621 .phy_cap_info[6] = 622 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 623 .phy_cap_info[7] = 624 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 625 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 626 .phy_cap_info[8] = 627 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 628 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 629 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 630 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 631 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996, 632 .phy_cap_info[9] = 633 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 634 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 635 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED, 636 }, 637 /* 638 * Set default Tx/Rx HE MCS NSS Support field. 639 * Indicate support for up to 2 spatial streams and all 640 * MCS, without any special cases 641 */ 642 .he_mcs_nss_supp = { 643 .rx_mcs_80 = cpu_to_le16(0xfffa), 644 .tx_mcs_80 = cpu_to_le16(0xfffa), 645 .rx_mcs_160 = cpu_to_le16(0xfffa), 646 .tx_mcs_160 = cpu_to_le16(0xfffa), 647 .rx_mcs_80p80 = cpu_to_le16(0xffff), 648 .tx_mcs_80p80 = cpu_to_le16(0xffff), 649 }, 650 /* 651 * Set default PPE thresholds, with PPET16 set to 0, 652 * PPET8 set to 7 653 */ 654 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 655 }, 656 }, 657 }; 658 659 static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband, 660 u8 tx_chains, u8 rx_chains) 661 { 662 sband->iftype_data = iwl_he_capa; 663 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa); 664 665 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */ 666 if ((tx_chains & rx_chains) != ANT_AB) { 667 int i; 668 669 for (i = 0; i < sband->n_iftype_data; i++) { 670 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &= 671 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 672 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &= 673 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 674 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &= 675 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 676 } 677 } 678 } 679 680 static void iwl_init_sbands(struct iwl_trans *trans, 681 struct iwl_nvm_data *data, 682 const void *nvm_ch_flags, u8 tx_chains, 683 u8 rx_chains, u32 sbands_flags, bool v4) 684 { 685 struct device *dev = trans->dev; 686 const struct iwl_cfg *cfg = trans->cfg; 687 int n_channels; 688 int n_used = 0; 689 struct ieee80211_supported_band *sband; 690 691 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 692 sbands_flags, v4); 693 sband = &data->bands[NL80211_BAND_2GHZ]; 694 sband->band = NL80211_BAND_2GHZ; 695 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 696 sband->n_bitrates = N_RATES_24; 697 n_used += iwl_init_sband_channels(data, sband, n_channels, 698 NL80211_BAND_2GHZ); 699 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 700 tx_chains, rx_chains); 701 702 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 703 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 704 705 sband = &data->bands[NL80211_BAND_5GHZ]; 706 sband->band = NL80211_BAND_5GHZ; 707 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 708 sband->n_bitrates = N_RATES_52; 709 n_used += iwl_init_sband_channels(data, sband, n_channels, 710 NL80211_BAND_5GHZ); 711 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 712 tx_chains, rx_chains); 713 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 714 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 715 tx_chains, rx_chains); 716 717 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 718 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 719 720 if (n_channels != n_used) 721 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 722 n_used, n_channels); 723 } 724 725 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 726 const __le16 *phy_sku) 727 { 728 if (cfg->nvm_type != IWL_NVM_EXT) 729 return le16_to_cpup(nvm_sw + SKU); 730 731 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 732 } 733 734 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 735 { 736 if (cfg->nvm_type != IWL_NVM_EXT) 737 return le16_to_cpup(nvm_sw + NVM_VERSION); 738 else 739 return le32_to_cpup((__le32 *)(nvm_sw + 740 NVM_VERSION_EXT_NVM)); 741 } 742 743 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 744 const __le16 *phy_sku) 745 { 746 if (cfg->nvm_type != IWL_NVM_EXT) 747 return le16_to_cpup(nvm_sw + RADIO_CFG); 748 749 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 750 751 } 752 753 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 754 { 755 int n_hw_addr; 756 757 if (cfg->nvm_type != IWL_NVM_EXT) 758 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 759 760 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 761 762 return n_hw_addr & N_HW_ADDR_MASK; 763 } 764 765 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 766 struct iwl_nvm_data *data, 767 u32 radio_cfg) 768 { 769 if (cfg->nvm_type != IWL_NVM_EXT) { 770 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 771 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 772 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 773 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 774 return; 775 } 776 777 /* set the radio configuration for family 8000 */ 778 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 779 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 780 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 781 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 782 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 783 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 784 } 785 786 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 787 { 788 const u8 *hw_addr; 789 790 hw_addr = (const u8 *)&mac_addr0; 791 dest[0] = hw_addr[3]; 792 dest[1] = hw_addr[2]; 793 dest[2] = hw_addr[1]; 794 dest[3] = hw_addr[0]; 795 796 hw_addr = (const u8 *)&mac_addr1; 797 dest[4] = hw_addr[1]; 798 dest[5] = hw_addr[0]; 799 } 800 801 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 802 struct iwl_nvm_data *data) 803 { 804 __le32 mac_addr0 = 805 cpu_to_le32(iwl_read32(trans, 806 trans->trans_cfg->csr->mac_addr0_strap)); 807 __le32 mac_addr1 = 808 cpu_to_le32(iwl_read32(trans, 809 trans->trans_cfg->csr->mac_addr1_strap)); 810 811 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 812 /* 813 * If the OEM fused a valid address, use it instead of the one in the 814 * OTP 815 */ 816 if (is_valid_ether_addr(data->hw_addr)) 817 return; 818 819 mac_addr0 = cpu_to_le32(iwl_read32(trans, 820 trans->trans_cfg->csr->mac_addr0_otp)); 821 mac_addr1 = cpu_to_le32(iwl_read32(trans, 822 trans->trans_cfg->csr->mac_addr1_otp)); 823 824 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 825 } 826 827 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 828 const struct iwl_cfg *cfg, 829 struct iwl_nvm_data *data, 830 const __le16 *mac_override, 831 const __be16 *nvm_hw) 832 { 833 const u8 *hw_addr; 834 835 if (mac_override) { 836 static const u8 reserved_mac[] = { 837 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 838 }; 839 840 hw_addr = (const u8 *)(mac_override + 841 MAC_ADDRESS_OVERRIDE_EXT_NVM); 842 843 /* 844 * Store the MAC address from MAO section. 845 * No byte swapping is required in MAO section 846 */ 847 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 848 849 /* 850 * Force the use of the OTP MAC address in case of reserved MAC 851 * address in the NVM, or if address is given but invalid. 852 */ 853 if (is_valid_ether_addr(data->hw_addr) && 854 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 855 return; 856 857 IWL_ERR(trans, 858 "mac address from nvm override section is not valid\n"); 859 } 860 861 if (nvm_hw) { 862 /* read the mac address from WFMP registers */ 863 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 864 WFMP_MAC_ADDR_0)); 865 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 866 WFMP_MAC_ADDR_1)); 867 868 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 869 870 return; 871 } 872 873 IWL_ERR(trans, "mac address is not found\n"); 874 } 875 876 static int iwl_set_hw_address(struct iwl_trans *trans, 877 const struct iwl_cfg *cfg, 878 struct iwl_nvm_data *data, const __be16 *nvm_hw, 879 const __le16 *mac_override) 880 { 881 if (cfg->mac_addr_from_csr) { 882 iwl_set_hw_address_from_csr(trans, data); 883 } else if (cfg->nvm_type != IWL_NVM_EXT) { 884 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 885 886 /* The byte order is little endian 16 bit, meaning 214365 */ 887 data->hw_addr[0] = hw_addr[1]; 888 data->hw_addr[1] = hw_addr[0]; 889 data->hw_addr[2] = hw_addr[3]; 890 data->hw_addr[3] = hw_addr[2]; 891 data->hw_addr[4] = hw_addr[5]; 892 data->hw_addr[5] = hw_addr[4]; 893 } else { 894 iwl_set_hw_address_family_8000(trans, cfg, data, 895 mac_override, nvm_hw); 896 } 897 898 if (!is_valid_ether_addr(data->hw_addr)) { 899 IWL_ERR(trans, "no valid mac address was found\n"); 900 return -EINVAL; 901 } 902 903 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 904 905 return 0; 906 } 907 908 static bool 909 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 910 const __be16 *nvm_hw) 911 { 912 /* 913 * Workaround a bug in Indonesia SKUs where the regulatory in 914 * some 7000-family OTPs erroneously allow wide channels in 915 * 5GHz. To check for Indonesia, we take the SKU value from 916 * bits 1-4 in the subsystem ID and check if it is either 5 or 917 * 9. In those cases, we need to force-disable wide channels 918 * in 5GHz otherwise the FW will throw a sysassert when we try 919 * to use them. 920 */ 921 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 922 /* 923 * Unlike the other sections in the NVM, the hw 924 * section uses big-endian. 925 */ 926 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 927 u8 sku = (subsystem_id & 0x1e) >> 1; 928 929 if (sku == 5 || sku == 9) { 930 IWL_DEBUG_EEPROM(trans->dev, 931 "disabling wide channels in 5GHz (0x%0x %d)\n", 932 subsystem_id, sku); 933 return true; 934 } 935 } 936 937 return false; 938 } 939 940 struct iwl_nvm_data * 941 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 942 const __be16 *nvm_hw, const __le16 *nvm_sw, 943 const __le16 *nvm_calib, const __le16 *regulatory, 944 const __le16 *mac_override, const __le16 *phy_sku, 945 u8 tx_chains, u8 rx_chains, bool lar_fw_supported) 946 { 947 struct iwl_nvm_data *data; 948 bool lar_enabled; 949 u32 sku, radio_cfg; 950 u32 sbands_flags = 0; 951 u16 lar_config; 952 const __le16 *ch_section; 953 954 if (cfg->uhb_supported) 955 data = kzalloc(struct_size(data, channels, 956 IWL_NVM_NUM_CHANNELS_UHB), 957 GFP_KERNEL); 958 else if (cfg->nvm_type != IWL_NVM_EXT) 959 data = kzalloc(struct_size(data, channels, 960 IWL_NVM_NUM_CHANNELS), 961 GFP_KERNEL); 962 else 963 data = kzalloc(struct_size(data, channels, 964 IWL_NVM_NUM_CHANNELS_EXT), 965 GFP_KERNEL); 966 if (!data) 967 return NULL; 968 969 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 970 971 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 972 iwl_set_radio_cfg(cfg, data, radio_cfg); 973 if (data->valid_tx_ant) 974 tx_chains &= data->valid_tx_ant; 975 if (data->valid_rx_ant) 976 rx_chains &= data->valid_rx_ant; 977 978 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 979 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 980 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 981 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 982 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 983 data->sku_cap_11n_enable = false; 984 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 985 (sku & NVM_SKU_CAP_11AC_ENABLE); 986 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 987 988 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 989 990 if (cfg->nvm_type != IWL_NVM_EXT) { 991 /* Checking for required sections */ 992 if (!nvm_calib) { 993 IWL_ERR(trans, 994 "Can't parse empty Calib NVM sections\n"); 995 kfree(data); 996 return NULL; 997 } 998 999 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1000 ®ulatory[NVM_CHANNELS_SDP] : 1001 &nvm_sw[NVM_CHANNELS]; 1002 1003 /* in family 8000 Xtal calibration values moved to OTP */ 1004 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 1005 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 1006 lar_enabled = true; 1007 } else { 1008 u16 lar_offset = data->nvm_version < 0xE39 ? 1009 NVM_LAR_OFFSET_OLD : 1010 NVM_LAR_OFFSET; 1011 1012 lar_config = le16_to_cpup(regulatory + lar_offset); 1013 data->lar_enabled = !!(lar_config & 1014 NVM_LAR_ENABLED); 1015 lar_enabled = data->lar_enabled; 1016 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1017 } 1018 1019 /* If no valid mac address was found - bail out */ 1020 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1021 kfree(data); 1022 return NULL; 1023 } 1024 1025 if (lar_fw_supported && lar_enabled) 1026 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1027 1028 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1029 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1030 1031 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1032 sbands_flags, false); 1033 data->calib_version = 255; 1034 1035 return data; 1036 } 1037 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1038 1039 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1040 int ch_idx, u16 nvm_flags, 1041 const struct iwl_cfg *cfg) 1042 { 1043 u32 flags = NL80211_RRF_NO_HT40; 1044 1045 if (ch_idx < NUM_2GHZ_CHANNELS && 1046 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1047 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1048 flags &= ~NL80211_RRF_NO_HT40PLUS; 1049 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1050 flags &= ~NL80211_RRF_NO_HT40MINUS; 1051 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1052 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1053 flags &= ~NL80211_RRF_NO_HT40PLUS; 1054 else 1055 flags &= ~NL80211_RRF_NO_HT40MINUS; 1056 } 1057 1058 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1059 flags |= NL80211_RRF_NO_80MHZ; 1060 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1061 flags |= NL80211_RRF_NO_160MHZ; 1062 1063 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1064 flags |= NL80211_RRF_NO_IR; 1065 1066 if (nvm_flags & NVM_CHANNEL_RADAR) 1067 flags |= NL80211_RRF_DFS; 1068 1069 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1070 flags |= NL80211_RRF_NO_OUTDOOR; 1071 1072 /* Set the GO concurrent flag only in case that NO_IR is set. 1073 * Otherwise it is meaningless 1074 */ 1075 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1076 (flags & NL80211_RRF_NO_IR)) 1077 flags |= NL80211_RRF_GO_CONCURRENT; 1078 1079 return flags; 1080 } 1081 1082 struct ieee80211_regdomain * 1083 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1084 int num_of_ch, __le32 *channels, u16 fw_mcc, 1085 u16 geo_info) 1086 { 1087 int ch_idx; 1088 u16 ch_flags; 1089 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1090 const u16 *nvm_chan; 1091 struct ieee80211_regdomain *regd, *copy_rd; 1092 struct ieee80211_reg_rule *rule; 1093 enum nl80211_band band; 1094 int center_freq, prev_center_freq = 0; 1095 int valid_rules = 0; 1096 bool new_rule; 1097 int max_num_ch; 1098 1099 if (cfg->uhb_supported) { 1100 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1101 nvm_chan = iwl_uhb_nvm_channels; 1102 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1103 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1104 nvm_chan = iwl_ext_nvm_channels; 1105 } else { 1106 max_num_ch = IWL_NVM_NUM_CHANNELS; 1107 nvm_chan = iwl_nvm_channels; 1108 } 1109 1110 if (WARN_ON(num_of_ch > max_num_ch)) 1111 num_of_ch = max_num_ch; 1112 1113 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1114 return ERR_PTR(-EINVAL); 1115 1116 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1117 num_of_ch); 1118 1119 /* build a regdomain rule for every valid channel */ 1120 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1121 if (!regd) 1122 return ERR_PTR(-ENOMEM); 1123 1124 /* set alpha2 from FW. */ 1125 regd->alpha2[0] = fw_mcc >> 8; 1126 regd->alpha2[1] = fw_mcc & 0xff; 1127 1128 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1129 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1130 band = (ch_idx < NUM_2GHZ_CHANNELS) ? 1131 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1132 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1133 band); 1134 new_rule = false; 1135 1136 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1137 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1138 nvm_chan[ch_idx], ch_flags); 1139 continue; 1140 } 1141 1142 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1143 ch_flags, cfg); 1144 1145 /* we can't continue the same rule */ 1146 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1147 center_freq - prev_center_freq > 20) { 1148 valid_rules++; 1149 new_rule = true; 1150 } 1151 1152 rule = ®d->reg_rules[valid_rules - 1]; 1153 1154 if (new_rule) 1155 rule->freq_range.start_freq_khz = 1156 MHZ_TO_KHZ(center_freq - 10); 1157 1158 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1159 1160 /* this doesn't matter - not used by FW */ 1161 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1162 rule->power_rule.max_eirp = 1163 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1164 1165 rule->flags = reg_rule_flags; 1166 1167 /* rely on auto-calculation to merge BW of contiguous chans */ 1168 rule->flags |= NL80211_RRF_AUTO_BW; 1169 rule->freq_range.max_bandwidth_khz = 0; 1170 1171 prev_center_freq = center_freq; 1172 prev_reg_rule_flags = reg_rule_flags; 1173 1174 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1175 nvm_chan[ch_idx], ch_flags); 1176 1177 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1178 band == NL80211_BAND_2GHZ) 1179 continue; 1180 1181 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1182 } 1183 1184 regd->n_reg_rules = valid_rules; 1185 1186 /* 1187 * Narrow down regdom for unused regulatory rules to prevent hole 1188 * between reg rules to wmm rules. 1189 */ 1190 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1191 GFP_KERNEL); 1192 if (!copy_rd) 1193 copy_rd = ERR_PTR(-ENOMEM); 1194 1195 kfree(regd); 1196 return copy_rd; 1197 } 1198 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1199 1200 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1201 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1202 #define MAX_NVM_FILE_LEN 16384 1203 1204 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1205 unsigned int len) 1206 { 1207 #define IWL_4165_DEVICE_ID 0x5501 1208 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1209 1210 if (section == NVM_SECTION_TYPE_PHY_SKU && 1211 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1212 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1213 /* OTP 0x52 bug work around: it's a 1x1 device */ 1214 data[3] = ANT_B | (ANT_B << 4); 1215 } 1216 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1217 1218 /* 1219 * Reads external NVM from a file into mvm->nvm_sections 1220 * 1221 * HOW TO CREATE THE NVM FILE FORMAT: 1222 * ------------------------------ 1223 * 1. create hex file, format: 1224 * 3800 -> header 1225 * 0000 -> header 1226 * 5a40 -> data 1227 * 1228 * rev - 6 bit (word1) 1229 * len - 10 bit (word1) 1230 * id - 4 bit (word2) 1231 * rsv - 12 bit (word2) 1232 * 1233 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1234 * 1235 * 3. create binary file from the hex file 1236 * 1237 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1238 */ 1239 int iwl_read_external_nvm(struct iwl_trans *trans, 1240 const char *nvm_file_name, 1241 struct iwl_nvm_section *nvm_sections) 1242 { 1243 int ret, section_size; 1244 u16 section_id; 1245 const struct firmware *fw_entry; 1246 const struct { 1247 __le16 word1; 1248 __le16 word2; 1249 u8 data[]; 1250 } *file_sec; 1251 const u8 *eof; 1252 u8 *temp; 1253 int max_section_size; 1254 const __le32 *dword_buff; 1255 1256 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1257 #define NVM_WORD2_ID(x) (x >> 12) 1258 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1259 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1260 #define NVM_HEADER_0 (0x2A504C54) 1261 #define NVM_HEADER_1 (0x4E564D2A) 1262 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1263 1264 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1265 1266 /* Maximal size depends on NVM version */ 1267 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1268 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1269 else 1270 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1271 1272 /* 1273 * Obtain NVM image via request_firmware. Since we already used 1274 * request_firmware_nowait() for the firmware binary load and only 1275 * get here after that we assume the NVM request can be satisfied 1276 * synchronously. 1277 */ 1278 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1279 if (ret) { 1280 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1281 nvm_file_name, ret); 1282 return ret; 1283 } 1284 1285 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1286 nvm_file_name, fw_entry->size); 1287 1288 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1289 IWL_ERR(trans, "NVM file too large\n"); 1290 ret = -EINVAL; 1291 goto out; 1292 } 1293 1294 eof = fw_entry->data + fw_entry->size; 1295 dword_buff = (__le32 *)fw_entry->data; 1296 1297 /* some NVM file will contain a header. 1298 * The header is identified by 2 dwords header as follow: 1299 * dword[0] = 0x2A504C54 1300 * dword[1] = 0x4E564D2A 1301 * 1302 * This header must be skipped when providing the NVM data to the FW. 1303 */ 1304 if (fw_entry->size > NVM_HEADER_SIZE && 1305 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1306 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1307 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1308 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1309 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1310 le32_to_cpu(dword_buff[3])); 1311 1312 /* nvm file validation, dword_buff[2] holds the file version */ 1313 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1314 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP && 1315 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1316 ret = -EFAULT; 1317 goto out; 1318 } 1319 } else { 1320 file_sec = (void *)fw_entry->data; 1321 } 1322 1323 while (true) { 1324 if (file_sec->data > eof) { 1325 IWL_ERR(trans, 1326 "ERROR - NVM file too short for section header\n"); 1327 ret = -EINVAL; 1328 break; 1329 } 1330 1331 /* check for EOF marker */ 1332 if (!file_sec->word1 && !file_sec->word2) { 1333 ret = 0; 1334 break; 1335 } 1336 1337 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1338 section_size = 1339 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1340 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1341 } else { 1342 section_size = 2 * EXT_NVM_WORD2_LEN( 1343 le16_to_cpu(file_sec->word2)); 1344 section_id = EXT_NVM_WORD1_ID( 1345 le16_to_cpu(file_sec->word1)); 1346 } 1347 1348 if (section_size > max_section_size) { 1349 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1350 section_size); 1351 ret = -EINVAL; 1352 break; 1353 } 1354 1355 if (!section_size) { 1356 IWL_ERR(trans, "ERROR - section empty\n"); 1357 ret = -EINVAL; 1358 break; 1359 } 1360 1361 if (file_sec->data + section_size > eof) { 1362 IWL_ERR(trans, 1363 "ERROR - NVM file too short for section (%d bytes)\n", 1364 section_size); 1365 ret = -EINVAL; 1366 break; 1367 } 1368 1369 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1370 "Invalid NVM section ID %d\n", section_id)) { 1371 ret = -EINVAL; 1372 break; 1373 } 1374 1375 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1376 if (!temp) { 1377 ret = -ENOMEM; 1378 break; 1379 } 1380 1381 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1382 1383 kfree(nvm_sections[section_id].data); 1384 nvm_sections[section_id].data = temp; 1385 nvm_sections[section_id].length = section_size; 1386 1387 /* advance to the next section */ 1388 file_sec = (void *)(file_sec->data + section_size); 1389 } 1390 out: 1391 release_firmware(fw_entry); 1392 return ret; 1393 } 1394 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1395 1396 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1397 const struct iwl_fw *fw) 1398 { 1399 struct iwl_nvm_get_info cmd = {}; 1400 struct iwl_nvm_data *nvm; 1401 struct iwl_host_cmd hcmd = { 1402 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1403 .data = { &cmd, }, 1404 .len = { sizeof(cmd) }, 1405 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1406 }; 1407 int ret; 1408 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable && 1409 fw_has_capa(&fw->ucode_capa, 1410 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 1411 bool empty_otp; 1412 u32 mac_flags; 1413 u32 sbands_flags = 0; 1414 /* 1415 * All the values in iwl_nvm_get_info_rsp v4 are the same as 1416 * in v3, except for the channel profile part of the 1417 * regulatory. So we can just access the new struct, with the 1418 * exception of the latter. 1419 */ 1420 struct iwl_nvm_get_info_rsp *rsp; 1421 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 1422 bool v4 = fw_has_api(&fw->ucode_capa, 1423 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 1424 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 1425 void *channel_profile; 1426 1427 ret = iwl_trans_send_cmd(trans, &hcmd); 1428 if (ret) 1429 return ERR_PTR(ret); 1430 1431 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 1432 "Invalid payload len in NVM response from FW %d", 1433 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1434 ret = -EINVAL; 1435 goto out; 1436 } 1437 1438 rsp = (void *)hcmd.resp_pkt->data; 1439 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1440 NVM_GENERAL_FLAGS_EMPTY_OTP); 1441 if (empty_otp) 1442 IWL_INFO(trans, "OTP is empty\n"); 1443 1444 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 1445 if (!nvm) { 1446 ret = -ENOMEM; 1447 goto out; 1448 } 1449 1450 iwl_set_hw_address_from_csr(trans, nvm); 1451 /* TODO: if platform NVM has MAC address - override it here */ 1452 1453 if (!is_valid_ether_addr(nvm->hw_addr)) { 1454 IWL_ERR(trans, "no valid mac address was found\n"); 1455 ret = -EINVAL; 1456 goto err_free; 1457 } 1458 1459 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1460 1461 /* Initialize general data */ 1462 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1463 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1464 if (nvm->n_hw_addrs == 0) 1465 IWL_WARN(trans, 1466 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1467 empty_otp); 1468 1469 /* Initialize MAC sku data */ 1470 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1471 nvm->sku_cap_11ac_enable = 1472 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1473 nvm->sku_cap_11n_enable = 1474 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1475 nvm->sku_cap_11ax_enable = 1476 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1477 nvm->sku_cap_band_24ghz_enable = 1478 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1479 nvm->sku_cap_band_52ghz_enable = 1480 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1481 nvm->sku_cap_mimo_disabled = 1482 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1483 1484 /* Initialize PHY sku data */ 1485 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1486 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1487 1488 if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) { 1489 nvm->lar_enabled = true; 1490 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1491 } 1492 1493 rsp_v3 = (void *)rsp; 1494 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 1495 (void *)rsp_v3->regulatory.channel_profile; 1496 1497 iwl_init_sbands(trans, nvm, 1498 channel_profile, 1499 nvm->valid_tx_ant & fw->valid_tx_ant, 1500 nvm->valid_rx_ant & fw->valid_rx_ant, 1501 sbands_flags, v4); 1502 1503 iwl_free_resp(&hcmd); 1504 return nvm; 1505 1506 err_free: 1507 kfree(nvm); 1508 out: 1509 iwl_free_resp(&hcmd); 1510 return ERR_PTR(ret); 1511 } 1512 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1513