1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/types.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/etherdevice.h> 11 #include <linux/pci.h> 12 #include <linux/firmware.h> 13 14 #include "iwl-drv.h" 15 #include "iwl-modparams.h" 16 #include "iwl-nvm-parse.h" 17 #include "iwl-prph.h" 18 #include "iwl-io.h" 19 #include "iwl-csr.h" 20 #include "fw/acpi.h" 21 #include "fw/api/nvm-reg.h" 22 #include "fw/api/commands.h" 23 #include "fw/api/cmdhdr.h" 24 #include "fw/img.h" 25 #include "mei/iwl-mei.h" 26 27 /* NVM offsets (in words) definitions */ 28 enum nvm_offsets { 29 /* NVM HW-Section offset (in words) definitions */ 30 SUBSYSTEM_ID = 0x0A, 31 HW_ADDR = 0x15, 32 33 /* NVM SW-Section offset (in words) definitions */ 34 NVM_SW_SECTION = 0x1C0, 35 NVM_VERSION = 0, 36 RADIO_CFG = 1, 37 SKU = 2, 38 N_HW_ADDRS = 3, 39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 40 41 /* NVM calibration section offset (in words) definitions */ 42 NVM_CALIB_SECTION = 0x2B8, 43 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 44 45 /* NVM REGULATORY -Section offset (in words) definitions */ 46 NVM_CHANNELS_SDP = 0, 47 }; 48 49 enum ext_nvm_offsets { 50 /* NVM HW-Section offset (in words) definitions */ 51 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 52 53 /* NVM SW-Section offset (in words) definitions */ 54 NVM_VERSION_EXT_NVM = 0, 55 N_HW_ADDRS_FAMILY_8000 = 3, 56 57 /* NVM PHY_SKU-Section offset (in words) definitions */ 58 RADIO_CFG_FAMILY_EXT_NVM = 0, 59 SKU_FAMILY_8000 = 2, 60 61 /* NVM REGULATORY -Section offset (in words) definitions */ 62 NVM_CHANNELS_EXTENDED = 0, 63 NVM_LAR_OFFSET_OLD = 0x4C7, 64 NVM_LAR_OFFSET = 0x507, 65 NVM_LAR_ENABLED = 0x7, 66 }; 67 68 /* SKU Capabilities (actual values from NVM definition) */ 69 enum nvm_sku_bits { 70 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 71 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 72 NVM_SKU_CAP_11N_ENABLE = BIT(2), 73 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 74 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 75 }; 76 77 /* 78 * These are the channel numbers in the order that they are stored in the NVM 79 */ 80 static const u16 iwl_nvm_channels[] = { 81 /* 2.4 GHz */ 82 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 83 /* 5 GHz */ 84 36, 40, 44 , 48, 52, 56, 60, 64, 85 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 86 149, 153, 157, 161, 165 87 }; 88 89 static const u16 iwl_ext_nvm_channels[] = { 90 /* 2.4 GHz */ 91 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 92 /* 5 GHz */ 93 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 94 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 95 149, 153, 157, 161, 165, 169, 173, 177, 181 96 }; 97 98 static const u16 iwl_uhb_nvm_channels[] = { 99 /* 2.4 GHz */ 100 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 101 /* 5 GHz */ 102 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 103 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 104 149, 153, 157, 161, 165, 169, 173, 177, 181, 105 /* 6-7 GHz */ 106 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 107 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 108 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 109 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 110 }; 111 112 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 113 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 114 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 115 #define NUM_2GHZ_CHANNELS 14 116 #define NUM_5GHZ_CHANNELS 37 117 #define FIRST_2GHZ_HT_MINUS 5 118 #define LAST_2GHZ_HT_PLUS 9 119 #define N_HW_ADDR_MASK 0xF 120 121 /* rate data (static) */ 122 static struct ieee80211_rate iwl_cfg80211_rates[] = { 123 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 124 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 125 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 126 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 127 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 128 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 130 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 131 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 132 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 133 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 134 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 135 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 136 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 137 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 138 }; 139 #define RATES_24_OFFS 0 140 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 141 #define RATES_52_OFFS 4 142 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 143 144 /** 145 * enum iwl_nvm_channel_flags - channel flags in NVM 146 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 147 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 148 * @NVM_CHANNEL_ACTIVE: active scanning allowed 149 * @NVM_CHANNEL_RADAR: radar detection required 150 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 151 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 152 * on same channel on 2.4 or same UNII band on 5.2 153 * @NVM_CHANNEL_UNIFORM: uniform spreading required 154 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 155 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 156 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 157 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 158 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 159 */ 160 enum iwl_nvm_channel_flags { 161 NVM_CHANNEL_VALID = BIT(0), 162 NVM_CHANNEL_IBSS = BIT(1), 163 NVM_CHANNEL_ACTIVE = BIT(3), 164 NVM_CHANNEL_RADAR = BIT(4), 165 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 166 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 167 NVM_CHANNEL_UNIFORM = BIT(7), 168 NVM_CHANNEL_20MHZ = BIT(8), 169 NVM_CHANNEL_40MHZ = BIT(9), 170 NVM_CHANNEL_80MHZ = BIT(10), 171 NVM_CHANNEL_160MHZ = BIT(11), 172 NVM_CHANNEL_DC_HIGH = BIT(12), 173 }; 174 175 /** 176 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory 177 * domain. 178 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 179 * 2.4Ghz band is allowed. 180 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 181 * 5Ghz band is allowed. 182 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 183 * for this regulatory domain (valid only in 5Ghz). 184 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 185 * for this regulatory domain (valid only in 5Ghz). 186 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 187 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 188 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden 189 * for this regulatory domain (valid only in 5Ghz). 190 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed. 191 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 192 */ 193 enum iwl_reg_capa_flags { 194 REG_CAPA_BF_CCD_LOW_BAND = BIT(0), 195 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1), 196 REG_CAPA_160MHZ_ALLOWED = BIT(2), 197 REG_CAPA_80MHZ_ALLOWED = BIT(3), 198 REG_CAPA_MCS_8_ALLOWED = BIT(4), 199 REG_CAPA_MCS_9_ALLOWED = BIT(5), 200 REG_CAPA_40MHZ_FORBIDDEN = BIT(7), 201 REG_CAPA_DC_HIGH_ENABLED = BIT(9), 202 REG_CAPA_11AX_DISABLED = BIT(10), 203 }; 204 205 /** 206 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory 207 * domain (version 2). 208 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are 209 * disabled. 210 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 211 * 2.4Ghz band is allowed. 212 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 213 * 5Ghz band is allowed. 214 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 215 * for this regulatory domain (valid only in 5Ghz). 216 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 217 * for this regulatory domain (valid only in 5Ghz). 218 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 219 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 220 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118, 221 * 126, 122) are disabled. 222 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed 223 * for this regulatory domain (uvalid only in 5Ghz). 224 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 225 */ 226 enum iwl_reg_capa_flags_v2 { 227 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0), 228 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1), 229 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2), 230 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3), 231 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4), 232 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5), 233 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6), 234 REG_CAPA_V2_WEATHER_DISABLED = BIT(7), 235 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8), 236 REG_CAPA_V2_11AX_DISABLED = BIT(10), 237 }; 238 239 /* 240 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the 241 * MCC update command response. 242 */ 243 #define REG_CAPA_V2_RESP_VER 6 244 245 /** 246 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for 247 * handling the different APIs of reg_capa_flags. 248 * 249 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed 250 * for this regulatory domain (valid only in 5Ghz). 251 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed 252 * for this regulatory domain (valid only in 5Ghz). 253 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed 254 * for this regulatory domain (valid only in 5Ghz). 255 * @disable_11ax: 11ax is forbidden for this regulatory domain. 256 */ 257 struct iwl_reg_capa { 258 u16 allow_40mhz; 259 u16 allow_80mhz; 260 u16 allow_160mhz; 261 u16 disable_11ax; 262 }; 263 264 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 265 int chan, u32 flags) 266 { 267 #define CHECK_AND_PRINT_I(x) \ 268 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 269 270 if (!(flags & NVM_CHANNEL_VALID)) { 271 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 272 chan, flags); 273 return; 274 } 275 276 /* Note: already can print up to 101 characters, 110 is the limit! */ 277 IWL_DEBUG_DEV(dev, level, 278 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 279 chan, flags, 280 CHECK_AND_PRINT_I(VALID), 281 CHECK_AND_PRINT_I(IBSS), 282 CHECK_AND_PRINT_I(ACTIVE), 283 CHECK_AND_PRINT_I(RADAR), 284 CHECK_AND_PRINT_I(INDOOR_ONLY), 285 CHECK_AND_PRINT_I(GO_CONCURRENT), 286 CHECK_AND_PRINT_I(UNIFORM), 287 CHECK_AND_PRINT_I(20MHZ), 288 CHECK_AND_PRINT_I(40MHZ), 289 CHECK_AND_PRINT_I(80MHZ), 290 CHECK_AND_PRINT_I(160MHZ), 291 CHECK_AND_PRINT_I(DC_HIGH)); 292 #undef CHECK_AND_PRINT_I 293 } 294 295 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 296 u32 nvm_flags, const struct iwl_cfg *cfg) 297 { 298 u32 flags = IEEE80211_CHAN_NO_HT40; 299 300 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 301 if (ch_num <= LAST_2GHZ_HT_PLUS) 302 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 303 if (ch_num >= FIRST_2GHZ_HT_MINUS) 304 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 305 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 306 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 307 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 308 else 309 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 310 } 311 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 312 flags |= IEEE80211_CHAN_NO_80MHZ; 313 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 314 flags |= IEEE80211_CHAN_NO_160MHZ; 315 316 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 317 flags |= IEEE80211_CHAN_NO_IR; 318 319 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 320 flags |= IEEE80211_CHAN_NO_IR; 321 322 if (nvm_flags & NVM_CHANNEL_RADAR) 323 flags |= IEEE80211_CHAN_RADAR; 324 325 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 326 flags |= IEEE80211_CHAN_INDOOR_ONLY; 327 328 /* Set the GO concurrent flag only in case that NO_IR is set. 329 * Otherwise it is meaningless 330 */ 331 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 332 (flags & IEEE80211_CHAN_NO_IR)) 333 flags |= IEEE80211_CHAN_IR_CONCURRENT; 334 335 return flags; 336 } 337 338 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 339 { 340 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) { 341 return NL80211_BAND_6GHZ; 342 } 343 344 if (ch_idx >= NUM_2GHZ_CHANNELS) 345 return NL80211_BAND_5GHZ; 346 return NL80211_BAND_2GHZ; 347 } 348 349 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 350 struct iwl_nvm_data *data, 351 const void * const nvm_ch_flags, 352 u32 sbands_flags, bool v4) 353 { 354 int ch_idx; 355 int n_channels = 0; 356 struct ieee80211_channel *channel; 357 u32 ch_flags; 358 int num_of_ch; 359 const u16 *nvm_chan; 360 361 if (cfg->uhb_supported) { 362 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 363 nvm_chan = iwl_uhb_nvm_channels; 364 } else if (cfg->nvm_type == IWL_NVM_EXT) { 365 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 366 nvm_chan = iwl_ext_nvm_channels; 367 } else { 368 num_of_ch = IWL_NVM_NUM_CHANNELS; 369 nvm_chan = iwl_nvm_channels; 370 } 371 372 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 373 enum nl80211_band band = 374 iwl_nl80211_band_from_channel_idx(ch_idx); 375 376 if (v4) 377 ch_flags = 378 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx); 379 else 380 ch_flags = 381 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx); 382 383 if (band == NL80211_BAND_5GHZ && 384 !data->sku_cap_band_52ghz_enable) 385 continue; 386 387 /* workaround to disable wide channels in 5GHz */ 388 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 389 band == NL80211_BAND_5GHZ) { 390 ch_flags &= ~(NVM_CHANNEL_40MHZ | 391 NVM_CHANNEL_80MHZ | 392 NVM_CHANNEL_160MHZ); 393 } 394 395 if (ch_flags & NVM_CHANNEL_160MHZ) 396 data->vht160_supported = true; 397 398 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 399 !(ch_flags & NVM_CHANNEL_VALID)) { 400 /* 401 * Channels might become valid later if lar is 402 * supported, hence we still want to add them to 403 * the list of supported channels to cfg80211. 404 */ 405 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 406 nvm_chan[ch_idx], ch_flags); 407 continue; 408 } 409 410 channel = &data->channels[n_channels]; 411 n_channels++; 412 413 channel->hw_value = nvm_chan[ch_idx]; 414 channel->band = band; 415 channel->center_freq = 416 ieee80211_channel_to_frequency( 417 channel->hw_value, channel->band); 418 419 /* Initialize regulatory-based run-time data */ 420 421 /* 422 * Default value - highest tx power value. max_power 423 * is not used in mvm, and is used for backwards compatibility 424 */ 425 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 426 427 /* don't put limitations in case we're using LAR */ 428 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 429 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 430 ch_idx, band, 431 ch_flags, cfg); 432 else 433 channel->flags = 0; 434 435 /* TODO: Don't put limitations on UHB devices as we still don't 436 * have NVM for them 437 */ 438 if (cfg->uhb_supported) 439 channel->flags = 0; 440 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 441 channel->hw_value, ch_flags); 442 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 443 channel->hw_value, channel->max_power); 444 } 445 446 return n_channels; 447 } 448 449 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 450 struct iwl_nvm_data *data, 451 struct ieee80211_sta_vht_cap *vht_cap, 452 u8 tx_chains, u8 rx_chains) 453 { 454 const struct iwl_cfg *cfg = trans->cfg; 455 int num_rx_ants = num_of_ant(rx_chains); 456 int num_tx_ants = num_of_ant(tx_chains); 457 458 vht_cap->vht_supported = true; 459 460 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 461 IEEE80211_VHT_CAP_RXSTBC_1 | 462 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 463 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 464 IEEE80211_VHT_MAX_AMPDU_1024K << 465 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 466 467 if (data->vht160_supported) 468 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 469 IEEE80211_VHT_CAP_SHORT_GI_160; 470 471 if (cfg->vht_mu_mimo_supported) 472 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 473 474 if (cfg->ht_params->ldpc) 475 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 476 477 if (data->sku_cap_mimo_disabled) { 478 num_rx_ants = 1; 479 num_tx_ants = 1; 480 } 481 482 if (num_tx_ants > 1) 483 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 484 else 485 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 486 487 switch (iwlwifi_mod_params.amsdu_size) { 488 case IWL_AMSDU_DEF: 489 if (trans->trans_cfg->mq_rx_supported) 490 vht_cap->cap |= 491 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 492 else 493 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 494 break; 495 case IWL_AMSDU_2K: 496 if (trans->trans_cfg->mq_rx_supported) 497 vht_cap->cap |= 498 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 499 else 500 WARN(1, "RB size of 2K is not supported by this device\n"); 501 break; 502 case IWL_AMSDU_4K: 503 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 504 break; 505 case IWL_AMSDU_8K: 506 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 507 break; 508 case IWL_AMSDU_12K: 509 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 510 break; 511 default: 512 break; 513 } 514 515 vht_cap->vht_mcs.rx_mcs_map = 516 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 517 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 520 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 523 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 524 525 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 526 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 527 /* this works because NOT_SUPPORTED == 3 */ 528 vht_cap->vht_mcs.rx_mcs_map |= 529 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 530 } 531 532 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 533 534 vht_cap->vht_mcs.tx_highest |= 535 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 536 } 537 538 static const u8 iwl_vendor_caps[] = { 539 0xdd, /* vendor element */ 540 0x06, /* length */ 541 0x00, 0x17, 0x35, /* Intel OUI */ 542 0x08, /* type (Intel Capabilities) */ 543 /* followed by 16 bits of capabilities */ 544 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0) 545 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE, 546 0x00 547 }; 548 549 static const struct ieee80211_sband_iftype_data iwl_he_capa[] = { 550 { 551 .types_mask = BIT(NL80211_IFTYPE_STATION), 552 .he_cap = { 553 .has_he = true, 554 .he_cap_elem = { 555 .mac_cap_info[0] = 556 IEEE80211_HE_MAC_CAP0_HTC_HE | 557 IEEE80211_HE_MAC_CAP0_TWT_REQ, 558 .mac_cap_info[1] = 559 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 560 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 561 .mac_cap_info[2] = 562 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP, 563 .mac_cap_info[3] = 564 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 565 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS, 566 .mac_cap_info[4] = 567 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU | 568 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 569 .mac_cap_info[5] = 570 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 571 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 572 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 573 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 574 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 575 .phy_cap_info[0] = 576 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 577 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 578 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 579 .phy_cap_info[1] = 580 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 581 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 582 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 583 .phy_cap_info[2] = 584 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 585 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 586 .phy_cap_info[3] = 587 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 588 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 589 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 590 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 591 .phy_cap_info[4] = 592 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 593 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 594 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 595 .phy_cap_info[6] = 596 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 597 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB | 598 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 599 .phy_cap_info[7] = 600 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 601 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 602 .phy_cap_info[8] = 603 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 604 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 605 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 606 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 607 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 608 .phy_cap_info[9] = 609 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 610 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 611 (IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED << 612 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS), 613 .phy_cap_info[10] = 614 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF, 615 }, 616 /* 617 * Set default Tx/Rx HE MCS NSS Support field. 618 * Indicate support for up to 2 spatial streams and all 619 * MCS, without any special cases 620 */ 621 .he_mcs_nss_supp = { 622 .rx_mcs_80 = cpu_to_le16(0xfffa), 623 .tx_mcs_80 = cpu_to_le16(0xfffa), 624 .rx_mcs_160 = cpu_to_le16(0xfffa), 625 .tx_mcs_160 = cpu_to_le16(0xfffa), 626 .rx_mcs_80p80 = cpu_to_le16(0xffff), 627 .tx_mcs_80p80 = cpu_to_le16(0xffff), 628 }, 629 /* 630 * Set default PPE thresholds, with PPET16 set to 0, 631 * PPET8 set to 7 632 */ 633 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 634 }, 635 }, 636 { 637 .types_mask = BIT(NL80211_IFTYPE_AP), 638 .he_cap = { 639 .has_he = true, 640 .he_cap_elem = { 641 .mac_cap_info[0] = 642 IEEE80211_HE_MAC_CAP0_HTC_HE, 643 .mac_cap_info[1] = 644 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 645 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 646 .mac_cap_info[3] = 647 IEEE80211_HE_MAC_CAP3_OMI_CONTROL, 648 .phy_cap_info[0] = 649 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 650 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G, 651 .phy_cap_info[1] = 652 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 653 .phy_cap_info[2] = 654 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 655 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 656 .phy_cap_info[3] = 657 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 658 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 659 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 660 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 661 .phy_cap_info[6] = 662 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 663 .phy_cap_info[7] = 664 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 665 .phy_cap_info[8] = 666 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 667 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 668 .phy_cap_info[9] = 669 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED 670 << IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS, 671 }, 672 /* 673 * Set default Tx/Rx HE MCS NSS Support field. 674 * Indicate support for up to 2 spatial streams and all 675 * MCS, without any special cases 676 */ 677 .he_mcs_nss_supp = { 678 .rx_mcs_80 = cpu_to_le16(0xfffa), 679 .tx_mcs_80 = cpu_to_le16(0xfffa), 680 .rx_mcs_160 = cpu_to_le16(0xfffa), 681 .tx_mcs_160 = cpu_to_le16(0xfffa), 682 .rx_mcs_80p80 = cpu_to_le16(0xffff), 683 .tx_mcs_80p80 = cpu_to_le16(0xffff), 684 }, 685 /* 686 * Set default PPE thresholds, with PPET16 set to 0, 687 * PPET8 set to 7 688 */ 689 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 690 }, 691 }, 692 }; 693 694 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans, 695 struct iwl_nvm_data *data, 696 struct ieee80211_supported_band *sband, 697 u8 tx_chains, u8 rx_chains) 698 { 699 struct ieee80211_sta_ht_cap ht_cap; 700 struct ieee80211_sta_vht_cap vht_cap = {}; 701 struct ieee80211_sband_iftype_data *iftype_data; 702 u16 he_6ghz_capa = 0; 703 u32 exp; 704 int i; 705 706 if (sband->band != NL80211_BAND_6GHZ) 707 return; 708 709 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */ 710 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ, 711 tx_chains, rx_chains); 712 WARN_ON(!ht_cap.ht_supported); 713 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains); 714 WARN_ON(!vht_cap.vht_supported); 715 716 he_6ghz_capa |= 717 u16_encode_bits(ht_cap.ampdu_density, 718 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START); 719 exp = u32_get_bits(vht_cap.cap, 720 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK); 721 he_6ghz_capa |= 722 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP); 723 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK); 724 he_6ghz_capa |= 725 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 726 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */ 727 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN) 728 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS; 729 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN) 730 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 731 732 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa); 733 734 /* we know it's writable - we set it before ourselves */ 735 iftype_data = (void *)sband->iftype_data; 736 for (i = 0; i < sband->n_iftype_data; i++) 737 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa); 738 } 739 740 static void 741 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, 742 struct ieee80211_supported_band *sband, 743 struct ieee80211_sband_iftype_data *iftype_data, 744 u8 tx_chains, u8 rx_chains, 745 const struct iwl_fw *fw) 746 { 747 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP); 748 749 /* Advertise an A-MPDU exponent extension based on 750 * operating band 751 */ 752 if (sband->band != NL80211_BAND_2GHZ) 753 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 754 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1; 755 else 756 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 757 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 758 759 if (is_ap && iwlwifi_mod_params.nvm_file) 760 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 761 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 762 763 if ((tx_chains & rx_chains) == ANT_AB) { 764 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 765 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ; 766 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |= 767 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 768 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2; 769 if (!is_ap) 770 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 771 IEEE80211_HE_PHY_CAP7_MAX_NC_2; 772 } else if (!is_ap) { 773 /* If not 2x2, we need to indicate 1x1 in the 774 * Midamble RX Max NSTS - but not for AP mode 775 */ 776 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &= 777 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 778 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 779 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 780 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 781 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 782 } 783 784 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 785 case IWL_CFG_RF_TYPE_GF: 786 case IWL_CFG_RF_TYPE_MR: 787 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 788 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 789 if (!is_ap) 790 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 791 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 792 break; 793 } 794 795 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT)) 796 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |= 797 IEEE80211_HE_MAC_CAP2_BCAST_TWT; 798 799 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 800 !is_ap) { 801 iftype_data->vendor_elems.data = iwl_vendor_caps; 802 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps); 803 } 804 } 805 806 static void iwl_init_he_hw_capab(struct iwl_trans *trans, 807 struct iwl_nvm_data *data, 808 struct ieee80211_supported_band *sband, 809 u8 tx_chains, u8 rx_chains, 810 const struct iwl_fw *fw) 811 { 812 struct ieee80211_sband_iftype_data *iftype_data; 813 int i; 814 815 /* should only initialize once */ 816 if (WARN_ON(sband->iftype_data)) 817 return; 818 819 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_capa)); 820 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_capa)); 821 822 switch (sband->band) { 823 case NL80211_BAND_2GHZ: 824 iftype_data = data->iftd.low; 825 break; 826 case NL80211_BAND_5GHZ: 827 case NL80211_BAND_6GHZ: 828 iftype_data = data->iftd.high; 829 break; 830 default: 831 WARN_ON(1); 832 return; 833 } 834 835 memcpy(iftype_data, iwl_he_capa, sizeof(iwl_he_capa)); 836 837 sband->iftype_data = iftype_data; 838 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa); 839 840 for (i = 0; i < sband->n_iftype_data; i++) 841 iwl_nvm_fixup_sband_iftd(trans, sband, &iftype_data[i], 842 tx_chains, rx_chains, fw); 843 844 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains); 845 } 846 847 static void iwl_init_sbands(struct iwl_trans *trans, 848 struct iwl_nvm_data *data, 849 const void *nvm_ch_flags, u8 tx_chains, 850 u8 rx_chains, u32 sbands_flags, bool v4, 851 const struct iwl_fw *fw) 852 { 853 struct device *dev = trans->dev; 854 const struct iwl_cfg *cfg = trans->cfg; 855 int n_channels; 856 int n_used = 0; 857 struct ieee80211_supported_band *sband; 858 859 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 860 sbands_flags, v4); 861 sband = &data->bands[NL80211_BAND_2GHZ]; 862 sband->band = NL80211_BAND_2GHZ; 863 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 864 sband->n_bitrates = N_RATES_24; 865 n_used += iwl_init_sband_channels(data, sband, n_channels, 866 NL80211_BAND_2GHZ); 867 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 868 tx_chains, rx_chains); 869 870 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 871 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 872 fw); 873 874 sband = &data->bands[NL80211_BAND_5GHZ]; 875 sband->band = NL80211_BAND_5GHZ; 876 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 877 sband->n_bitrates = N_RATES_52; 878 n_used += iwl_init_sband_channels(data, sband, n_channels, 879 NL80211_BAND_5GHZ); 880 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 881 tx_chains, rx_chains); 882 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 883 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 884 tx_chains, rx_chains); 885 886 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 887 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 888 fw); 889 890 /* 6GHz band. */ 891 sband = &data->bands[NL80211_BAND_6GHZ]; 892 sband->band = NL80211_BAND_6GHZ; 893 /* use the same rates as 5GHz band */ 894 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 895 sband->n_bitrates = N_RATES_52; 896 n_used += iwl_init_sband_channels(data, sband, n_channels, 897 NL80211_BAND_6GHZ); 898 899 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 900 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 901 fw); 902 else 903 sband->n_channels = 0; 904 if (n_channels != n_used) 905 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 906 n_used, n_channels); 907 } 908 909 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 910 const __le16 *phy_sku) 911 { 912 if (cfg->nvm_type != IWL_NVM_EXT) 913 return le16_to_cpup(nvm_sw + SKU); 914 915 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 916 } 917 918 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 919 { 920 if (cfg->nvm_type != IWL_NVM_EXT) 921 return le16_to_cpup(nvm_sw + NVM_VERSION); 922 else 923 return le32_to_cpup((__le32 *)(nvm_sw + 924 NVM_VERSION_EXT_NVM)); 925 } 926 927 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 928 const __le16 *phy_sku) 929 { 930 if (cfg->nvm_type != IWL_NVM_EXT) 931 return le16_to_cpup(nvm_sw + RADIO_CFG); 932 933 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 934 935 } 936 937 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 938 { 939 int n_hw_addr; 940 941 if (cfg->nvm_type != IWL_NVM_EXT) 942 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 943 944 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 945 946 return n_hw_addr & N_HW_ADDR_MASK; 947 } 948 949 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 950 struct iwl_nvm_data *data, 951 u32 radio_cfg) 952 { 953 if (cfg->nvm_type != IWL_NVM_EXT) { 954 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 955 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 956 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 957 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 958 return; 959 } 960 961 /* set the radio configuration for family 8000 */ 962 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 963 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 964 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 965 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 966 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 967 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 968 } 969 970 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 971 { 972 const u8 *hw_addr; 973 974 hw_addr = (const u8 *)&mac_addr0; 975 dest[0] = hw_addr[3]; 976 dest[1] = hw_addr[2]; 977 dest[2] = hw_addr[1]; 978 dest[3] = hw_addr[0]; 979 980 hw_addr = (const u8 *)&mac_addr1; 981 dest[4] = hw_addr[1]; 982 dest[5] = hw_addr[0]; 983 } 984 985 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 986 struct iwl_nvm_data *data) 987 { 988 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, 989 CSR_MAC_ADDR0_STRAP(trans))); 990 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, 991 CSR_MAC_ADDR1_STRAP(trans))); 992 993 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 994 /* 995 * If the OEM fused a valid address, use it instead of the one in the 996 * OTP 997 */ 998 if (is_valid_ether_addr(data->hw_addr)) 999 return; 1000 1001 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); 1002 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); 1003 1004 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1005 } 1006 1007 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 1008 const struct iwl_cfg *cfg, 1009 struct iwl_nvm_data *data, 1010 const __le16 *mac_override, 1011 const __be16 *nvm_hw) 1012 { 1013 const u8 *hw_addr; 1014 1015 if (mac_override) { 1016 static const u8 reserved_mac[] = { 1017 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1018 }; 1019 1020 hw_addr = (const u8 *)(mac_override + 1021 MAC_ADDRESS_OVERRIDE_EXT_NVM); 1022 1023 /* 1024 * Store the MAC address from MAO section. 1025 * No byte swapping is required in MAO section 1026 */ 1027 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 1028 1029 /* 1030 * Force the use of the OTP MAC address in case of reserved MAC 1031 * address in the NVM, or if address is given but invalid. 1032 */ 1033 if (is_valid_ether_addr(data->hw_addr) && 1034 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 1035 return; 1036 1037 IWL_ERR(trans, 1038 "mac address from nvm override section is not valid\n"); 1039 } 1040 1041 if (nvm_hw) { 1042 /* read the mac address from WFMP registers */ 1043 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 1044 WFMP_MAC_ADDR_0)); 1045 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 1046 WFMP_MAC_ADDR_1)); 1047 1048 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1049 1050 return; 1051 } 1052 1053 IWL_ERR(trans, "mac address is not found\n"); 1054 } 1055 1056 static int iwl_set_hw_address(struct iwl_trans *trans, 1057 const struct iwl_cfg *cfg, 1058 struct iwl_nvm_data *data, const __be16 *nvm_hw, 1059 const __le16 *mac_override) 1060 { 1061 if (cfg->mac_addr_from_csr) { 1062 iwl_set_hw_address_from_csr(trans, data); 1063 } else if (cfg->nvm_type != IWL_NVM_EXT) { 1064 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 1065 1066 /* The byte order is little endian 16 bit, meaning 214365 */ 1067 data->hw_addr[0] = hw_addr[1]; 1068 data->hw_addr[1] = hw_addr[0]; 1069 data->hw_addr[2] = hw_addr[3]; 1070 data->hw_addr[3] = hw_addr[2]; 1071 data->hw_addr[4] = hw_addr[5]; 1072 data->hw_addr[5] = hw_addr[4]; 1073 } else { 1074 iwl_set_hw_address_family_8000(trans, cfg, data, 1075 mac_override, nvm_hw); 1076 } 1077 1078 if (!is_valid_ether_addr(data->hw_addr)) { 1079 IWL_ERR(trans, "no valid mac address was found\n"); 1080 return -EINVAL; 1081 } 1082 1083 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 1084 1085 return 0; 1086 } 1087 1088 static bool 1089 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1090 const __be16 *nvm_hw) 1091 { 1092 /* 1093 * Workaround a bug in Indonesia SKUs where the regulatory in 1094 * some 7000-family OTPs erroneously allow wide channels in 1095 * 5GHz. To check for Indonesia, we take the SKU value from 1096 * bits 1-4 in the subsystem ID and check if it is either 5 or 1097 * 9. In those cases, we need to force-disable wide channels 1098 * in 5GHz otherwise the FW will throw a sysassert when we try 1099 * to use them. 1100 */ 1101 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1102 /* 1103 * Unlike the other sections in the NVM, the hw 1104 * section uses big-endian. 1105 */ 1106 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 1107 u8 sku = (subsystem_id & 0x1e) >> 1; 1108 1109 if (sku == 5 || sku == 9) { 1110 IWL_DEBUG_EEPROM(trans->dev, 1111 "disabling wide channels in 5GHz (0x%0x %d)\n", 1112 subsystem_id, sku); 1113 return true; 1114 } 1115 } 1116 1117 return false; 1118 } 1119 1120 struct iwl_nvm_data * 1121 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1122 const struct iwl_mei_nvm *mei_nvm, 1123 const struct iwl_fw *fw) 1124 { 1125 struct iwl_nvm_data *data; 1126 u32 sbands_flags = 0; 1127 u8 rx_chains = fw->valid_rx_ant; 1128 u8 tx_chains = fw->valid_rx_ant; 1129 1130 if (cfg->uhb_supported) 1131 data = kzalloc(struct_size(data, channels, 1132 IWL_NVM_NUM_CHANNELS_UHB), 1133 GFP_KERNEL); 1134 else 1135 data = kzalloc(struct_size(data, channels, 1136 IWL_NVM_NUM_CHANNELS_EXT), 1137 GFP_KERNEL); 1138 if (!data) 1139 return NULL; 1140 1141 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) != 1142 IWL_NVM_NUM_CHANNELS_UHB); 1143 data->nvm_version = mei_nvm->nvm_version; 1144 1145 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg); 1146 if (data->valid_tx_ant) 1147 tx_chains &= data->valid_tx_ant; 1148 if (data->valid_rx_ant) 1149 rx_chains &= data->valid_rx_ant; 1150 1151 data->sku_cap_mimo_disabled = false; 1152 data->sku_cap_band_24ghz_enable = true; 1153 data->sku_cap_band_52ghz_enable = true; 1154 data->sku_cap_11n_enable = 1155 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL); 1156 data->sku_cap_11ac_enable = true; 1157 data->sku_cap_11ax_enable = 1158 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT; 1159 1160 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT; 1161 1162 data->n_hw_addrs = mei_nvm->n_hw_addrs; 1163 /* If no valid mac address was found - bail out */ 1164 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) { 1165 kfree(data); 1166 return NULL; 1167 } 1168 1169 if (data->lar_enabled && 1170 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1171 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1172 1173 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains, 1174 sbands_flags, true, fw); 1175 1176 return data; 1177 } 1178 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data); 1179 1180 struct iwl_nvm_data * 1181 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1182 const struct iwl_fw *fw, 1183 const __be16 *nvm_hw, const __le16 *nvm_sw, 1184 const __le16 *nvm_calib, const __le16 *regulatory, 1185 const __le16 *mac_override, const __le16 *phy_sku, 1186 u8 tx_chains, u8 rx_chains) 1187 { 1188 struct iwl_nvm_data *data; 1189 bool lar_enabled; 1190 u32 sku, radio_cfg; 1191 u32 sbands_flags = 0; 1192 u16 lar_config; 1193 const __le16 *ch_section; 1194 1195 if (cfg->uhb_supported) 1196 data = kzalloc(struct_size(data, channels, 1197 IWL_NVM_NUM_CHANNELS_UHB), 1198 GFP_KERNEL); 1199 else if (cfg->nvm_type != IWL_NVM_EXT) 1200 data = kzalloc(struct_size(data, channels, 1201 IWL_NVM_NUM_CHANNELS), 1202 GFP_KERNEL); 1203 else 1204 data = kzalloc(struct_size(data, channels, 1205 IWL_NVM_NUM_CHANNELS_EXT), 1206 GFP_KERNEL); 1207 if (!data) 1208 return NULL; 1209 1210 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 1211 1212 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 1213 iwl_set_radio_cfg(cfg, data, radio_cfg); 1214 if (data->valid_tx_ant) 1215 tx_chains &= data->valid_tx_ant; 1216 if (data->valid_rx_ant) 1217 rx_chains &= data->valid_rx_ant; 1218 1219 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 1220 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 1221 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 1222 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 1223 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1224 data->sku_cap_11n_enable = false; 1225 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 1226 (sku & NVM_SKU_CAP_11AC_ENABLE); 1227 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 1228 1229 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 1230 1231 if (cfg->nvm_type != IWL_NVM_EXT) { 1232 /* Checking for required sections */ 1233 if (!nvm_calib) { 1234 IWL_ERR(trans, 1235 "Can't parse empty Calib NVM sections\n"); 1236 kfree(data); 1237 return NULL; 1238 } 1239 1240 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1241 ®ulatory[NVM_CHANNELS_SDP] : 1242 &nvm_sw[NVM_CHANNELS]; 1243 1244 /* in family 8000 Xtal calibration values moved to OTP */ 1245 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 1246 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 1247 lar_enabled = true; 1248 } else { 1249 u16 lar_offset = data->nvm_version < 0xE39 ? 1250 NVM_LAR_OFFSET_OLD : 1251 NVM_LAR_OFFSET; 1252 1253 lar_config = le16_to_cpup(regulatory + lar_offset); 1254 data->lar_enabled = !!(lar_config & 1255 NVM_LAR_ENABLED); 1256 lar_enabled = data->lar_enabled; 1257 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1258 } 1259 1260 /* If no valid mac address was found - bail out */ 1261 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1262 kfree(data); 1263 return NULL; 1264 } 1265 1266 if (lar_enabled && 1267 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1268 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1269 1270 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1271 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1272 1273 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1274 sbands_flags, false, fw); 1275 data->calib_version = 255; 1276 1277 return data; 1278 } 1279 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1280 1281 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1282 int ch_idx, u16 nvm_flags, 1283 struct iwl_reg_capa reg_capa, 1284 const struct iwl_cfg *cfg) 1285 { 1286 u32 flags = NL80211_RRF_NO_HT40; 1287 1288 if (ch_idx < NUM_2GHZ_CHANNELS && 1289 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1290 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1291 flags &= ~NL80211_RRF_NO_HT40PLUS; 1292 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1293 flags &= ~NL80211_RRF_NO_HT40MINUS; 1294 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1295 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1296 flags &= ~NL80211_RRF_NO_HT40PLUS; 1297 else 1298 flags &= ~NL80211_RRF_NO_HT40MINUS; 1299 } 1300 1301 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1302 flags |= NL80211_RRF_NO_80MHZ; 1303 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1304 flags |= NL80211_RRF_NO_160MHZ; 1305 1306 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1307 flags |= NL80211_RRF_NO_IR; 1308 1309 if (nvm_flags & NVM_CHANNEL_RADAR) 1310 flags |= NL80211_RRF_DFS; 1311 1312 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1313 flags |= NL80211_RRF_NO_OUTDOOR; 1314 1315 /* Set the GO concurrent flag only in case that NO_IR is set. 1316 * Otherwise it is meaningless 1317 */ 1318 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1319 (flags & NL80211_RRF_NO_IR)) 1320 flags |= NL80211_RRF_GO_CONCURRENT; 1321 1322 /* 1323 * reg_capa is per regulatory domain so apply it for every channel 1324 */ 1325 if (ch_idx >= NUM_2GHZ_CHANNELS) { 1326 if (!reg_capa.allow_40mhz) 1327 flags |= NL80211_RRF_NO_HT40; 1328 1329 if (!reg_capa.allow_80mhz) 1330 flags |= NL80211_RRF_NO_80MHZ; 1331 1332 if (!reg_capa.allow_160mhz) 1333 flags |= NL80211_RRF_NO_160MHZ; 1334 } 1335 if (reg_capa.disable_11ax) 1336 flags |= NL80211_RRF_NO_HE; 1337 1338 return flags; 1339 } 1340 1341 static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver) 1342 { 1343 struct iwl_reg_capa reg_capa; 1344 1345 if (resp_ver >= REG_CAPA_V2_RESP_VER) { 1346 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED; 1347 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED; 1348 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED; 1349 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED; 1350 } else { 1351 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN); 1352 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED; 1353 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED; 1354 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED; 1355 } 1356 return reg_capa; 1357 } 1358 1359 struct ieee80211_regdomain * 1360 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1361 int num_of_ch, __le32 *channels, u16 fw_mcc, 1362 u16 geo_info, u16 cap, u8 resp_ver) 1363 { 1364 int ch_idx; 1365 u16 ch_flags; 1366 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1367 const u16 *nvm_chan; 1368 struct ieee80211_regdomain *regd, *copy_rd; 1369 struct ieee80211_reg_rule *rule; 1370 enum nl80211_band band; 1371 int center_freq, prev_center_freq = 0; 1372 int valid_rules = 0; 1373 bool new_rule; 1374 int max_num_ch; 1375 struct iwl_reg_capa reg_capa; 1376 1377 if (cfg->uhb_supported) { 1378 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1379 nvm_chan = iwl_uhb_nvm_channels; 1380 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1381 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1382 nvm_chan = iwl_ext_nvm_channels; 1383 } else { 1384 max_num_ch = IWL_NVM_NUM_CHANNELS; 1385 nvm_chan = iwl_nvm_channels; 1386 } 1387 1388 if (WARN_ON(num_of_ch > max_num_ch)) 1389 num_of_ch = max_num_ch; 1390 1391 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1392 return ERR_PTR(-EINVAL); 1393 1394 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1395 num_of_ch); 1396 1397 /* build a regdomain rule for every valid channel */ 1398 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1399 if (!regd) 1400 return ERR_PTR(-ENOMEM); 1401 1402 /* set alpha2 from FW. */ 1403 regd->alpha2[0] = fw_mcc >> 8; 1404 regd->alpha2[1] = fw_mcc & 0xff; 1405 1406 /* parse regulatory capability flags */ 1407 reg_capa = iwl_get_reg_capa(cap, resp_ver); 1408 1409 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1410 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1411 band = iwl_nl80211_band_from_channel_idx(ch_idx); 1412 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1413 band); 1414 new_rule = false; 1415 1416 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1417 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1418 nvm_chan[ch_idx], ch_flags); 1419 continue; 1420 } 1421 1422 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1423 ch_flags, reg_capa, 1424 cfg); 1425 1426 /* we can't continue the same rule */ 1427 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1428 center_freq - prev_center_freq > 20) { 1429 valid_rules++; 1430 new_rule = true; 1431 } 1432 1433 rule = ®d->reg_rules[valid_rules - 1]; 1434 1435 if (new_rule) 1436 rule->freq_range.start_freq_khz = 1437 MHZ_TO_KHZ(center_freq - 10); 1438 1439 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1440 1441 /* this doesn't matter - not used by FW */ 1442 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1443 rule->power_rule.max_eirp = 1444 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1445 1446 rule->flags = reg_rule_flags; 1447 1448 /* rely on auto-calculation to merge BW of contiguous chans */ 1449 rule->flags |= NL80211_RRF_AUTO_BW; 1450 rule->freq_range.max_bandwidth_khz = 0; 1451 1452 prev_center_freq = center_freq; 1453 prev_reg_rule_flags = reg_rule_flags; 1454 1455 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1456 nvm_chan[ch_idx], ch_flags); 1457 1458 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1459 band == NL80211_BAND_2GHZ) 1460 continue; 1461 1462 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1463 } 1464 1465 /* 1466 * Certain firmware versions might report no valid channels 1467 * if booted in RF-kill, i.e. not all calibrations etc. are 1468 * running. We'll get out of this situation later when the 1469 * rfkill is removed and we update the regdomain again, but 1470 * since cfg80211 doesn't accept an empty regdomain, add a 1471 * dummy (unusable) rule here in this case so we can init. 1472 */ 1473 if (!valid_rules) { 1474 valid_rules = 1; 1475 rule = ®d->reg_rules[valid_rules - 1]; 1476 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412); 1477 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413); 1478 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1); 1479 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1480 rule->power_rule.max_eirp = 1481 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1482 } 1483 1484 regd->n_reg_rules = valid_rules; 1485 1486 /* 1487 * Narrow down regdom for unused regulatory rules to prevent hole 1488 * between reg rules to wmm rules. 1489 */ 1490 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1491 GFP_KERNEL); 1492 if (!copy_rd) 1493 copy_rd = ERR_PTR(-ENOMEM); 1494 1495 kfree(regd); 1496 return copy_rd; 1497 } 1498 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1499 1500 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1501 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1502 #define MAX_NVM_FILE_LEN 16384 1503 1504 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1505 unsigned int len) 1506 { 1507 #define IWL_4165_DEVICE_ID 0x5501 1508 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1509 1510 if (section == NVM_SECTION_TYPE_PHY_SKU && 1511 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1512 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1513 /* OTP 0x52 bug work around: it's a 1x1 device */ 1514 data[3] = ANT_B | (ANT_B << 4); 1515 } 1516 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1517 1518 /* 1519 * Reads external NVM from a file into mvm->nvm_sections 1520 * 1521 * HOW TO CREATE THE NVM FILE FORMAT: 1522 * ------------------------------ 1523 * 1. create hex file, format: 1524 * 3800 -> header 1525 * 0000 -> header 1526 * 5a40 -> data 1527 * 1528 * rev - 6 bit (word1) 1529 * len - 10 bit (word1) 1530 * id - 4 bit (word2) 1531 * rsv - 12 bit (word2) 1532 * 1533 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1534 * 1535 * 3. create binary file from the hex file 1536 * 1537 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1538 */ 1539 int iwl_read_external_nvm(struct iwl_trans *trans, 1540 const char *nvm_file_name, 1541 struct iwl_nvm_section *nvm_sections) 1542 { 1543 int ret, section_size; 1544 u16 section_id; 1545 const struct firmware *fw_entry; 1546 const struct { 1547 __le16 word1; 1548 __le16 word2; 1549 u8 data[]; 1550 } *file_sec; 1551 const u8 *eof; 1552 u8 *temp; 1553 int max_section_size; 1554 const __le32 *dword_buff; 1555 1556 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1557 #define NVM_WORD2_ID(x) (x >> 12) 1558 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1559 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1560 #define NVM_HEADER_0 (0x2A504C54) 1561 #define NVM_HEADER_1 (0x4E564D2A) 1562 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1563 1564 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1565 1566 /* Maximal size depends on NVM version */ 1567 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1568 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1569 else 1570 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1571 1572 /* 1573 * Obtain NVM image via request_firmware. Since we already used 1574 * request_firmware_nowait() for the firmware binary load and only 1575 * get here after that we assume the NVM request can be satisfied 1576 * synchronously. 1577 */ 1578 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1579 if (ret) { 1580 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1581 nvm_file_name, ret); 1582 return ret; 1583 } 1584 1585 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1586 nvm_file_name, fw_entry->size); 1587 1588 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1589 IWL_ERR(trans, "NVM file too large\n"); 1590 ret = -EINVAL; 1591 goto out; 1592 } 1593 1594 eof = fw_entry->data + fw_entry->size; 1595 dword_buff = (__le32 *)fw_entry->data; 1596 1597 /* some NVM file will contain a header. 1598 * The header is identified by 2 dwords header as follow: 1599 * dword[0] = 0x2A504C54 1600 * dword[1] = 0x4E564D2A 1601 * 1602 * This header must be skipped when providing the NVM data to the FW. 1603 */ 1604 if (fw_entry->size > NVM_HEADER_SIZE && 1605 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1606 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1607 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1608 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1609 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1610 le32_to_cpu(dword_buff[3])); 1611 1612 /* nvm file validation, dword_buff[2] holds the file version */ 1613 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1614 trans->hw_rev_step == SILICON_C_STEP && 1615 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1616 ret = -EFAULT; 1617 goto out; 1618 } 1619 } else { 1620 file_sec = (void *)fw_entry->data; 1621 } 1622 1623 while (true) { 1624 if (file_sec->data > eof) { 1625 IWL_ERR(trans, 1626 "ERROR - NVM file too short for section header\n"); 1627 ret = -EINVAL; 1628 break; 1629 } 1630 1631 /* check for EOF marker */ 1632 if (!file_sec->word1 && !file_sec->word2) { 1633 ret = 0; 1634 break; 1635 } 1636 1637 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1638 section_size = 1639 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1640 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1641 } else { 1642 section_size = 2 * EXT_NVM_WORD2_LEN( 1643 le16_to_cpu(file_sec->word2)); 1644 section_id = EXT_NVM_WORD1_ID( 1645 le16_to_cpu(file_sec->word1)); 1646 } 1647 1648 if (section_size > max_section_size) { 1649 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1650 section_size); 1651 ret = -EINVAL; 1652 break; 1653 } 1654 1655 if (!section_size) { 1656 IWL_ERR(trans, "ERROR - section empty\n"); 1657 ret = -EINVAL; 1658 break; 1659 } 1660 1661 if (file_sec->data + section_size > eof) { 1662 IWL_ERR(trans, 1663 "ERROR - NVM file too short for section (%d bytes)\n", 1664 section_size); 1665 ret = -EINVAL; 1666 break; 1667 } 1668 1669 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1670 "Invalid NVM section ID %d\n", section_id)) { 1671 ret = -EINVAL; 1672 break; 1673 } 1674 1675 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1676 if (!temp) { 1677 ret = -ENOMEM; 1678 break; 1679 } 1680 1681 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1682 1683 kfree(nvm_sections[section_id].data); 1684 nvm_sections[section_id].data = temp; 1685 nvm_sections[section_id].length = section_size; 1686 1687 /* advance to the next section */ 1688 file_sec = (void *)(file_sec->data + section_size); 1689 } 1690 out: 1691 release_firmware(fw_entry); 1692 return ret; 1693 } 1694 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1695 1696 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1697 const struct iwl_fw *fw) 1698 { 1699 struct iwl_nvm_get_info cmd = {}; 1700 struct iwl_nvm_data *nvm; 1701 struct iwl_host_cmd hcmd = { 1702 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1703 .data = { &cmd, }, 1704 .len = { sizeof(cmd) }, 1705 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1706 }; 1707 int ret; 1708 bool empty_otp; 1709 u32 mac_flags; 1710 u32 sbands_flags = 0; 1711 /* 1712 * All the values in iwl_nvm_get_info_rsp v4 are the same as 1713 * in v3, except for the channel profile part of the 1714 * regulatory. So we can just access the new struct, with the 1715 * exception of the latter. 1716 */ 1717 struct iwl_nvm_get_info_rsp *rsp; 1718 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 1719 bool v4 = fw_has_api(&fw->ucode_capa, 1720 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 1721 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 1722 void *channel_profile; 1723 1724 ret = iwl_trans_send_cmd(trans, &hcmd); 1725 if (ret) 1726 return ERR_PTR(ret); 1727 1728 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 1729 "Invalid payload len in NVM response from FW %d", 1730 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1731 ret = -EINVAL; 1732 goto out; 1733 } 1734 1735 rsp = (void *)hcmd.resp_pkt->data; 1736 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1737 NVM_GENERAL_FLAGS_EMPTY_OTP); 1738 if (empty_otp) 1739 IWL_INFO(trans, "OTP is empty\n"); 1740 1741 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 1742 if (!nvm) { 1743 ret = -ENOMEM; 1744 goto out; 1745 } 1746 1747 iwl_set_hw_address_from_csr(trans, nvm); 1748 /* TODO: if platform NVM has MAC address - override it here */ 1749 1750 if (!is_valid_ether_addr(nvm->hw_addr)) { 1751 IWL_ERR(trans, "no valid mac address was found\n"); 1752 ret = -EINVAL; 1753 goto err_free; 1754 } 1755 1756 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1757 1758 /* Initialize general data */ 1759 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1760 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1761 if (nvm->n_hw_addrs == 0) 1762 IWL_WARN(trans, 1763 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1764 empty_otp); 1765 1766 /* Initialize MAC sku data */ 1767 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1768 nvm->sku_cap_11ac_enable = 1769 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1770 nvm->sku_cap_11n_enable = 1771 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1772 nvm->sku_cap_11ax_enable = 1773 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1774 nvm->sku_cap_band_24ghz_enable = 1775 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1776 nvm->sku_cap_band_52ghz_enable = 1777 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1778 nvm->sku_cap_mimo_disabled = 1779 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1780 1781 /* Initialize PHY sku data */ 1782 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1783 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1784 1785 if (le32_to_cpu(rsp->regulatory.lar_enabled) && 1786 fw_has_capa(&fw->ucode_capa, 1787 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) { 1788 nvm->lar_enabled = true; 1789 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1790 } 1791 1792 rsp_v3 = (void *)rsp; 1793 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 1794 (void *)rsp_v3->regulatory.channel_profile; 1795 1796 iwl_init_sbands(trans, nvm, 1797 channel_profile, 1798 nvm->valid_tx_ant & fw->valid_tx_ant, 1799 nvm->valid_rx_ant & fw->valid_rx_ant, 1800 sbands_flags, v4, fw); 1801 1802 iwl_free_resp(&hcmd); 1803 return nvm; 1804 1805 err_free: 1806 kfree(nvm); 1807 out: 1808 iwl_free_resp(&hcmd); 1809 return ERR_PTR(ret); 1810 } 1811 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1812