1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/types.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/etherdevice.h> 11 #include <linux/pci.h> 12 #include <linux/firmware.h> 13 14 #include "iwl-drv.h" 15 #include "iwl-modparams.h" 16 #include "iwl-nvm-parse.h" 17 #include "iwl-prph.h" 18 #include "iwl-io.h" 19 #include "iwl-csr.h" 20 #include "fw/acpi.h" 21 #include "fw/api/nvm-reg.h" 22 #include "fw/api/commands.h" 23 #include "fw/api/cmdhdr.h" 24 #include "fw/img.h" 25 26 /* NVM offsets (in words) definitions */ 27 enum nvm_offsets { 28 /* NVM HW-Section offset (in words) definitions */ 29 SUBSYSTEM_ID = 0x0A, 30 HW_ADDR = 0x15, 31 32 /* NVM SW-Section offset (in words) definitions */ 33 NVM_SW_SECTION = 0x1C0, 34 NVM_VERSION = 0, 35 RADIO_CFG = 1, 36 SKU = 2, 37 N_HW_ADDRS = 3, 38 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 39 40 /* NVM calibration section offset (in words) definitions */ 41 NVM_CALIB_SECTION = 0x2B8, 42 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 43 44 /* NVM REGULATORY -Section offset (in words) definitions */ 45 NVM_CHANNELS_SDP = 0, 46 }; 47 48 enum ext_nvm_offsets { 49 /* NVM HW-Section offset (in words) definitions */ 50 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 51 52 /* NVM SW-Section offset (in words) definitions */ 53 NVM_VERSION_EXT_NVM = 0, 54 N_HW_ADDRS_FAMILY_8000 = 3, 55 56 /* NVM PHY_SKU-Section offset (in words) definitions */ 57 RADIO_CFG_FAMILY_EXT_NVM = 0, 58 SKU_FAMILY_8000 = 2, 59 60 /* NVM REGULATORY -Section offset (in words) definitions */ 61 NVM_CHANNELS_EXTENDED = 0, 62 NVM_LAR_OFFSET_OLD = 0x4C7, 63 NVM_LAR_OFFSET = 0x507, 64 NVM_LAR_ENABLED = 0x7, 65 }; 66 67 /* SKU Capabilities (actual values from NVM definition) */ 68 enum nvm_sku_bits { 69 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 70 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 71 NVM_SKU_CAP_11N_ENABLE = BIT(2), 72 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 73 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 74 }; 75 76 /* 77 * These are the channel numbers in the order that they are stored in the NVM 78 */ 79 static const u16 iwl_nvm_channels[] = { 80 /* 2.4 GHz */ 81 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 82 /* 5 GHz */ 83 36, 40, 44 , 48, 52, 56, 60, 64, 84 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 85 149, 153, 157, 161, 165 86 }; 87 88 static const u16 iwl_ext_nvm_channels[] = { 89 /* 2.4 GHz */ 90 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 91 /* 5 GHz */ 92 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 93 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 94 149, 153, 157, 161, 165, 169, 173, 177, 181 95 }; 96 97 static const u16 iwl_uhb_nvm_channels[] = { 98 /* 2.4 GHz */ 99 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 100 /* 5 GHz */ 101 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 102 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 103 149, 153, 157, 161, 165, 169, 173, 177, 181, 104 /* 6-7 GHz */ 105 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 106 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 107 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 108 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 109 }; 110 111 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 112 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 113 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 114 #define NUM_2GHZ_CHANNELS 14 115 #define NUM_5GHZ_CHANNELS 37 116 #define FIRST_2GHZ_HT_MINUS 5 117 #define LAST_2GHZ_HT_PLUS 9 118 #define N_HW_ADDR_MASK 0xF 119 120 /* rate data (static) */ 121 static struct ieee80211_rate iwl_cfg80211_rates[] = { 122 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 123 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 124 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 125 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 126 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 127 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 128 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 129 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 130 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 131 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 132 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 133 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 134 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 135 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 136 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 137 }; 138 #define RATES_24_OFFS 0 139 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 140 #define RATES_52_OFFS 4 141 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 142 143 /** 144 * enum iwl_nvm_channel_flags - channel flags in NVM 145 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 146 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 147 * @NVM_CHANNEL_ACTIVE: active scanning allowed 148 * @NVM_CHANNEL_RADAR: radar detection required 149 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 150 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 151 * on same channel on 2.4 or same UNII band on 5.2 152 * @NVM_CHANNEL_UNIFORM: uniform spreading required 153 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 154 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 155 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 156 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 157 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 158 */ 159 enum iwl_nvm_channel_flags { 160 NVM_CHANNEL_VALID = BIT(0), 161 NVM_CHANNEL_IBSS = BIT(1), 162 NVM_CHANNEL_ACTIVE = BIT(3), 163 NVM_CHANNEL_RADAR = BIT(4), 164 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 165 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 166 NVM_CHANNEL_UNIFORM = BIT(7), 167 NVM_CHANNEL_20MHZ = BIT(8), 168 NVM_CHANNEL_40MHZ = BIT(9), 169 NVM_CHANNEL_80MHZ = BIT(10), 170 NVM_CHANNEL_160MHZ = BIT(11), 171 NVM_CHANNEL_DC_HIGH = BIT(12), 172 }; 173 174 /** 175 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory 176 * domain. 177 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 178 * 2.4Ghz band is allowed. 179 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 180 * 5Ghz band is allowed. 181 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 182 * for this regulatory domain (valid only in 5Ghz). 183 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 184 * for this regulatory domain (valid only in 5Ghz). 185 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 186 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 187 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden 188 * for this regulatory domain (valid only in 5Ghz). 189 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed. 190 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 191 */ 192 enum iwl_reg_capa_flags { 193 REG_CAPA_BF_CCD_LOW_BAND = BIT(0), 194 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1), 195 REG_CAPA_160MHZ_ALLOWED = BIT(2), 196 REG_CAPA_80MHZ_ALLOWED = BIT(3), 197 REG_CAPA_MCS_8_ALLOWED = BIT(4), 198 REG_CAPA_MCS_9_ALLOWED = BIT(5), 199 REG_CAPA_40MHZ_FORBIDDEN = BIT(7), 200 REG_CAPA_DC_HIGH_ENABLED = BIT(9), 201 REG_CAPA_11AX_DISABLED = BIT(10), 202 }; 203 204 /** 205 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory 206 * domain (version 2). 207 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are 208 * disabled. 209 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 210 * 2.4Ghz band is allowed. 211 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 212 * 5Ghz band is allowed. 213 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 214 * for this regulatory domain (valid only in 5Ghz). 215 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 216 * for this regulatory domain (valid only in 5Ghz). 217 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 218 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 219 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118, 220 * 126, 122) are disabled. 221 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed 222 * for this regulatory domain (uvalid only in 5Ghz). 223 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 224 */ 225 enum iwl_reg_capa_flags_v2 { 226 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0), 227 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1), 228 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2), 229 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3), 230 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4), 231 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5), 232 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6), 233 REG_CAPA_V2_WEATHER_DISABLED = BIT(7), 234 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8), 235 REG_CAPA_V2_11AX_DISABLED = BIT(10), 236 }; 237 238 /* 239 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the 240 * MCC update command response. 241 */ 242 #define REG_CAPA_V2_RESP_VER 6 243 244 /** 245 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for 246 * handling the different APIs of reg_capa_flags. 247 * 248 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed 249 * for this regulatory domain (valid only in 5Ghz). 250 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed 251 * for this regulatory domain (valid only in 5Ghz). 252 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed 253 * for this regulatory domain (valid only in 5Ghz). 254 * @disable_11ax: 11ax is forbidden for this regulatory domain. 255 */ 256 struct iwl_reg_capa { 257 u16 allow_40mhz; 258 u16 allow_80mhz; 259 u16 allow_160mhz; 260 u16 disable_11ax; 261 }; 262 263 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 264 int chan, u32 flags) 265 { 266 #define CHECK_AND_PRINT_I(x) \ 267 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 268 269 if (!(flags & NVM_CHANNEL_VALID)) { 270 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 271 chan, flags); 272 return; 273 } 274 275 /* Note: already can print up to 101 characters, 110 is the limit! */ 276 IWL_DEBUG_DEV(dev, level, 277 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 278 chan, flags, 279 CHECK_AND_PRINT_I(VALID), 280 CHECK_AND_PRINT_I(IBSS), 281 CHECK_AND_PRINT_I(ACTIVE), 282 CHECK_AND_PRINT_I(RADAR), 283 CHECK_AND_PRINT_I(INDOOR_ONLY), 284 CHECK_AND_PRINT_I(GO_CONCURRENT), 285 CHECK_AND_PRINT_I(UNIFORM), 286 CHECK_AND_PRINT_I(20MHZ), 287 CHECK_AND_PRINT_I(40MHZ), 288 CHECK_AND_PRINT_I(80MHZ), 289 CHECK_AND_PRINT_I(160MHZ), 290 CHECK_AND_PRINT_I(DC_HIGH)); 291 #undef CHECK_AND_PRINT_I 292 } 293 294 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 295 u32 nvm_flags, const struct iwl_cfg *cfg) 296 { 297 u32 flags = IEEE80211_CHAN_NO_HT40; 298 299 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 300 if (ch_num <= LAST_2GHZ_HT_PLUS) 301 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 302 if (ch_num >= FIRST_2GHZ_HT_MINUS) 303 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 304 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 305 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 306 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 307 else 308 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 309 } 310 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 311 flags |= IEEE80211_CHAN_NO_80MHZ; 312 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 313 flags |= IEEE80211_CHAN_NO_160MHZ; 314 315 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 316 flags |= IEEE80211_CHAN_NO_IR; 317 318 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 319 flags |= IEEE80211_CHAN_NO_IR; 320 321 if (nvm_flags & NVM_CHANNEL_RADAR) 322 flags |= IEEE80211_CHAN_RADAR; 323 324 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 325 flags |= IEEE80211_CHAN_INDOOR_ONLY; 326 327 /* Set the GO concurrent flag only in case that NO_IR is set. 328 * Otherwise it is meaningless 329 */ 330 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 331 (flags & IEEE80211_CHAN_NO_IR)) 332 flags |= IEEE80211_CHAN_IR_CONCURRENT; 333 334 return flags; 335 } 336 337 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 338 { 339 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) { 340 return NL80211_BAND_6GHZ; 341 } 342 343 if (ch_idx >= NUM_2GHZ_CHANNELS) 344 return NL80211_BAND_5GHZ; 345 return NL80211_BAND_2GHZ; 346 } 347 348 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 349 struct iwl_nvm_data *data, 350 const void * const nvm_ch_flags, 351 u32 sbands_flags, bool v4) 352 { 353 int ch_idx; 354 int n_channels = 0; 355 struct ieee80211_channel *channel; 356 u32 ch_flags; 357 int num_of_ch; 358 const u16 *nvm_chan; 359 360 if (cfg->uhb_supported) { 361 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 362 nvm_chan = iwl_uhb_nvm_channels; 363 } else if (cfg->nvm_type == IWL_NVM_EXT) { 364 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 365 nvm_chan = iwl_ext_nvm_channels; 366 } else { 367 num_of_ch = IWL_NVM_NUM_CHANNELS; 368 nvm_chan = iwl_nvm_channels; 369 } 370 371 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 372 enum nl80211_band band = 373 iwl_nl80211_band_from_channel_idx(ch_idx); 374 375 if (v4) 376 ch_flags = 377 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx); 378 else 379 ch_flags = 380 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx); 381 382 if (band == NL80211_BAND_5GHZ && 383 !data->sku_cap_band_52ghz_enable) 384 continue; 385 386 /* workaround to disable wide channels in 5GHz */ 387 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 388 band == NL80211_BAND_5GHZ) { 389 ch_flags &= ~(NVM_CHANNEL_40MHZ | 390 NVM_CHANNEL_80MHZ | 391 NVM_CHANNEL_160MHZ); 392 } 393 394 if (ch_flags & NVM_CHANNEL_160MHZ) 395 data->vht160_supported = true; 396 397 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 398 !(ch_flags & NVM_CHANNEL_VALID)) { 399 /* 400 * Channels might become valid later if lar is 401 * supported, hence we still want to add them to 402 * the list of supported channels to cfg80211. 403 */ 404 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 405 nvm_chan[ch_idx], ch_flags); 406 continue; 407 } 408 409 channel = &data->channels[n_channels]; 410 n_channels++; 411 412 channel->hw_value = nvm_chan[ch_idx]; 413 channel->band = band; 414 channel->center_freq = 415 ieee80211_channel_to_frequency( 416 channel->hw_value, channel->band); 417 418 /* Initialize regulatory-based run-time data */ 419 420 /* 421 * Default value - highest tx power value. max_power 422 * is not used in mvm, and is used for backwards compatibility 423 */ 424 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 425 426 /* don't put limitations in case we're using LAR */ 427 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 428 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 429 ch_idx, band, 430 ch_flags, cfg); 431 else 432 channel->flags = 0; 433 434 /* TODO: Don't put limitations on UHB devices as we still don't 435 * have NVM for them 436 */ 437 if (cfg->uhb_supported) 438 channel->flags = 0; 439 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 440 channel->hw_value, ch_flags); 441 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 442 channel->hw_value, channel->max_power); 443 } 444 445 return n_channels; 446 } 447 448 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 449 struct iwl_nvm_data *data, 450 struct ieee80211_sta_vht_cap *vht_cap, 451 u8 tx_chains, u8 rx_chains) 452 { 453 const struct iwl_cfg *cfg = trans->cfg; 454 int num_rx_ants = num_of_ant(rx_chains); 455 int num_tx_ants = num_of_ant(tx_chains); 456 457 vht_cap->vht_supported = true; 458 459 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 460 IEEE80211_VHT_CAP_RXSTBC_1 | 461 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 462 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 463 IEEE80211_VHT_MAX_AMPDU_1024K << 464 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 465 466 if (data->vht160_supported) 467 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 468 IEEE80211_VHT_CAP_SHORT_GI_160; 469 470 if (cfg->vht_mu_mimo_supported) 471 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 472 473 if (cfg->ht_params->ldpc) 474 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 475 476 if (data->sku_cap_mimo_disabled) { 477 num_rx_ants = 1; 478 num_tx_ants = 1; 479 } 480 481 if (num_tx_ants > 1) 482 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 483 else 484 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 485 486 switch (iwlwifi_mod_params.amsdu_size) { 487 case IWL_AMSDU_DEF: 488 if (trans->trans_cfg->mq_rx_supported) 489 vht_cap->cap |= 490 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 491 else 492 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 493 break; 494 case IWL_AMSDU_2K: 495 if (trans->trans_cfg->mq_rx_supported) 496 vht_cap->cap |= 497 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 498 else 499 WARN(1, "RB size of 2K is not supported by this device\n"); 500 break; 501 case IWL_AMSDU_4K: 502 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 503 break; 504 case IWL_AMSDU_8K: 505 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 506 break; 507 case IWL_AMSDU_12K: 508 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 509 break; 510 default: 511 break; 512 } 513 514 vht_cap->vht_mcs.rx_mcs_map = 515 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 516 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 517 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 520 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 523 524 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 525 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 526 /* this works because NOT_SUPPORTED == 3 */ 527 vht_cap->vht_mcs.rx_mcs_map |= 528 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 529 } 530 531 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 532 533 vht_cap->vht_mcs.tx_highest |= 534 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 535 } 536 537 static const u8 iwl_vendor_caps[] = { 538 0xdd, /* vendor element */ 539 0x06, /* length */ 540 0x00, 0x17, 0x35, /* Intel OUI */ 541 0x08, /* type (Intel Capabilities) */ 542 /* followed by 16 bits of capabilities */ 543 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0) 544 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE, 545 0x00 546 }; 547 548 static const struct ieee80211_sband_iftype_data iwl_he_capa[] = { 549 { 550 .types_mask = BIT(NL80211_IFTYPE_STATION), 551 .he_cap = { 552 .has_he = true, 553 .he_cap_elem = { 554 .mac_cap_info[0] = 555 IEEE80211_HE_MAC_CAP0_HTC_HE | 556 IEEE80211_HE_MAC_CAP0_TWT_REQ, 557 .mac_cap_info[1] = 558 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 559 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 560 .mac_cap_info[2] = 561 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP, 562 .mac_cap_info[3] = 563 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 564 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS, 565 .mac_cap_info[4] = 566 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU | 567 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 568 .mac_cap_info[5] = 569 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 570 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 571 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 572 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 573 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 574 .phy_cap_info[0] = 575 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 576 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 577 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 578 .phy_cap_info[1] = 579 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 580 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 581 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 582 .phy_cap_info[2] = 583 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 584 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 585 .phy_cap_info[3] = 586 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 587 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 588 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 589 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 590 .phy_cap_info[4] = 591 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 592 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 593 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 594 .phy_cap_info[6] = 595 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 596 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB | 597 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 598 .phy_cap_info[7] = 599 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 600 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 601 .phy_cap_info[8] = 602 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 603 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 604 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 605 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 606 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 607 .phy_cap_info[9] = 608 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 609 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 610 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED, 611 .phy_cap_info[10] = 612 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF, 613 }, 614 /* 615 * Set default Tx/Rx HE MCS NSS Support field. 616 * Indicate support for up to 2 spatial streams and all 617 * MCS, without any special cases 618 */ 619 .he_mcs_nss_supp = { 620 .rx_mcs_80 = cpu_to_le16(0xfffa), 621 .tx_mcs_80 = cpu_to_le16(0xfffa), 622 .rx_mcs_160 = cpu_to_le16(0xfffa), 623 .tx_mcs_160 = cpu_to_le16(0xfffa), 624 .rx_mcs_80p80 = cpu_to_le16(0xffff), 625 .tx_mcs_80p80 = cpu_to_le16(0xffff), 626 }, 627 /* 628 * Set default PPE thresholds, with PPET16 set to 0, 629 * PPET8 set to 7 630 */ 631 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 632 }, 633 }, 634 { 635 .types_mask = BIT(NL80211_IFTYPE_AP), 636 .he_cap = { 637 .has_he = true, 638 .he_cap_elem = { 639 .mac_cap_info[0] = 640 IEEE80211_HE_MAC_CAP0_HTC_HE, 641 .mac_cap_info[1] = 642 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 643 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 644 .mac_cap_info[3] = 645 IEEE80211_HE_MAC_CAP3_OMI_CONTROL, 646 .phy_cap_info[0] = 647 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 648 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G, 649 .phy_cap_info[1] = 650 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 651 .phy_cap_info[2] = 652 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 653 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 654 .phy_cap_info[3] = 655 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 656 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 657 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 658 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 659 .phy_cap_info[6] = 660 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 661 .phy_cap_info[7] = 662 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 663 .phy_cap_info[8] = 664 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 665 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 666 .phy_cap_info[9] = 667 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED, 668 }, 669 /* 670 * Set default Tx/Rx HE MCS NSS Support field. 671 * Indicate support for up to 2 spatial streams and all 672 * MCS, without any special cases 673 */ 674 .he_mcs_nss_supp = { 675 .rx_mcs_80 = cpu_to_le16(0xfffa), 676 .tx_mcs_80 = cpu_to_le16(0xfffa), 677 .rx_mcs_160 = cpu_to_le16(0xfffa), 678 .tx_mcs_160 = cpu_to_le16(0xfffa), 679 .rx_mcs_80p80 = cpu_to_le16(0xffff), 680 .tx_mcs_80p80 = cpu_to_le16(0xffff), 681 }, 682 /* 683 * Set default PPE thresholds, with PPET16 set to 0, 684 * PPET8 set to 7 685 */ 686 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 687 }, 688 }, 689 }; 690 691 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans, 692 struct iwl_nvm_data *data, 693 struct ieee80211_supported_band *sband, 694 u8 tx_chains, u8 rx_chains) 695 { 696 struct ieee80211_sta_ht_cap ht_cap; 697 struct ieee80211_sta_vht_cap vht_cap = {}; 698 struct ieee80211_sband_iftype_data *iftype_data; 699 u16 he_6ghz_capa = 0; 700 u32 exp; 701 int i; 702 703 if (sband->band != NL80211_BAND_6GHZ) 704 return; 705 706 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */ 707 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ, 708 tx_chains, rx_chains); 709 WARN_ON(!ht_cap.ht_supported); 710 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains); 711 WARN_ON(!vht_cap.vht_supported); 712 713 he_6ghz_capa |= 714 u16_encode_bits(ht_cap.ampdu_density, 715 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START); 716 exp = u32_get_bits(vht_cap.cap, 717 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK); 718 he_6ghz_capa |= 719 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP); 720 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK); 721 he_6ghz_capa |= 722 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 723 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */ 724 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN) 725 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS; 726 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN) 727 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 728 729 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa); 730 731 /* we know it's writable - we set it before ourselves */ 732 iftype_data = (void *)sband->iftype_data; 733 for (i = 0; i < sband->n_iftype_data; i++) 734 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa); 735 } 736 737 static void 738 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, 739 struct ieee80211_supported_band *sband, 740 struct ieee80211_sband_iftype_data *iftype_data, 741 u8 tx_chains, u8 rx_chains, 742 const struct iwl_fw *fw) 743 { 744 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP); 745 746 /* Advertise an A-MPDU exponent extension based on 747 * operating band 748 */ 749 if (sband->band != NL80211_BAND_2GHZ) 750 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 751 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1; 752 else 753 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 754 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 755 756 if (is_ap && iwlwifi_mod_params.nvm_file) 757 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 758 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 759 760 if ((tx_chains & rx_chains) == ANT_AB) { 761 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 762 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ; 763 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |= 764 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 765 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2; 766 if (!is_ap) 767 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 768 IEEE80211_HE_PHY_CAP7_MAX_NC_2; 769 } else if (!is_ap) { 770 /* If not 2x2, we need to indicate 1x1 in the 771 * Midamble RX Max NSTS - but not for AP mode 772 */ 773 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &= 774 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 775 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 776 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 777 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 778 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 779 } 780 781 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 782 case IWL_CFG_RF_TYPE_GF: 783 case IWL_CFG_RF_TYPE_MR: 784 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 785 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 786 if (!is_ap) 787 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 788 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 789 break; 790 } 791 792 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT)) 793 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |= 794 IEEE80211_HE_MAC_CAP2_BCAST_TWT; 795 796 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 797 !is_ap) { 798 iftype_data->vendor_elems.data = iwl_vendor_caps; 799 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps); 800 } 801 } 802 803 static void iwl_init_he_hw_capab(struct iwl_trans *trans, 804 struct iwl_nvm_data *data, 805 struct ieee80211_supported_band *sband, 806 u8 tx_chains, u8 rx_chains, 807 const struct iwl_fw *fw) 808 { 809 struct ieee80211_sband_iftype_data *iftype_data; 810 int i; 811 812 /* should only initialize once */ 813 if (WARN_ON(sband->iftype_data)) 814 return; 815 816 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_capa)); 817 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_capa)); 818 819 switch (sband->band) { 820 case NL80211_BAND_2GHZ: 821 iftype_data = data->iftd.low; 822 break; 823 case NL80211_BAND_5GHZ: 824 case NL80211_BAND_6GHZ: 825 iftype_data = data->iftd.high; 826 break; 827 default: 828 WARN_ON(1); 829 return; 830 } 831 832 memcpy(iftype_data, iwl_he_capa, sizeof(iwl_he_capa)); 833 834 sband->iftype_data = iftype_data; 835 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa); 836 837 for (i = 0; i < sband->n_iftype_data; i++) 838 iwl_nvm_fixup_sband_iftd(trans, sband, &iftype_data[i], 839 tx_chains, rx_chains, fw); 840 841 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains); 842 } 843 844 static void iwl_init_sbands(struct iwl_trans *trans, 845 struct iwl_nvm_data *data, 846 const void *nvm_ch_flags, u8 tx_chains, 847 u8 rx_chains, u32 sbands_flags, bool v4, 848 const struct iwl_fw *fw) 849 { 850 struct device *dev = trans->dev; 851 const struct iwl_cfg *cfg = trans->cfg; 852 int n_channels; 853 int n_used = 0; 854 struct ieee80211_supported_band *sband; 855 856 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 857 sbands_flags, v4); 858 sband = &data->bands[NL80211_BAND_2GHZ]; 859 sband->band = NL80211_BAND_2GHZ; 860 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 861 sband->n_bitrates = N_RATES_24; 862 n_used += iwl_init_sband_channels(data, sband, n_channels, 863 NL80211_BAND_2GHZ); 864 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 865 tx_chains, rx_chains); 866 867 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 868 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 869 fw); 870 871 sband = &data->bands[NL80211_BAND_5GHZ]; 872 sband->band = NL80211_BAND_5GHZ; 873 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 874 sband->n_bitrates = N_RATES_52; 875 n_used += iwl_init_sband_channels(data, sband, n_channels, 876 NL80211_BAND_5GHZ); 877 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 878 tx_chains, rx_chains); 879 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 880 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 881 tx_chains, rx_chains); 882 883 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 884 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 885 fw); 886 887 /* 6GHz band. */ 888 sband = &data->bands[NL80211_BAND_6GHZ]; 889 sband->band = NL80211_BAND_6GHZ; 890 /* use the same rates as 5GHz band */ 891 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 892 sband->n_bitrates = N_RATES_52; 893 n_used += iwl_init_sband_channels(data, sband, n_channels, 894 NL80211_BAND_6GHZ); 895 896 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 897 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 898 fw); 899 else 900 sband->n_channels = 0; 901 if (n_channels != n_used) 902 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 903 n_used, n_channels); 904 } 905 906 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 907 const __le16 *phy_sku) 908 { 909 if (cfg->nvm_type != IWL_NVM_EXT) 910 return le16_to_cpup(nvm_sw + SKU); 911 912 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 913 } 914 915 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 916 { 917 if (cfg->nvm_type != IWL_NVM_EXT) 918 return le16_to_cpup(nvm_sw + NVM_VERSION); 919 else 920 return le32_to_cpup((__le32 *)(nvm_sw + 921 NVM_VERSION_EXT_NVM)); 922 } 923 924 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 925 const __le16 *phy_sku) 926 { 927 if (cfg->nvm_type != IWL_NVM_EXT) 928 return le16_to_cpup(nvm_sw + RADIO_CFG); 929 930 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 931 932 } 933 934 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 935 { 936 int n_hw_addr; 937 938 if (cfg->nvm_type != IWL_NVM_EXT) 939 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 940 941 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 942 943 return n_hw_addr & N_HW_ADDR_MASK; 944 } 945 946 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 947 struct iwl_nvm_data *data, 948 u32 radio_cfg) 949 { 950 if (cfg->nvm_type != IWL_NVM_EXT) { 951 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 952 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 953 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 954 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 955 return; 956 } 957 958 /* set the radio configuration for family 8000 */ 959 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 960 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 961 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 962 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 963 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 964 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 965 } 966 967 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 968 { 969 const u8 *hw_addr; 970 971 hw_addr = (const u8 *)&mac_addr0; 972 dest[0] = hw_addr[3]; 973 dest[1] = hw_addr[2]; 974 dest[2] = hw_addr[1]; 975 dest[3] = hw_addr[0]; 976 977 hw_addr = (const u8 *)&mac_addr1; 978 dest[4] = hw_addr[1]; 979 dest[5] = hw_addr[0]; 980 } 981 982 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 983 struct iwl_nvm_data *data) 984 { 985 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, 986 CSR_MAC_ADDR0_STRAP(trans))); 987 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, 988 CSR_MAC_ADDR1_STRAP(trans))); 989 990 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 991 /* 992 * If the OEM fused a valid address, use it instead of the one in the 993 * OTP 994 */ 995 if (is_valid_ether_addr(data->hw_addr)) 996 return; 997 998 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); 999 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); 1000 1001 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1002 } 1003 1004 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 1005 const struct iwl_cfg *cfg, 1006 struct iwl_nvm_data *data, 1007 const __le16 *mac_override, 1008 const __be16 *nvm_hw) 1009 { 1010 const u8 *hw_addr; 1011 1012 if (mac_override) { 1013 static const u8 reserved_mac[] = { 1014 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1015 }; 1016 1017 hw_addr = (const u8 *)(mac_override + 1018 MAC_ADDRESS_OVERRIDE_EXT_NVM); 1019 1020 /* 1021 * Store the MAC address from MAO section. 1022 * No byte swapping is required in MAO section 1023 */ 1024 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 1025 1026 /* 1027 * Force the use of the OTP MAC address in case of reserved MAC 1028 * address in the NVM, or if address is given but invalid. 1029 */ 1030 if (is_valid_ether_addr(data->hw_addr) && 1031 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 1032 return; 1033 1034 IWL_ERR(trans, 1035 "mac address from nvm override section is not valid\n"); 1036 } 1037 1038 if (nvm_hw) { 1039 /* read the mac address from WFMP registers */ 1040 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 1041 WFMP_MAC_ADDR_0)); 1042 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 1043 WFMP_MAC_ADDR_1)); 1044 1045 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1046 1047 return; 1048 } 1049 1050 IWL_ERR(trans, "mac address is not found\n"); 1051 } 1052 1053 static int iwl_set_hw_address(struct iwl_trans *trans, 1054 const struct iwl_cfg *cfg, 1055 struct iwl_nvm_data *data, const __be16 *nvm_hw, 1056 const __le16 *mac_override) 1057 { 1058 if (cfg->mac_addr_from_csr) { 1059 iwl_set_hw_address_from_csr(trans, data); 1060 } else if (cfg->nvm_type != IWL_NVM_EXT) { 1061 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 1062 1063 /* The byte order is little endian 16 bit, meaning 214365 */ 1064 data->hw_addr[0] = hw_addr[1]; 1065 data->hw_addr[1] = hw_addr[0]; 1066 data->hw_addr[2] = hw_addr[3]; 1067 data->hw_addr[3] = hw_addr[2]; 1068 data->hw_addr[4] = hw_addr[5]; 1069 data->hw_addr[5] = hw_addr[4]; 1070 } else { 1071 iwl_set_hw_address_family_8000(trans, cfg, data, 1072 mac_override, nvm_hw); 1073 } 1074 1075 if (!is_valid_ether_addr(data->hw_addr)) { 1076 IWL_ERR(trans, "no valid mac address was found\n"); 1077 return -EINVAL; 1078 } 1079 1080 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 1081 1082 return 0; 1083 } 1084 1085 static bool 1086 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1087 const __be16 *nvm_hw) 1088 { 1089 /* 1090 * Workaround a bug in Indonesia SKUs where the regulatory in 1091 * some 7000-family OTPs erroneously allow wide channels in 1092 * 5GHz. To check for Indonesia, we take the SKU value from 1093 * bits 1-4 in the subsystem ID and check if it is either 5 or 1094 * 9. In those cases, we need to force-disable wide channels 1095 * in 5GHz otherwise the FW will throw a sysassert when we try 1096 * to use them. 1097 */ 1098 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1099 /* 1100 * Unlike the other sections in the NVM, the hw 1101 * section uses big-endian. 1102 */ 1103 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 1104 u8 sku = (subsystem_id & 0x1e) >> 1; 1105 1106 if (sku == 5 || sku == 9) { 1107 IWL_DEBUG_EEPROM(trans->dev, 1108 "disabling wide channels in 5GHz (0x%0x %d)\n", 1109 subsystem_id, sku); 1110 return true; 1111 } 1112 } 1113 1114 return false; 1115 } 1116 1117 struct iwl_nvm_data * 1118 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1119 const struct iwl_fw *fw, 1120 const __be16 *nvm_hw, const __le16 *nvm_sw, 1121 const __le16 *nvm_calib, const __le16 *regulatory, 1122 const __le16 *mac_override, const __le16 *phy_sku, 1123 u8 tx_chains, u8 rx_chains) 1124 { 1125 struct iwl_nvm_data *data; 1126 bool lar_enabled; 1127 u32 sku, radio_cfg; 1128 u32 sbands_flags = 0; 1129 u16 lar_config; 1130 const __le16 *ch_section; 1131 1132 if (cfg->uhb_supported) 1133 data = kzalloc(struct_size(data, channels, 1134 IWL_NVM_NUM_CHANNELS_UHB), 1135 GFP_KERNEL); 1136 else if (cfg->nvm_type != IWL_NVM_EXT) 1137 data = kzalloc(struct_size(data, channels, 1138 IWL_NVM_NUM_CHANNELS), 1139 GFP_KERNEL); 1140 else 1141 data = kzalloc(struct_size(data, channels, 1142 IWL_NVM_NUM_CHANNELS_EXT), 1143 GFP_KERNEL); 1144 if (!data) 1145 return NULL; 1146 1147 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 1148 1149 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 1150 iwl_set_radio_cfg(cfg, data, radio_cfg); 1151 if (data->valid_tx_ant) 1152 tx_chains &= data->valid_tx_ant; 1153 if (data->valid_rx_ant) 1154 rx_chains &= data->valid_rx_ant; 1155 1156 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 1157 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 1158 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 1159 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 1160 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1161 data->sku_cap_11n_enable = false; 1162 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 1163 (sku & NVM_SKU_CAP_11AC_ENABLE); 1164 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 1165 1166 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 1167 1168 if (cfg->nvm_type != IWL_NVM_EXT) { 1169 /* Checking for required sections */ 1170 if (!nvm_calib) { 1171 IWL_ERR(trans, 1172 "Can't parse empty Calib NVM sections\n"); 1173 kfree(data); 1174 return NULL; 1175 } 1176 1177 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1178 ®ulatory[NVM_CHANNELS_SDP] : 1179 &nvm_sw[NVM_CHANNELS]; 1180 1181 /* in family 8000 Xtal calibration values moved to OTP */ 1182 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 1183 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 1184 lar_enabled = true; 1185 } else { 1186 u16 lar_offset = data->nvm_version < 0xE39 ? 1187 NVM_LAR_OFFSET_OLD : 1188 NVM_LAR_OFFSET; 1189 1190 lar_config = le16_to_cpup(regulatory + lar_offset); 1191 data->lar_enabled = !!(lar_config & 1192 NVM_LAR_ENABLED); 1193 lar_enabled = data->lar_enabled; 1194 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1195 } 1196 1197 /* If no valid mac address was found - bail out */ 1198 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1199 kfree(data); 1200 return NULL; 1201 } 1202 1203 if (lar_enabled && 1204 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1205 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1206 1207 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1208 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1209 1210 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1211 sbands_flags, false, fw); 1212 data->calib_version = 255; 1213 1214 return data; 1215 } 1216 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1217 1218 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1219 int ch_idx, u16 nvm_flags, 1220 struct iwl_reg_capa reg_capa, 1221 const struct iwl_cfg *cfg) 1222 { 1223 u32 flags = NL80211_RRF_NO_HT40; 1224 1225 if (ch_idx < NUM_2GHZ_CHANNELS && 1226 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1227 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1228 flags &= ~NL80211_RRF_NO_HT40PLUS; 1229 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1230 flags &= ~NL80211_RRF_NO_HT40MINUS; 1231 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1232 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1233 flags &= ~NL80211_RRF_NO_HT40PLUS; 1234 else 1235 flags &= ~NL80211_RRF_NO_HT40MINUS; 1236 } 1237 1238 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1239 flags |= NL80211_RRF_NO_80MHZ; 1240 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1241 flags |= NL80211_RRF_NO_160MHZ; 1242 1243 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1244 flags |= NL80211_RRF_NO_IR; 1245 1246 if (nvm_flags & NVM_CHANNEL_RADAR) 1247 flags |= NL80211_RRF_DFS; 1248 1249 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1250 flags |= NL80211_RRF_NO_OUTDOOR; 1251 1252 /* Set the GO concurrent flag only in case that NO_IR is set. 1253 * Otherwise it is meaningless 1254 */ 1255 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1256 (flags & NL80211_RRF_NO_IR)) 1257 flags |= NL80211_RRF_GO_CONCURRENT; 1258 1259 /* 1260 * reg_capa is per regulatory domain so apply it for every channel 1261 */ 1262 if (ch_idx >= NUM_2GHZ_CHANNELS) { 1263 if (!reg_capa.allow_40mhz) 1264 flags |= NL80211_RRF_NO_HT40; 1265 1266 if (!reg_capa.allow_80mhz) 1267 flags |= NL80211_RRF_NO_80MHZ; 1268 1269 if (!reg_capa.allow_160mhz) 1270 flags |= NL80211_RRF_NO_160MHZ; 1271 } 1272 if (reg_capa.disable_11ax) 1273 flags |= NL80211_RRF_NO_HE; 1274 1275 return flags; 1276 } 1277 1278 static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver) 1279 { 1280 struct iwl_reg_capa reg_capa; 1281 1282 if (resp_ver >= REG_CAPA_V2_RESP_VER) { 1283 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED; 1284 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED; 1285 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED; 1286 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED; 1287 } else { 1288 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN); 1289 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED; 1290 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED; 1291 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED; 1292 } 1293 return reg_capa; 1294 } 1295 1296 struct ieee80211_regdomain * 1297 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1298 int num_of_ch, __le32 *channels, u16 fw_mcc, 1299 u16 geo_info, u16 cap, u8 resp_ver) 1300 { 1301 int ch_idx; 1302 u16 ch_flags; 1303 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1304 const u16 *nvm_chan; 1305 struct ieee80211_regdomain *regd, *copy_rd; 1306 struct ieee80211_reg_rule *rule; 1307 enum nl80211_band band; 1308 int center_freq, prev_center_freq = 0; 1309 int valid_rules = 0; 1310 bool new_rule; 1311 int max_num_ch; 1312 struct iwl_reg_capa reg_capa; 1313 1314 if (cfg->uhb_supported) { 1315 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1316 nvm_chan = iwl_uhb_nvm_channels; 1317 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1318 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1319 nvm_chan = iwl_ext_nvm_channels; 1320 } else { 1321 max_num_ch = IWL_NVM_NUM_CHANNELS; 1322 nvm_chan = iwl_nvm_channels; 1323 } 1324 1325 if (WARN_ON(num_of_ch > max_num_ch)) 1326 num_of_ch = max_num_ch; 1327 1328 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1329 return ERR_PTR(-EINVAL); 1330 1331 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1332 num_of_ch); 1333 1334 /* build a regdomain rule for every valid channel */ 1335 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1336 if (!regd) 1337 return ERR_PTR(-ENOMEM); 1338 1339 /* set alpha2 from FW. */ 1340 regd->alpha2[0] = fw_mcc >> 8; 1341 regd->alpha2[1] = fw_mcc & 0xff; 1342 1343 /* parse regulatory capability flags */ 1344 reg_capa = iwl_get_reg_capa(cap, resp_ver); 1345 1346 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1347 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1348 band = iwl_nl80211_band_from_channel_idx(ch_idx); 1349 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1350 band); 1351 new_rule = false; 1352 1353 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1354 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1355 nvm_chan[ch_idx], ch_flags); 1356 continue; 1357 } 1358 1359 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1360 ch_flags, reg_capa, 1361 cfg); 1362 1363 /* we can't continue the same rule */ 1364 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1365 center_freq - prev_center_freq > 20) { 1366 valid_rules++; 1367 new_rule = true; 1368 } 1369 1370 rule = ®d->reg_rules[valid_rules - 1]; 1371 1372 if (new_rule) 1373 rule->freq_range.start_freq_khz = 1374 MHZ_TO_KHZ(center_freq - 10); 1375 1376 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1377 1378 /* this doesn't matter - not used by FW */ 1379 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1380 rule->power_rule.max_eirp = 1381 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1382 1383 rule->flags = reg_rule_flags; 1384 1385 /* rely on auto-calculation to merge BW of contiguous chans */ 1386 rule->flags |= NL80211_RRF_AUTO_BW; 1387 rule->freq_range.max_bandwidth_khz = 0; 1388 1389 prev_center_freq = center_freq; 1390 prev_reg_rule_flags = reg_rule_flags; 1391 1392 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1393 nvm_chan[ch_idx], ch_flags); 1394 1395 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1396 band == NL80211_BAND_2GHZ) 1397 continue; 1398 1399 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1400 } 1401 1402 /* 1403 * Certain firmware versions might report no valid channels 1404 * if booted in RF-kill, i.e. not all calibrations etc. are 1405 * running. We'll get out of this situation later when the 1406 * rfkill is removed and we update the regdomain again, but 1407 * since cfg80211 doesn't accept an empty regdomain, add a 1408 * dummy (unusable) rule here in this case so we can init. 1409 */ 1410 if (!valid_rules) { 1411 valid_rules = 1; 1412 rule = ®d->reg_rules[valid_rules - 1]; 1413 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412); 1414 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413); 1415 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1); 1416 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1417 rule->power_rule.max_eirp = 1418 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1419 } 1420 1421 regd->n_reg_rules = valid_rules; 1422 1423 /* 1424 * Narrow down regdom for unused regulatory rules to prevent hole 1425 * between reg rules to wmm rules. 1426 */ 1427 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1428 GFP_KERNEL); 1429 if (!copy_rd) 1430 copy_rd = ERR_PTR(-ENOMEM); 1431 1432 kfree(regd); 1433 return copy_rd; 1434 } 1435 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1436 1437 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1438 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1439 #define MAX_NVM_FILE_LEN 16384 1440 1441 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1442 unsigned int len) 1443 { 1444 #define IWL_4165_DEVICE_ID 0x5501 1445 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1446 1447 if (section == NVM_SECTION_TYPE_PHY_SKU && 1448 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1449 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1450 /* OTP 0x52 bug work around: it's a 1x1 device */ 1451 data[3] = ANT_B | (ANT_B << 4); 1452 } 1453 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1454 1455 /* 1456 * Reads external NVM from a file into mvm->nvm_sections 1457 * 1458 * HOW TO CREATE THE NVM FILE FORMAT: 1459 * ------------------------------ 1460 * 1. create hex file, format: 1461 * 3800 -> header 1462 * 0000 -> header 1463 * 5a40 -> data 1464 * 1465 * rev - 6 bit (word1) 1466 * len - 10 bit (word1) 1467 * id - 4 bit (word2) 1468 * rsv - 12 bit (word2) 1469 * 1470 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1471 * 1472 * 3. create binary file from the hex file 1473 * 1474 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1475 */ 1476 int iwl_read_external_nvm(struct iwl_trans *trans, 1477 const char *nvm_file_name, 1478 struct iwl_nvm_section *nvm_sections) 1479 { 1480 int ret, section_size; 1481 u16 section_id; 1482 const struct firmware *fw_entry; 1483 const struct { 1484 __le16 word1; 1485 __le16 word2; 1486 u8 data[]; 1487 } *file_sec; 1488 const u8 *eof; 1489 u8 *temp; 1490 int max_section_size; 1491 const __le32 *dword_buff; 1492 1493 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1494 #define NVM_WORD2_ID(x) (x >> 12) 1495 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1496 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1497 #define NVM_HEADER_0 (0x2A504C54) 1498 #define NVM_HEADER_1 (0x4E564D2A) 1499 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1500 1501 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1502 1503 /* Maximal size depends on NVM version */ 1504 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1505 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1506 else 1507 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1508 1509 /* 1510 * Obtain NVM image via request_firmware. Since we already used 1511 * request_firmware_nowait() for the firmware binary load and only 1512 * get here after that we assume the NVM request can be satisfied 1513 * synchronously. 1514 */ 1515 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1516 if (ret) { 1517 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1518 nvm_file_name, ret); 1519 return ret; 1520 } 1521 1522 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1523 nvm_file_name, fw_entry->size); 1524 1525 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1526 IWL_ERR(trans, "NVM file too large\n"); 1527 ret = -EINVAL; 1528 goto out; 1529 } 1530 1531 eof = fw_entry->data + fw_entry->size; 1532 dword_buff = (__le32 *)fw_entry->data; 1533 1534 /* some NVM file will contain a header. 1535 * The header is identified by 2 dwords header as follow: 1536 * dword[0] = 0x2A504C54 1537 * dword[1] = 0x4E564D2A 1538 * 1539 * This header must be skipped when providing the NVM data to the FW. 1540 */ 1541 if (fw_entry->size > NVM_HEADER_SIZE && 1542 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1543 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1544 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1545 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1546 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1547 le32_to_cpu(dword_buff[3])); 1548 1549 /* nvm file validation, dword_buff[2] holds the file version */ 1550 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1551 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP && 1552 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1553 ret = -EFAULT; 1554 goto out; 1555 } 1556 } else { 1557 file_sec = (void *)fw_entry->data; 1558 } 1559 1560 while (true) { 1561 if (file_sec->data > eof) { 1562 IWL_ERR(trans, 1563 "ERROR - NVM file too short for section header\n"); 1564 ret = -EINVAL; 1565 break; 1566 } 1567 1568 /* check for EOF marker */ 1569 if (!file_sec->word1 && !file_sec->word2) { 1570 ret = 0; 1571 break; 1572 } 1573 1574 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1575 section_size = 1576 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1577 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1578 } else { 1579 section_size = 2 * EXT_NVM_WORD2_LEN( 1580 le16_to_cpu(file_sec->word2)); 1581 section_id = EXT_NVM_WORD1_ID( 1582 le16_to_cpu(file_sec->word1)); 1583 } 1584 1585 if (section_size > max_section_size) { 1586 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1587 section_size); 1588 ret = -EINVAL; 1589 break; 1590 } 1591 1592 if (!section_size) { 1593 IWL_ERR(trans, "ERROR - section empty\n"); 1594 ret = -EINVAL; 1595 break; 1596 } 1597 1598 if (file_sec->data + section_size > eof) { 1599 IWL_ERR(trans, 1600 "ERROR - NVM file too short for section (%d bytes)\n", 1601 section_size); 1602 ret = -EINVAL; 1603 break; 1604 } 1605 1606 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1607 "Invalid NVM section ID %d\n", section_id)) { 1608 ret = -EINVAL; 1609 break; 1610 } 1611 1612 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1613 if (!temp) { 1614 ret = -ENOMEM; 1615 break; 1616 } 1617 1618 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1619 1620 kfree(nvm_sections[section_id].data); 1621 nvm_sections[section_id].data = temp; 1622 nvm_sections[section_id].length = section_size; 1623 1624 /* advance to the next section */ 1625 file_sec = (void *)(file_sec->data + section_size); 1626 } 1627 out: 1628 release_firmware(fw_entry); 1629 return ret; 1630 } 1631 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1632 1633 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1634 const struct iwl_fw *fw) 1635 { 1636 struct iwl_nvm_get_info cmd = {}; 1637 struct iwl_nvm_data *nvm; 1638 struct iwl_host_cmd hcmd = { 1639 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1640 .data = { &cmd, }, 1641 .len = { sizeof(cmd) }, 1642 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1643 }; 1644 int ret; 1645 bool empty_otp; 1646 u32 mac_flags; 1647 u32 sbands_flags = 0; 1648 /* 1649 * All the values in iwl_nvm_get_info_rsp v4 are the same as 1650 * in v3, except for the channel profile part of the 1651 * regulatory. So we can just access the new struct, with the 1652 * exception of the latter. 1653 */ 1654 struct iwl_nvm_get_info_rsp *rsp; 1655 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 1656 bool v4 = fw_has_api(&fw->ucode_capa, 1657 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 1658 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 1659 void *channel_profile; 1660 1661 ret = iwl_trans_send_cmd(trans, &hcmd); 1662 if (ret) 1663 return ERR_PTR(ret); 1664 1665 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 1666 "Invalid payload len in NVM response from FW %d", 1667 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1668 ret = -EINVAL; 1669 goto out; 1670 } 1671 1672 rsp = (void *)hcmd.resp_pkt->data; 1673 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1674 NVM_GENERAL_FLAGS_EMPTY_OTP); 1675 if (empty_otp) 1676 IWL_INFO(trans, "OTP is empty\n"); 1677 1678 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 1679 if (!nvm) { 1680 ret = -ENOMEM; 1681 goto out; 1682 } 1683 1684 iwl_set_hw_address_from_csr(trans, nvm); 1685 /* TODO: if platform NVM has MAC address - override it here */ 1686 1687 if (!is_valid_ether_addr(nvm->hw_addr)) { 1688 IWL_ERR(trans, "no valid mac address was found\n"); 1689 ret = -EINVAL; 1690 goto err_free; 1691 } 1692 1693 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1694 1695 /* Initialize general data */ 1696 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1697 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1698 if (nvm->n_hw_addrs == 0) 1699 IWL_WARN(trans, 1700 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1701 empty_otp); 1702 1703 /* Initialize MAC sku data */ 1704 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1705 nvm->sku_cap_11ac_enable = 1706 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1707 nvm->sku_cap_11n_enable = 1708 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1709 nvm->sku_cap_11ax_enable = 1710 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1711 nvm->sku_cap_band_24ghz_enable = 1712 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1713 nvm->sku_cap_band_52ghz_enable = 1714 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1715 nvm->sku_cap_mimo_disabled = 1716 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1717 1718 /* Initialize PHY sku data */ 1719 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1720 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1721 1722 if (le32_to_cpu(rsp->regulatory.lar_enabled) && 1723 fw_has_capa(&fw->ucode_capa, 1724 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) { 1725 nvm->lar_enabled = true; 1726 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1727 } 1728 1729 rsp_v3 = (void *)rsp; 1730 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 1731 (void *)rsp_v3->regulatory.channel_profile; 1732 1733 iwl_init_sbands(trans, nvm, 1734 channel_profile, 1735 nvm->valid_tx_ant & fw->valid_tx_ant, 1736 nvm->valid_rx_ant & fw->valid_rx_ant, 1737 sbands_flags, v4, fw); 1738 1739 iwl_free_resp(&hcmd); 1740 return nvm; 1741 1742 err_free: 1743 kfree(nvm); 1744 out: 1745 iwl_free_resp(&hcmd); 1746 return ERR_PTR(ret); 1747 } 1748 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1749