1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/types.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/etherdevice.h> 11 #include <linux/pci.h> 12 #include <linux/firmware.h> 13 14 #include "iwl-drv.h" 15 #include "iwl-modparams.h" 16 #include "iwl-nvm-parse.h" 17 #include "iwl-prph.h" 18 #include "iwl-io.h" 19 #include "iwl-csr.h" 20 #include "fw/acpi.h" 21 #include "fw/api/nvm-reg.h" 22 #include "fw/api/commands.h" 23 #include "fw/api/cmdhdr.h" 24 #include "fw/img.h" 25 #include "mei/iwl-mei.h" 26 27 /* NVM offsets (in words) definitions */ 28 enum nvm_offsets { 29 /* NVM HW-Section offset (in words) definitions */ 30 SUBSYSTEM_ID = 0x0A, 31 HW_ADDR = 0x15, 32 33 /* NVM SW-Section offset (in words) definitions */ 34 NVM_SW_SECTION = 0x1C0, 35 NVM_VERSION = 0, 36 RADIO_CFG = 1, 37 SKU = 2, 38 N_HW_ADDRS = 3, 39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 40 41 /* NVM calibration section offset (in words) definitions */ 42 NVM_CALIB_SECTION = 0x2B8, 43 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 44 45 /* NVM REGULATORY -Section offset (in words) definitions */ 46 NVM_CHANNELS_SDP = 0, 47 }; 48 49 enum ext_nvm_offsets { 50 /* NVM HW-Section offset (in words) definitions */ 51 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 52 53 /* NVM SW-Section offset (in words) definitions */ 54 NVM_VERSION_EXT_NVM = 0, 55 N_HW_ADDRS_FAMILY_8000 = 3, 56 57 /* NVM PHY_SKU-Section offset (in words) definitions */ 58 RADIO_CFG_FAMILY_EXT_NVM = 0, 59 SKU_FAMILY_8000 = 2, 60 61 /* NVM REGULATORY -Section offset (in words) definitions */ 62 NVM_CHANNELS_EXTENDED = 0, 63 NVM_LAR_OFFSET_OLD = 0x4C7, 64 NVM_LAR_OFFSET = 0x507, 65 NVM_LAR_ENABLED = 0x7, 66 }; 67 68 /* SKU Capabilities (actual values from NVM definition) */ 69 enum nvm_sku_bits { 70 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 71 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 72 NVM_SKU_CAP_11N_ENABLE = BIT(2), 73 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 74 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 75 }; 76 77 /* 78 * These are the channel numbers in the order that they are stored in the NVM 79 */ 80 static const u16 iwl_nvm_channels[] = { 81 /* 2.4 GHz */ 82 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 83 /* 5 GHz */ 84 36, 40, 44 , 48, 52, 56, 60, 64, 85 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 86 149, 153, 157, 161, 165 87 }; 88 89 static const u16 iwl_ext_nvm_channels[] = { 90 /* 2.4 GHz */ 91 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 92 /* 5 GHz */ 93 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 94 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 95 149, 153, 157, 161, 165, 169, 173, 177, 181 96 }; 97 98 static const u16 iwl_uhb_nvm_channels[] = { 99 /* 2.4 GHz */ 100 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 101 /* 5 GHz */ 102 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 103 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 104 149, 153, 157, 161, 165, 169, 173, 177, 181, 105 /* 6-7 GHz */ 106 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 107 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 108 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 109 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 110 }; 111 112 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 113 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 114 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 115 #define NUM_2GHZ_CHANNELS 14 116 #define NUM_5GHZ_CHANNELS 37 117 #define FIRST_2GHZ_HT_MINUS 5 118 #define LAST_2GHZ_HT_PLUS 9 119 #define N_HW_ADDR_MASK 0xF 120 121 /* rate data (static) */ 122 static struct ieee80211_rate iwl_cfg80211_rates[] = { 123 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 124 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 125 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 126 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 127 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 128 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 130 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 131 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 132 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 133 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 134 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 135 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 136 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 137 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 138 }; 139 #define RATES_24_OFFS 0 140 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 141 #define RATES_52_OFFS 4 142 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 143 144 /** 145 * enum iwl_nvm_channel_flags - channel flags in NVM 146 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 147 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 148 * @NVM_CHANNEL_ACTIVE: active scanning allowed 149 * @NVM_CHANNEL_RADAR: radar detection required 150 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 151 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 152 * on same channel on 2.4 or same UNII band on 5.2 153 * @NVM_CHANNEL_UNIFORM: uniform spreading required 154 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 155 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 156 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 157 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 158 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 159 */ 160 enum iwl_nvm_channel_flags { 161 NVM_CHANNEL_VALID = BIT(0), 162 NVM_CHANNEL_IBSS = BIT(1), 163 NVM_CHANNEL_ACTIVE = BIT(3), 164 NVM_CHANNEL_RADAR = BIT(4), 165 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 166 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 167 NVM_CHANNEL_UNIFORM = BIT(7), 168 NVM_CHANNEL_20MHZ = BIT(8), 169 NVM_CHANNEL_40MHZ = BIT(9), 170 NVM_CHANNEL_80MHZ = BIT(10), 171 NVM_CHANNEL_160MHZ = BIT(11), 172 NVM_CHANNEL_DC_HIGH = BIT(12), 173 }; 174 175 /** 176 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory 177 * domain. 178 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 179 * 2.4Ghz band is allowed. 180 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 181 * 5Ghz band is allowed. 182 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 183 * for this regulatory domain (valid only in 5Ghz). 184 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 185 * for this regulatory domain (valid only in 5Ghz). 186 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 187 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 188 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden 189 * for this regulatory domain (valid only in 5Ghz). 190 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed. 191 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 192 */ 193 enum iwl_reg_capa_flags { 194 REG_CAPA_BF_CCD_LOW_BAND = BIT(0), 195 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1), 196 REG_CAPA_160MHZ_ALLOWED = BIT(2), 197 REG_CAPA_80MHZ_ALLOWED = BIT(3), 198 REG_CAPA_MCS_8_ALLOWED = BIT(4), 199 REG_CAPA_MCS_9_ALLOWED = BIT(5), 200 REG_CAPA_40MHZ_FORBIDDEN = BIT(7), 201 REG_CAPA_DC_HIGH_ENABLED = BIT(9), 202 REG_CAPA_11AX_DISABLED = BIT(10), 203 }; 204 205 /** 206 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory 207 * domain (version 2). 208 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are 209 * disabled. 210 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 211 * 2.4Ghz band is allowed. 212 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 213 * 5Ghz band is allowed. 214 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 215 * for this regulatory domain (valid only in 5Ghz). 216 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 217 * for this regulatory domain (valid only in 5Ghz). 218 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 219 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 220 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118, 221 * 126, 122) are disabled. 222 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed 223 * for this regulatory domain (uvalid only in 5Ghz). 224 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 225 */ 226 enum iwl_reg_capa_flags_v2 { 227 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0), 228 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1), 229 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2), 230 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3), 231 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4), 232 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5), 233 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6), 234 REG_CAPA_V2_WEATHER_DISABLED = BIT(7), 235 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8), 236 REG_CAPA_V2_11AX_DISABLED = BIT(10), 237 }; 238 239 /* 240 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the 241 * MCC update command response. 242 */ 243 #define REG_CAPA_V2_RESP_VER 6 244 245 /** 246 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for 247 * handling the different APIs of reg_capa_flags. 248 * 249 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed 250 * for this regulatory domain (valid only in 5Ghz). 251 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed 252 * for this regulatory domain (valid only in 5Ghz). 253 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed 254 * for this regulatory domain (valid only in 5Ghz). 255 * @disable_11ax: 11ax is forbidden for this regulatory domain. 256 */ 257 struct iwl_reg_capa { 258 u16 allow_40mhz; 259 u16 allow_80mhz; 260 u16 allow_160mhz; 261 u16 disable_11ax; 262 }; 263 264 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 265 int chan, u32 flags) 266 { 267 #define CHECK_AND_PRINT_I(x) \ 268 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 269 270 if (!(flags & NVM_CHANNEL_VALID)) { 271 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 272 chan, flags); 273 return; 274 } 275 276 /* Note: already can print up to 101 characters, 110 is the limit! */ 277 IWL_DEBUG_DEV(dev, level, 278 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 279 chan, flags, 280 CHECK_AND_PRINT_I(VALID), 281 CHECK_AND_PRINT_I(IBSS), 282 CHECK_AND_PRINT_I(ACTIVE), 283 CHECK_AND_PRINT_I(RADAR), 284 CHECK_AND_PRINT_I(INDOOR_ONLY), 285 CHECK_AND_PRINT_I(GO_CONCURRENT), 286 CHECK_AND_PRINT_I(UNIFORM), 287 CHECK_AND_PRINT_I(20MHZ), 288 CHECK_AND_PRINT_I(40MHZ), 289 CHECK_AND_PRINT_I(80MHZ), 290 CHECK_AND_PRINT_I(160MHZ), 291 CHECK_AND_PRINT_I(DC_HIGH)); 292 #undef CHECK_AND_PRINT_I 293 } 294 295 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 296 u32 nvm_flags, const struct iwl_cfg *cfg) 297 { 298 u32 flags = IEEE80211_CHAN_NO_HT40; 299 300 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 301 if (ch_num <= LAST_2GHZ_HT_PLUS) 302 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 303 if (ch_num >= FIRST_2GHZ_HT_MINUS) 304 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 305 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 306 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 307 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 308 else 309 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 310 } 311 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 312 flags |= IEEE80211_CHAN_NO_80MHZ; 313 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 314 flags |= IEEE80211_CHAN_NO_160MHZ; 315 316 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 317 flags |= IEEE80211_CHAN_NO_IR; 318 319 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 320 flags |= IEEE80211_CHAN_NO_IR; 321 322 if (nvm_flags & NVM_CHANNEL_RADAR) 323 flags |= IEEE80211_CHAN_RADAR; 324 325 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 326 flags |= IEEE80211_CHAN_INDOOR_ONLY; 327 328 /* Set the GO concurrent flag only in case that NO_IR is set. 329 * Otherwise it is meaningless 330 */ 331 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 332 (flags & IEEE80211_CHAN_NO_IR)) 333 flags |= IEEE80211_CHAN_IR_CONCURRENT; 334 335 return flags; 336 } 337 338 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 339 { 340 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) { 341 return NL80211_BAND_6GHZ; 342 } 343 344 if (ch_idx >= NUM_2GHZ_CHANNELS) 345 return NL80211_BAND_5GHZ; 346 return NL80211_BAND_2GHZ; 347 } 348 349 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 350 struct iwl_nvm_data *data, 351 const void * const nvm_ch_flags, 352 u32 sbands_flags, bool v4) 353 { 354 int ch_idx; 355 int n_channels = 0; 356 struct ieee80211_channel *channel; 357 u32 ch_flags; 358 int num_of_ch; 359 const u16 *nvm_chan; 360 361 if (cfg->uhb_supported) { 362 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 363 nvm_chan = iwl_uhb_nvm_channels; 364 } else if (cfg->nvm_type == IWL_NVM_EXT) { 365 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 366 nvm_chan = iwl_ext_nvm_channels; 367 } else { 368 num_of_ch = IWL_NVM_NUM_CHANNELS; 369 nvm_chan = iwl_nvm_channels; 370 } 371 372 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 373 enum nl80211_band band = 374 iwl_nl80211_band_from_channel_idx(ch_idx); 375 376 if (v4) 377 ch_flags = 378 __le32_to_cpup((__le32 *)nvm_ch_flags + ch_idx); 379 else 380 ch_flags = 381 __le16_to_cpup((__le16 *)nvm_ch_flags + ch_idx); 382 383 if (band == NL80211_BAND_5GHZ && 384 !data->sku_cap_band_52ghz_enable) 385 continue; 386 387 /* workaround to disable wide channels in 5GHz */ 388 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 389 band == NL80211_BAND_5GHZ) { 390 ch_flags &= ~(NVM_CHANNEL_40MHZ | 391 NVM_CHANNEL_80MHZ | 392 NVM_CHANNEL_160MHZ); 393 } 394 395 if (ch_flags & NVM_CHANNEL_160MHZ) 396 data->vht160_supported = true; 397 398 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 399 !(ch_flags & NVM_CHANNEL_VALID)) { 400 /* 401 * Channels might become valid later if lar is 402 * supported, hence we still want to add them to 403 * the list of supported channels to cfg80211. 404 */ 405 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 406 nvm_chan[ch_idx], ch_flags); 407 continue; 408 } 409 410 channel = &data->channels[n_channels]; 411 n_channels++; 412 413 channel->hw_value = nvm_chan[ch_idx]; 414 channel->band = band; 415 channel->center_freq = 416 ieee80211_channel_to_frequency( 417 channel->hw_value, channel->band); 418 419 /* Initialize regulatory-based run-time data */ 420 421 /* 422 * Default value - highest tx power value. max_power 423 * is not used in mvm, and is used for backwards compatibility 424 */ 425 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 426 427 /* don't put limitations in case we're using LAR */ 428 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 429 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 430 ch_idx, band, 431 ch_flags, cfg); 432 else 433 channel->flags = 0; 434 435 /* TODO: Don't put limitations on UHB devices as we still don't 436 * have NVM for them 437 */ 438 if (cfg->uhb_supported) 439 channel->flags = 0; 440 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 441 channel->hw_value, ch_flags); 442 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 443 channel->hw_value, channel->max_power); 444 } 445 446 return n_channels; 447 } 448 449 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 450 struct iwl_nvm_data *data, 451 struct ieee80211_sta_vht_cap *vht_cap, 452 u8 tx_chains, u8 rx_chains) 453 { 454 const struct iwl_cfg *cfg = trans->cfg; 455 int num_rx_ants = num_of_ant(rx_chains); 456 int num_tx_ants = num_of_ant(tx_chains); 457 458 vht_cap->vht_supported = true; 459 460 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 461 IEEE80211_VHT_CAP_RXSTBC_1 | 462 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 463 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 464 IEEE80211_VHT_MAX_AMPDU_1024K << 465 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 466 467 if (data->vht160_supported) 468 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 469 IEEE80211_VHT_CAP_SHORT_GI_160; 470 471 if (cfg->vht_mu_mimo_supported) 472 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 473 474 if (cfg->ht_params->ldpc) 475 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 476 477 if (data->sku_cap_mimo_disabled) { 478 num_rx_ants = 1; 479 num_tx_ants = 1; 480 } 481 482 if (num_tx_ants > 1) 483 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 484 else 485 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 486 487 switch (iwlwifi_mod_params.amsdu_size) { 488 case IWL_AMSDU_DEF: 489 if (trans->trans_cfg->mq_rx_supported) 490 vht_cap->cap |= 491 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 492 else 493 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 494 break; 495 case IWL_AMSDU_2K: 496 if (trans->trans_cfg->mq_rx_supported) 497 vht_cap->cap |= 498 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 499 else 500 WARN(1, "RB size of 2K is not supported by this device\n"); 501 break; 502 case IWL_AMSDU_4K: 503 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 504 break; 505 case IWL_AMSDU_8K: 506 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 507 break; 508 case IWL_AMSDU_12K: 509 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 510 break; 511 default: 512 break; 513 } 514 515 vht_cap->vht_mcs.rx_mcs_map = 516 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 517 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 520 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 523 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 524 525 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 526 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 527 /* this works because NOT_SUPPORTED == 3 */ 528 vht_cap->vht_mcs.rx_mcs_map |= 529 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 530 } 531 532 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 533 534 vht_cap->vht_mcs.tx_highest |= 535 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 536 } 537 538 static const u8 iwl_vendor_caps[] = { 539 0xdd, /* vendor element */ 540 0x06, /* length */ 541 0x00, 0x17, 0x35, /* Intel OUI */ 542 0x08, /* type (Intel Capabilities) */ 543 /* followed by 16 bits of capabilities */ 544 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0) 545 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE, 546 0x00 547 }; 548 549 static const struct ieee80211_sband_iftype_data iwl_he_capa[] = { 550 { 551 .types_mask = BIT(NL80211_IFTYPE_STATION), 552 .he_cap = { 553 .has_he = true, 554 .he_cap_elem = { 555 .mac_cap_info[0] = 556 IEEE80211_HE_MAC_CAP0_HTC_HE | 557 IEEE80211_HE_MAC_CAP0_TWT_REQ, 558 .mac_cap_info[1] = 559 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 560 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 561 .mac_cap_info[2] = 562 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP, 563 .mac_cap_info[3] = 564 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 565 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS, 566 .mac_cap_info[4] = 567 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU | 568 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 569 .mac_cap_info[5] = 570 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 571 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 572 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 573 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 574 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 575 .phy_cap_info[0] = 576 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 577 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 578 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 579 .phy_cap_info[1] = 580 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 581 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 582 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 583 .phy_cap_info[2] = 584 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 585 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 586 .phy_cap_info[3] = 587 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 588 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 589 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 590 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 591 .phy_cap_info[4] = 592 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 593 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 594 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 595 .phy_cap_info[6] = 596 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 597 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB | 598 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 599 .phy_cap_info[7] = 600 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 601 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 602 .phy_cap_info[8] = 603 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 604 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 605 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 606 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 607 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 608 .phy_cap_info[9] = 609 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 610 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 611 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED, 612 .phy_cap_info[10] = 613 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF, 614 }, 615 /* 616 * Set default Tx/Rx HE MCS NSS Support field. 617 * Indicate support for up to 2 spatial streams and all 618 * MCS, without any special cases 619 */ 620 .he_mcs_nss_supp = { 621 .rx_mcs_80 = cpu_to_le16(0xfffa), 622 .tx_mcs_80 = cpu_to_le16(0xfffa), 623 .rx_mcs_160 = cpu_to_le16(0xfffa), 624 .tx_mcs_160 = cpu_to_le16(0xfffa), 625 .rx_mcs_80p80 = cpu_to_le16(0xffff), 626 .tx_mcs_80p80 = cpu_to_le16(0xffff), 627 }, 628 /* 629 * Set default PPE thresholds, with PPET16 set to 0, 630 * PPET8 set to 7 631 */ 632 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 633 }, 634 }, 635 { 636 .types_mask = BIT(NL80211_IFTYPE_AP), 637 .he_cap = { 638 .has_he = true, 639 .he_cap_elem = { 640 .mac_cap_info[0] = 641 IEEE80211_HE_MAC_CAP0_HTC_HE, 642 .mac_cap_info[1] = 643 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 644 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 645 .mac_cap_info[3] = 646 IEEE80211_HE_MAC_CAP3_OMI_CONTROL, 647 .phy_cap_info[0] = 648 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 649 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G, 650 .phy_cap_info[1] = 651 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 652 .phy_cap_info[2] = 653 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 654 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 655 .phy_cap_info[3] = 656 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM | 657 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 658 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM | 659 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 660 .phy_cap_info[6] = 661 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 662 .phy_cap_info[7] = 663 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 664 .phy_cap_info[8] = 665 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 666 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 667 .phy_cap_info[9] = 668 IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED, 669 }, 670 /* 671 * Set default Tx/Rx HE MCS NSS Support field. 672 * Indicate support for up to 2 spatial streams and all 673 * MCS, without any special cases 674 */ 675 .he_mcs_nss_supp = { 676 .rx_mcs_80 = cpu_to_le16(0xfffa), 677 .tx_mcs_80 = cpu_to_le16(0xfffa), 678 .rx_mcs_160 = cpu_to_le16(0xfffa), 679 .tx_mcs_160 = cpu_to_le16(0xfffa), 680 .rx_mcs_80p80 = cpu_to_le16(0xffff), 681 .tx_mcs_80p80 = cpu_to_le16(0xffff), 682 }, 683 /* 684 * Set default PPE thresholds, with PPET16 set to 0, 685 * PPET8 set to 7 686 */ 687 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 688 }, 689 }, 690 }; 691 692 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans, 693 struct iwl_nvm_data *data, 694 struct ieee80211_supported_band *sband, 695 u8 tx_chains, u8 rx_chains) 696 { 697 struct ieee80211_sta_ht_cap ht_cap; 698 struct ieee80211_sta_vht_cap vht_cap = {}; 699 struct ieee80211_sband_iftype_data *iftype_data; 700 u16 he_6ghz_capa = 0; 701 u32 exp; 702 int i; 703 704 if (sband->band != NL80211_BAND_6GHZ) 705 return; 706 707 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */ 708 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ, 709 tx_chains, rx_chains); 710 WARN_ON(!ht_cap.ht_supported); 711 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains); 712 WARN_ON(!vht_cap.vht_supported); 713 714 he_6ghz_capa |= 715 u16_encode_bits(ht_cap.ampdu_density, 716 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START); 717 exp = u32_get_bits(vht_cap.cap, 718 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK); 719 he_6ghz_capa |= 720 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP); 721 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK); 722 he_6ghz_capa |= 723 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 724 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */ 725 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN) 726 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS; 727 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN) 728 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 729 730 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa); 731 732 /* we know it's writable - we set it before ourselves */ 733 iftype_data = (void *)sband->iftype_data; 734 for (i = 0; i < sband->n_iftype_data; i++) 735 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa); 736 } 737 738 static void 739 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, 740 struct ieee80211_supported_band *sband, 741 struct ieee80211_sband_iftype_data *iftype_data, 742 u8 tx_chains, u8 rx_chains, 743 const struct iwl_fw *fw) 744 { 745 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP); 746 747 /* Advertise an A-MPDU exponent extension based on 748 * operating band 749 */ 750 if (sband->band != NL80211_BAND_2GHZ) 751 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 752 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1; 753 else 754 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 755 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 756 757 if (is_ap && iwlwifi_mod_params.nvm_file) 758 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 759 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 760 761 if ((tx_chains & rx_chains) == ANT_AB) { 762 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 763 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ; 764 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |= 765 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 766 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2; 767 if (!is_ap) 768 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 769 IEEE80211_HE_PHY_CAP7_MAX_NC_2; 770 } else if (!is_ap) { 771 /* If not 2x2, we need to indicate 1x1 in the 772 * Midamble RX Max NSTS - but not for AP mode 773 */ 774 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &= 775 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 776 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 777 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 778 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 779 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 780 } 781 782 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 783 case IWL_CFG_RF_TYPE_GF: 784 case IWL_CFG_RF_TYPE_MR: 785 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 786 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 787 if (!is_ap) 788 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 789 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 790 break; 791 } 792 793 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT)) 794 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |= 795 IEEE80211_HE_MAC_CAP2_BCAST_TWT; 796 797 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 798 !is_ap) { 799 iftype_data->vendor_elems.data = iwl_vendor_caps; 800 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps); 801 } 802 } 803 804 static void iwl_init_he_hw_capab(struct iwl_trans *trans, 805 struct iwl_nvm_data *data, 806 struct ieee80211_supported_band *sband, 807 u8 tx_chains, u8 rx_chains, 808 const struct iwl_fw *fw) 809 { 810 struct ieee80211_sband_iftype_data *iftype_data; 811 int i; 812 813 /* should only initialize once */ 814 if (WARN_ON(sband->iftype_data)) 815 return; 816 817 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_capa)); 818 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_capa)); 819 820 switch (sband->band) { 821 case NL80211_BAND_2GHZ: 822 iftype_data = data->iftd.low; 823 break; 824 case NL80211_BAND_5GHZ: 825 case NL80211_BAND_6GHZ: 826 iftype_data = data->iftd.high; 827 break; 828 default: 829 WARN_ON(1); 830 return; 831 } 832 833 memcpy(iftype_data, iwl_he_capa, sizeof(iwl_he_capa)); 834 835 sband->iftype_data = iftype_data; 836 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa); 837 838 for (i = 0; i < sband->n_iftype_data; i++) 839 iwl_nvm_fixup_sband_iftd(trans, sband, &iftype_data[i], 840 tx_chains, rx_chains, fw); 841 842 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains); 843 } 844 845 static void iwl_init_sbands(struct iwl_trans *trans, 846 struct iwl_nvm_data *data, 847 const void *nvm_ch_flags, u8 tx_chains, 848 u8 rx_chains, u32 sbands_flags, bool v4, 849 const struct iwl_fw *fw) 850 { 851 struct device *dev = trans->dev; 852 const struct iwl_cfg *cfg = trans->cfg; 853 int n_channels; 854 int n_used = 0; 855 struct ieee80211_supported_band *sband; 856 857 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 858 sbands_flags, v4); 859 sband = &data->bands[NL80211_BAND_2GHZ]; 860 sband->band = NL80211_BAND_2GHZ; 861 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 862 sband->n_bitrates = N_RATES_24; 863 n_used += iwl_init_sband_channels(data, sband, n_channels, 864 NL80211_BAND_2GHZ); 865 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 866 tx_chains, rx_chains); 867 868 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 869 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 870 fw); 871 872 sband = &data->bands[NL80211_BAND_5GHZ]; 873 sband->band = NL80211_BAND_5GHZ; 874 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 875 sband->n_bitrates = N_RATES_52; 876 n_used += iwl_init_sband_channels(data, sband, n_channels, 877 NL80211_BAND_5GHZ); 878 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 879 tx_chains, rx_chains); 880 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 881 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 882 tx_chains, rx_chains); 883 884 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 885 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 886 fw); 887 888 /* 6GHz band. */ 889 sband = &data->bands[NL80211_BAND_6GHZ]; 890 sband->band = NL80211_BAND_6GHZ; 891 /* use the same rates as 5GHz band */ 892 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 893 sband->n_bitrates = N_RATES_52; 894 n_used += iwl_init_sband_channels(data, sband, n_channels, 895 NL80211_BAND_6GHZ); 896 897 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 898 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 899 fw); 900 else 901 sband->n_channels = 0; 902 if (n_channels != n_used) 903 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 904 n_used, n_channels); 905 } 906 907 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 908 const __le16 *phy_sku) 909 { 910 if (cfg->nvm_type != IWL_NVM_EXT) 911 return le16_to_cpup(nvm_sw + SKU); 912 913 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 914 } 915 916 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 917 { 918 if (cfg->nvm_type != IWL_NVM_EXT) 919 return le16_to_cpup(nvm_sw + NVM_VERSION); 920 else 921 return le32_to_cpup((__le32 *)(nvm_sw + 922 NVM_VERSION_EXT_NVM)); 923 } 924 925 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 926 const __le16 *phy_sku) 927 { 928 if (cfg->nvm_type != IWL_NVM_EXT) 929 return le16_to_cpup(nvm_sw + RADIO_CFG); 930 931 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 932 933 } 934 935 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 936 { 937 int n_hw_addr; 938 939 if (cfg->nvm_type != IWL_NVM_EXT) 940 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 941 942 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 943 944 return n_hw_addr & N_HW_ADDR_MASK; 945 } 946 947 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 948 struct iwl_nvm_data *data, 949 u32 radio_cfg) 950 { 951 if (cfg->nvm_type != IWL_NVM_EXT) { 952 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 953 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 954 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 955 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 956 return; 957 } 958 959 /* set the radio configuration for family 8000 */ 960 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 961 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 962 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 963 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 964 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 965 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 966 } 967 968 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 969 { 970 const u8 *hw_addr; 971 972 hw_addr = (const u8 *)&mac_addr0; 973 dest[0] = hw_addr[3]; 974 dest[1] = hw_addr[2]; 975 dest[2] = hw_addr[1]; 976 dest[3] = hw_addr[0]; 977 978 hw_addr = (const u8 *)&mac_addr1; 979 dest[4] = hw_addr[1]; 980 dest[5] = hw_addr[0]; 981 } 982 983 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 984 struct iwl_nvm_data *data) 985 { 986 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, 987 CSR_MAC_ADDR0_STRAP(trans))); 988 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, 989 CSR_MAC_ADDR1_STRAP(trans))); 990 991 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 992 /* 993 * If the OEM fused a valid address, use it instead of the one in the 994 * OTP 995 */ 996 if (is_valid_ether_addr(data->hw_addr)) 997 return; 998 999 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); 1000 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); 1001 1002 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1003 } 1004 1005 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 1006 const struct iwl_cfg *cfg, 1007 struct iwl_nvm_data *data, 1008 const __le16 *mac_override, 1009 const __be16 *nvm_hw) 1010 { 1011 const u8 *hw_addr; 1012 1013 if (mac_override) { 1014 static const u8 reserved_mac[] = { 1015 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1016 }; 1017 1018 hw_addr = (const u8 *)(mac_override + 1019 MAC_ADDRESS_OVERRIDE_EXT_NVM); 1020 1021 /* 1022 * Store the MAC address from MAO section. 1023 * No byte swapping is required in MAO section 1024 */ 1025 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 1026 1027 /* 1028 * Force the use of the OTP MAC address in case of reserved MAC 1029 * address in the NVM, or if address is given but invalid. 1030 */ 1031 if (is_valid_ether_addr(data->hw_addr) && 1032 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 1033 return; 1034 1035 IWL_ERR(trans, 1036 "mac address from nvm override section is not valid\n"); 1037 } 1038 1039 if (nvm_hw) { 1040 /* read the mac address from WFMP registers */ 1041 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 1042 WFMP_MAC_ADDR_0)); 1043 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 1044 WFMP_MAC_ADDR_1)); 1045 1046 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1047 1048 return; 1049 } 1050 1051 IWL_ERR(trans, "mac address is not found\n"); 1052 } 1053 1054 static int iwl_set_hw_address(struct iwl_trans *trans, 1055 const struct iwl_cfg *cfg, 1056 struct iwl_nvm_data *data, const __be16 *nvm_hw, 1057 const __le16 *mac_override) 1058 { 1059 if (cfg->mac_addr_from_csr) { 1060 iwl_set_hw_address_from_csr(trans, data); 1061 } else if (cfg->nvm_type != IWL_NVM_EXT) { 1062 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 1063 1064 /* The byte order is little endian 16 bit, meaning 214365 */ 1065 data->hw_addr[0] = hw_addr[1]; 1066 data->hw_addr[1] = hw_addr[0]; 1067 data->hw_addr[2] = hw_addr[3]; 1068 data->hw_addr[3] = hw_addr[2]; 1069 data->hw_addr[4] = hw_addr[5]; 1070 data->hw_addr[5] = hw_addr[4]; 1071 } else { 1072 iwl_set_hw_address_family_8000(trans, cfg, data, 1073 mac_override, nvm_hw); 1074 } 1075 1076 if (!is_valid_ether_addr(data->hw_addr)) { 1077 IWL_ERR(trans, "no valid mac address was found\n"); 1078 return -EINVAL; 1079 } 1080 1081 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 1082 1083 return 0; 1084 } 1085 1086 static bool 1087 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1088 const __be16 *nvm_hw) 1089 { 1090 /* 1091 * Workaround a bug in Indonesia SKUs where the regulatory in 1092 * some 7000-family OTPs erroneously allow wide channels in 1093 * 5GHz. To check for Indonesia, we take the SKU value from 1094 * bits 1-4 in the subsystem ID and check if it is either 5 or 1095 * 9. In those cases, we need to force-disable wide channels 1096 * in 5GHz otherwise the FW will throw a sysassert when we try 1097 * to use them. 1098 */ 1099 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1100 /* 1101 * Unlike the other sections in the NVM, the hw 1102 * section uses big-endian. 1103 */ 1104 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 1105 u8 sku = (subsystem_id & 0x1e) >> 1; 1106 1107 if (sku == 5 || sku == 9) { 1108 IWL_DEBUG_EEPROM(trans->dev, 1109 "disabling wide channels in 5GHz (0x%0x %d)\n", 1110 subsystem_id, sku); 1111 return true; 1112 } 1113 } 1114 1115 return false; 1116 } 1117 1118 struct iwl_nvm_data * 1119 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1120 const struct iwl_mei_nvm *mei_nvm, 1121 const struct iwl_fw *fw) 1122 { 1123 struct iwl_nvm_data *data; 1124 u32 sbands_flags = 0; 1125 u8 rx_chains = fw->valid_rx_ant; 1126 u8 tx_chains = fw->valid_rx_ant; 1127 1128 if (cfg->uhb_supported) 1129 data = kzalloc(struct_size(data, channels, 1130 IWL_NVM_NUM_CHANNELS_UHB), 1131 GFP_KERNEL); 1132 else 1133 data = kzalloc(struct_size(data, channels, 1134 IWL_NVM_NUM_CHANNELS_EXT), 1135 GFP_KERNEL); 1136 if (!data) 1137 return NULL; 1138 1139 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) != 1140 IWL_NVM_NUM_CHANNELS_UHB); 1141 data->nvm_version = mei_nvm->nvm_version; 1142 1143 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg); 1144 if (data->valid_tx_ant) 1145 tx_chains &= data->valid_tx_ant; 1146 if (data->valid_rx_ant) 1147 rx_chains &= data->valid_rx_ant; 1148 1149 data->sku_cap_mimo_disabled = false; 1150 data->sku_cap_band_24ghz_enable = true; 1151 data->sku_cap_band_52ghz_enable = true; 1152 data->sku_cap_11n_enable = 1153 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL); 1154 data->sku_cap_11ac_enable = true; 1155 data->sku_cap_11ax_enable = 1156 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT; 1157 1158 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT; 1159 1160 data->n_hw_addrs = mei_nvm->n_hw_addrs; 1161 /* If no valid mac address was found - bail out */ 1162 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) { 1163 kfree(data); 1164 return NULL; 1165 } 1166 1167 if (data->lar_enabled && 1168 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1169 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1170 1171 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains, 1172 sbands_flags, true, fw); 1173 1174 return data; 1175 } 1176 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data); 1177 1178 struct iwl_nvm_data * 1179 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1180 const struct iwl_fw *fw, 1181 const __be16 *nvm_hw, const __le16 *nvm_sw, 1182 const __le16 *nvm_calib, const __le16 *regulatory, 1183 const __le16 *mac_override, const __le16 *phy_sku, 1184 u8 tx_chains, u8 rx_chains) 1185 { 1186 struct iwl_nvm_data *data; 1187 bool lar_enabled; 1188 u32 sku, radio_cfg; 1189 u32 sbands_flags = 0; 1190 u16 lar_config; 1191 const __le16 *ch_section; 1192 1193 if (cfg->uhb_supported) 1194 data = kzalloc(struct_size(data, channels, 1195 IWL_NVM_NUM_CHANNELS_UHB), 1196 GFP_KERNEL); 1197 else if (cfg->nvm_type != IWL_NVM_EXT) 1198 data = kzalloc(struct_size(data, channels, 1199 IWL_NVM_NUM_CHANNELS), 1200 GFP_KERNEL); 1201 else 1202 data = kzalloc(struct_size(data, channels, 1203 IWL_NVM_NUM_CHANNELS_EXT), 1204 GFP_KERNEL); 1205 if (!data) 1206 return NULL; 1207 1208 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 1209 1210 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 1211 iwl_set_radio_cfg(cfg, data, radio_cfg); 1212 if (data->valid_tx_ant) 1213 tx_chains &= data->valid_tx_ant; 1214 if (data->valid_rx_ant) 1215 rx_chains &= data->valid_rx_ant; 1216 1217 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 1218 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 1219 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 1220 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 1221 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1222 data->sku_cap_11n_enable = false; 1223 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 1224 (sku & NVM_SKU_CAP_11AC_ENABLE); 1225 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 1226 1227 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 1228 1229 if (cfg->nvm_type != IWL_NVM_EXT) { 1230 /* Checking for required sections */ 1231 if (!nvm_calib) { 1232 IWL_ERR(trans, 1233 "Can't parse empty Calib NVM sections\n"); 1234 kfree(data); 1235 return NULL; 1236 } 1237 1238 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1239 ®ulatory[NVM_CHANNELS_SDP] : 1240 &nvm_sw[NVM_CHANNELS]; 1241 1242 /* in family 8000 Xtal calibration values moved to OTP */ 1243 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 1244 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 1245 lar_enabled = true; 1246 } else { 1247 u16 lar_offset = data->nvm_version < 0xE39 ? 1248 NVM_LAR_OFFSET_OLD : 1249 NVM_LAR_OFFSET; 1250 1251 lar_config = le16_to_cpup(regulatory + lar_offset); 1252 data->lar_enabled = !!(lar_config & 1253 NVM_LAR_ENABLED); 1254 lar_enabled = data->lar_enabled; 1255 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1256 } 1257 1258 /* If no valid mac address was found - bail out */ 1259 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1260 kfree(data); 1261 return NULL; 1262 } 1263 1264 if (lar_enabled && 1265 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1266 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1267 1268 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1269 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1270 1271 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1272 sbands_flags, false, fw); 1273 data->calib_version = 255; 1274 1275 return data; 1276 } 1277 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1278 1279 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1280 int ch_idx, u16 nvm_flags, 1281 struct iwl_reg_capa reg_capa, 1282 const struct iwl_cfg *cfg) 1283 { 1284 u32 flags = NL80211_RRF_NO_HT40; 1285 1286 if (ch_idx < NUM_2GHZ_CHANNELS && 1287 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1288 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1289 flags &= ~NL80211_RRF_NO_HT40PLUS; 1290 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1291 flags &= ~NL80211_RRF_NO_HT40MINUS; 1292 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1293 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1294 flags &= ~NL80211_RRF_NO_HT40PLUS; 1295 else 1296 flags &= ~NL80211_RRF_NO_HT40MINUS; 1297 } 1298 1299 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1300 flags |= NL80211_RRF_NO_80MHZ; 1301 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1302 flags |= NL80211_RRF_NO_160MHZ; 1303 1304 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1305 flags |= NL80211_RRF_NO_IR; 1306 1307 if (nvm_flags & NVM_CHANNEL_RADAR) 1308 flags |= NL80211_RRF_DFS; 1309 1310 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1311 flags |= NL80211_RRF_NO_OUTDOOR; 1312 1313 /* Set the GO concurrent flag only in case that NO_IR is set. 1314 * Otherwise it is meaningless 1315 */ 1316 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1317 (flags & NL80211_RRF_NO_IR)) 1318 flags |= NL80211_RRF_GO_CONCURRENT; 1319 1320 /* 1321 * reg_capa is per regulatory domain so apply it for every channel 1322 */ 1323 if (ch_idx >= NUM_2GHZ_CHANNELS) { 1324 if (!reg_capa.allow_40mhz) 1325 flags |= NL80211_RRF_NO_HT40; 1326 1327 if (!reg_capa.allow_80mhz) 1328 flags |= NL80211_RRF_NO_80MHZ; 1329 1330 if (!reg_capa.allow_160mhz) 1331 flags |= NL80211_RRF_NO_160MHZ; 1332 } 1333 if (reg_capa.disable_11ax) 1334 flags |= NL80211_RRF_NO_HE; 1335 1336 return flags; 1337 } 1338 1339 static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver) 1340 { 1341 struct iwl_reg_capa reg_capa; 1342 1343 if (resp_ver >= REG_CAPA_V2_RESP_VER) { 1344 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED; 1345 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED; 1346 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED; 1347 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED; 1348 } else { 1349 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN); 1350 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED; 1351 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED; 1352 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED; 1353 } 1354 return reg_capa; 1355 } 1356 1357 struct ieee80211_regdomain * 1358 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1359 int num_of_ch, __le32 *channels, u16 fw_mcc, 1360 u16 geo_info, u16 cap, u8 resp_ver) 1361 { 1362 int ch_idx; 1363 u16 ch_flags; 1364 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1365 const u16 *nvm_chan; 1366 struct ieee80211_regdomain *regd, *copy_rd; 1367 struct ieee80211_reg_rule *rule; 1368 enum nl80211_band band; 1369 int center_freq, prev_center_freq = 0; 1370 int valid_rules = 0; 1371 bool new_rule; 1372 int max_num_ch; 1373 struct iwl_reg_capa reg_capa; 1374 1375 if (cfg->uhb_supported) { 1376 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1377 nvm_chan = iwl_uhb_nvm_channels; 1378 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1379 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1380 nvm_chan = iwl_ext_nvm_channels; 1381 } else { 1382 max_num_ch = IWL_NVM_NUM_CHANNELS; 1383 nvm_chan = iwl_nvm_channels; 1384 } 1385 1386 if (WARN_ON(num_of_ch > max_num_ch)) 1387 num_of_ch = max_num_ch; 1388 1389 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1390 return ERR_PTR(-EINVAL); 1391 1392 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1393 num_of_ch); 1394 1395 /* build a regdomain rule for every valid channel */ 1396 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1397 if (!regd) 1398 return ERR_PTR(-ENOMEM); 1399 1400 /* set alpha2 from FW. */ 1401 regd->alpha2[0] = fw_mcc >> 8; 1402 regd->alpha2[1] = fw_mcc & 0xff; 1403 1404 /* parse regulatory capability flags */ 1405 reg_capa = iwl_get_reg_capa(cap, resp_ver); 1406 1407 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1408 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1409 band = iwl_nl80211_band_from_channel_idx(ch_idx); 1410 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1411 band); 1412 new_rule = false; 1413 1414 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1415 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1416 nvm_chan[ch_idx], ch_flags); 1417 continue; 1418 } 1419 1420 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1421 ch_flags, reg_capa, 1422 cfg); 1423 1424 /* we can't continue the same rule */ 1425 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1426 center_freq - prev_center_freq > 20) { 1427 valid_rules++; 1428 new_rule = true; 1429 } 1430 1431 rule = ®d->reg_rules[valid_rules - 1]; 1432 1433 if (new_rule) 1434 rule->freq_range.start_freq_khz = 1435 MHZ_TO_KHZ(center_freq - 10); 1436 1437 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1438 1439 /* this doesn't matter - not used by FW */ 1440 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1441 rule->power_rule.max_eirp = 1442 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1443 1444 rule->flags = reg_rule_flags; 1445 1446 /* rely on auto-calculation to merge BW of contiguous chans */ 1447 rule->flags |= NL80211_RRF_AUTO_BW; 1448 rule->freq_range.max_bandwidth_khz = 0; 1449 1450 prev_center_freq = center_freq; 1451 prev_reg_rule_flags = reg_rule_flags; 1452 1453 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1454 nvm_chan[ch_idx], ch_flags); 1455 1456 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1457 band == NL80211_BAND_2GHZ) 1458 continue; 1459 1460 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1461 } 1462 1463 /* 1464 * Certain firmware versions might report no valid channels 1465 * if booted in RF-kill, i.e. not all calibrations etc. are 1466 * running. We'll get out of this situation later when the 1467 * rfkill is removed and we update the regdomain again, but 1468 * since cfg80211 doesn't accept an empty regdomain, add a 1469 * dummy (unusable) rule here in this case so we can init. 1470 */ 1471 if (!valid_rules) { 1472 valid_rules = 1; 1473 rule = ®d->reg_rules[valid_rules - 1]; 1474 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412); 1475 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413); 1476 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1); 1477 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1478 rule->power_rule.max_eirp = 1479 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1480 } 1481 1482 regd->n_reg_rules = valid_rules; 1483 1484 /* 1485 * Narrow down regdom for unused regulatory rules to prevent hole 1486 * between reg rules to wmm rules. 1487 */ 1488 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1489 GFP_KERNEL); 1490 if (!copy_rd) 1491 copy_rd = ERR_PTR(-ENOMEM); 1492 1493 kfree(regd); 1494 return copy_rd; 1495 } 1496 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1497 1498 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1499 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1500 #define MAX_NVM_FILE_LEN 16384 1501 1502 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1503 unsigned int len) 1504 { 1505 #define IWL_4165_DEVICE_ID 0x5501 1506 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1507 1508 if (section == NVM_SECTION_TYPE_PHY_SKU && 1509 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1510 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1511 /* OTP 0x52 bug work around: it's a 1x1 device */ 1512 data[3] = ANT_B | (ANT_B << 4); 1513 } 1514 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1515 1516 /* 1517 * Reads external NVM from a file into mvm->nvm_sections 1518 * 1519 * HOW TO CREATE THE NVM FILE FORMAT: 1520 * ------------------------------ 1521 * 1. create hex file, format: 1522 * 3800 -> header 1523 * 0000 -> header 1524 * 5a40 -> data 1525 * 1526 * rev - 6 bit (word1) 1527 * len - 10 bit (word1) 1528 * id - 4 bit (word2) 1529 * rsv - 12 bit (word2) 1530 * 1531 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1532 * 1533 * 3. create binary file from the hex file 1534 * 1535 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1536 */ 1537 int iwl_read_external_nvm(struct iwl_trans *trans, 1538 const char *nvm_file_name, 1539 struct iwl_nvm_section *nvm_sections) 1540 { 1541 int ret, section_size; 1542 u16 section_id; 1543 const struct firmware *fw_entry; 1544 const struct { 1545 __le16 word1; 1546 __le16 word2; 1547 u8 data[]; 1548 } *file_sec; 1549 const u8 *eof; 1550 u8 *temp; 1551 int max_section_size; 1552 const __le32 *dword_buff; 1553 1554 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1555 #define NVM_WORD2_ID(x) (x >> 12) 1556 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1557 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1558 #define NVM_HEADER_0 (0x2A504C54) 1559 #define NVM_HEADER_1 (0x4E564D2A) 1560 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1561 1562 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1563 1564 /* Maximal size depends on NVM version */ 1565 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1566 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1567 else 1568 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1569 1570 /* 1571 * Obtain NVM image via request_firmware. Since we already used 1572 * request_firmware_nowait() for the firmware binary load and only 1573 * get here after that we assume the NVM request can be satisfied 1574 * synchronously. 1575 */ 1576 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1577 if (ret) { 1578 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1579 nvm_file_name, ret); 1580 return ret; 1581 } 1582 1583 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1584 nvm_file_name, fw_entry->size); 1585 1586 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1587 IWL_ERR(trans, "NVM file too large\n"); 1588 ret = -EINVAL; 1589 goto out; 1590 } 1591 1592 eof = fw_entry->data + fw_entry->size; 1593 dword_buff = (__le32 *)fw_entry->data; 1594 1595 /* some NVM file will contain a header. 1596 * The header is identified by 2 dwords header as follow: 1597 * dword[0] = 0x2A504C54 1598 * dword[1] = 0x4E564D2A 1599 * 1600 * This header must be skipped when providing the NVM data to the FW. 1601 */ 1602 if (fw_entry->size > NVM_HEADER_SIZE && 1603 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1604 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1605 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1606 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1607 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1608 le32_to_cpu(dword_buff[3])); 1609 1610 /* nvm file validation, dword_buff[2] holds the file version */ 1611 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1612 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP && 1613 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1614 ret = -EFAULT; 1615 goto out; 1616 } 1617 } else { 1618 file_sec = (void *)fw_entry->data; 1619 } 1620 1621 while (true) { 1622 if (file_sec->data > eof) { 1623 IWL_ERR(trans, 1624 "ERROR - NVM file too short for section header\n"); 1625 ret = -EINVAL; 1626 break; 1627 } 1628 1629 /* check for EOF marker */ 1630 if (!file_sec->word1 && !file_sec->word2) { 1631 ret = 0; 1632 break; 1633 } 1634 1635 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1636 section_size = 1637 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1638 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1639 } else { 1640 section_size = 2 * EXT_NVM_WORD2_LEN( 1641 le16_to_cpu(file_sec->word2)); 1642 section_id = EXT_NVM_WORD1_ID( 1643 le16_to_cpu(file_sec->word1)); 1644 } 1645 1646 if (section_size > max_section_size) { 1647 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1648 section_size); 1649 ret = -EINVAL; 1650 break; 1651 } 1652 1653 if (!section_size) { 1654 IWL_ERR(trans, "ERROR - section empty\n"); 1655 ret = -EINVAL; 1656 break; 1657 } 1658 1659 if (file_sec->data + section_size > eof) { 1660 IWL_ERR(trans, 1661 "ERROR - NVM file too short for section (%d bytes)\n", 1662 section_size); 1663 ret = -EINVAL; 1664 break; 1665 } 1666 1667 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1668 "Invalid NVM section ID %d\n", section_id)) { 1669 ret = -EINVAL; 1670 break; 1671 } 1672 1673 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1674 if (!temp) { 1675 ret = -ENOMEM; 1676 break; 1677 } 1678 1679 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1680 1681 kfree(nvm_sections[section_id].data); 1682 nvm_sections[section_id].data = temp; 1683 nvm_sections[section_id].length = section_size; 1684 1685 /* advance to the next section */ 1686 file_sec = (void *)(file_sec->data + section_size); 1687 } 1688 out: 1689 release_firmware(fw_entry); 1690 return ret; 1691 } 1692 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1693 1694 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1695 const struct iwl_fw *fw) 1696 { 1697 struct iwl_nvm_get_info cmd = {}; 1698 struct iwl_nvm_data *nvm; 1699 struct iwl_host_cmd hcmd = { 1700 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1701 .data = { &cmd, }, 1702 .len = { sizeof(cmd) }, 1703 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1704 }; 1705 int ret; 1706 bool empty_otp; 1707 u32 mac_flags; 1708 u32 sbands_flags = 0; 1709 /* 1710 * All the values in iwl_nvm_get_info_rsp v4 are the same as 1711 * in v3, except for the channel profile part of the 1712 * regulatory. So we can just access the new struct, with the 1713 * exception of the latter. 1714 */ 1715 struct iwl_nvm_get_info_rsp *rsp; 1716 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 1717 bool v4 = fw_has_api(&fw->ucode_capa, 1718 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 1719 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 1720 void *channel_profile; 1721 1722 ret = iwl_trans_send_cmd(trans, &hcmd); 1723 if (ret) 1724 return ERR_PTR(ret); 1725 1726 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 1727 "Invalid payload len in NVM response from FW %d", 1728 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1729 ret = -EINVAL; 1730 goto out; 1731 } 1732 1733 rsp = (void *)hcmd.resp_pkt->data; 1734 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1735 NVM_GENERAL_FLAGS_EMPTY_OTP); 1736 if (empty_otp) 1737 IWL_INFO(trans, "OTP is empty\n"); 1738 1739 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 1740 if (!nvm) { 1741 ret = -ENOMEM; 1742 goto out; 1743 } 1744 1745 iwl_set_hw_address_from_csr(trans, nvm); 1746 /* TODO: if platform NVM has MAC address - override it here */ 1747 1748 if (!is_valid_ether_addr(nvm->hw_addr)) { 1749 IWL_ERR(trans, "no valid mac address was found\n"); 1750 ret = -EINVAL; 1751 goto err_free; 1752 } 1753 1754 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1755 1756 /* Initialize general data */ 1757 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1758 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1759 if (nvm->n_hw_addrs == 0) 1760 IWL_WARN(trans, 1761 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1762 empty_otp); 1763 1764 /* Initialize MAC sku data */ 1765 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1766 nvm->sku_cap_11ac_enable = 1767 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1768 nvm->sku_cap_11n_enable = 1769 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1770 nvm->sku_cap_11ax_enable = 1771 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1772 nvm->sku_cap_band_24ghz_enable = 1773 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1774 nvm->sku_cap_band_52ghz_enable = 1775 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1776 nvm->sku_cap_mimo_disabled = 1777 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1778 1779 /* Initialize PHY sku data */ 1780 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1781 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1782 1783 if (le32_to_cpu(rsp->regulatory.lar_enabled) && 1784 fw_has_capa(&fw->ucode_capa, 1785 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) { 1786 nvm->lar_enabled = true; 1787 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1788 } 1789 1790 rsp_v3 = (void *)rsp; 1791 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 1792 (void *)rsp_v3->regulatory.channel_profile; 1793 1794 iwl_init_sbands(trans, nvm, 1795 channel_profile, 1796 nvm->valid_tx_ant & fw->valid_tx_ant, 1797 nvm->valid_rx_ant & fw->valid_rx_ant, 1798 sbands_flags, v4, fw); 1799 1800 iwl_free_resp(&hcmd); 1801 return nvm; 1802 1803 err_free: 1804 kfree(nvm); 1805 out: 1806 iwl_free_resp(&hcmd); 1807 return ERR_PTR(ret); 1808 } 1809 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1810