1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 *****************************************************************************/ 63 #include <linux/types.h> 64 #include <linux/slab.h> 65 #include <linux/export.h> 66 #include <linux/etherdevice.h> 67 #include <linux/pci.h> 68 #include <linux/firmware.h> 69 70 #include "iwl-drv.h" 71 #include "iwl-modparams.h" 72 #include "iwl-nvm-parse.h" 73 #include "iwl-prph.h" 74 #include "iwl-io.h" 75 #include "iwl-csr.h" 76 #include "fw/acpi.h" 77 #include "fw/api/nvm-reg.h" 78 #include "fw/api/commands.h" 79 #include "fw/api/cmdhdr.h" 80 #include "fw/img.h" 81 82 /* NVM offsets (in words) definitions */ 83 enum nvm_offsets { 84 /* NVM HW-Section offset (in words) definitions */ 85 SUBSYSTEM_ID = 0x0A, 86 HW_ADDR = 0x15, 87 88 /* NVM SW-Section offset (in words) definitions */ 89 NVM_SW_SECTION = 0x1C0, 90 NVM_VERSION = 0, 91 RADIO_CFG = 1, 92 SKU = 2, 93 N_HW_ADDRS = 3, 94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 95 96 /* NVM calibration section offset (in words) definitions */ 97 NVM_CALIB_SECTION = 0x2B8, 98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 99 100 /* NVM REGULATORY -Section offset (in words) definitions */ 101 NVM_CHANNELS_SDP = 0, 102 }; 103 104 enum ext_nvm_offsets { 105 /* NVM HW-Section offset (in words) definitions */ 106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 107 108 /* NVM SW-Section offset (in words) definitions */ 109 NVM_VERSION_EXT_NVM = 0, 110 RADIO_CFG_FAMILY_EXT_NVM = 0, 111 SKU_FAMILY_8000 = 2, 112 N_HW_ADDRS_FAMILY_8000 = 3, 113 114 /* NVM REGULATORY -Section offset (in words) definitions */ 115 NVM_CHANNELS_EXTENDED = 0, 116 NVM_LAR_OFFSET_OLD = 0x4C7, 117 NVM_LAR_OFFSET = 0x507, 118 NVM_LAR_ENABLED = 0x7, 119 }; 120 121 /* SKU Capabilities (actual values from NVM definition) */ 122 enum nvm_sku_bits { 123 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 124 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 125 NVM_SKU_CAP_11N_ENABLE = BIT(2), 126 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 128 }; 129 130 /* 131 * These are the channel numbers in the order that they are stored in the NVM 132 */ 133 static const u8 iwl_nvm_channels[] = { 134 /* 2.4 GHz */ 135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 136 /* 5 GHz */ 137 36, 40, 44 , 48, 52, 56, 60, 64, 138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 139 149, 153, 157, 161, 165 140 }; 141 142 static const u8 iwl_ext_nvm_channels[] = { 143 /* 2.4 GHz */ 144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 145 /* 5 GHz */ 146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148 149, 153, 157, 161, 165, 169, 173, 177, 181 149 }; 150 151 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 152 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 153 #define NUM_2GHZ_CHANNELS 14 154 #define NUM_2GHZ_CHANNELS_EXT 14 155 #define FIRST_2GHZ_HT_MINUS 5 156 #define LAST_2GHZ_HT_PLUS 9 157 #define LAST_5GHZ_HT 165 158 #define LAST_5GHZ_HT_FAMILY_8000 181 159 #define N_HW_ADDR_MASK 0xF 160 161 /* rate data (static) */ 162 static struct ieee80211_rate iwl_cfg80211_rates[] = { 163 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 164 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 165 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 166 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 167 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 168 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 169 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 170 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 171 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 172 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 173 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 174 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 175 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 176 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 177 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 178 }; 179 #define RATES_24_OFFS 0 180 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 181 #define RATES_52_OFFS 4 182 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 183 184 /** 185 * enum iwl_nvm_channel_flags - channel flags in NVM 186 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 187 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 188 * @NVM_CHANNEL_ACTIVE: active scanning allowed 189 * @NVM_CHANNEL_RADAR: radar detection required 190 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 191 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 192 * on same channel on 2.4 or same UNII band on 5.2 193 * @NVM_CHANNEL_UNIFORM: uniform spreading required 194 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 195 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 196 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 197 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 198 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 199 */ 200 enum iwl_nvm_channel_flags { 201 NVM_CHANNEL_VALID = BIT(0), 202 NVM_CHANNEL_IBSS = BIT(1), 203 NVM_CHANNEL_ACTIVE = BIT(3), 204 NVM_CHANNEL_RADAR = BIT(4), 205 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 206 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 207 NVM_CHANNEL_UNIFORM = BIT(7), 208 NVM_CHANNEL_20MHZ = BIT(8), 209 NVM_CHANNEL_40MHZ = BIT(9), 210 NVM_CHANNEL_80MHZ = BIT(10), 211 NVM_CHANNEL_160MHZ = BIT(11), 212 NVM_CHANNEL_DC_HIGH = BIT(12), 213 }; 214 215 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 216 int chan, u16 flags) 217 { 218 #define CHECK_AND_PRINT_I(x) \ 219 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 220 221 if (!(flags & NVM_CHANNEL_VALID)) { 222 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 223 chan, flags); 224 return; 225 } 226 227 /* Note: already can print up to 101 characters, 110 is the limit! */ 228 IWL_DEBUG_DEV(dev, level, 229 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 230 chan, flags, 231 CHECK_AND_PRINT_I(VALID), 232 CHECK_AND_PRINT_I(IBSS), 233 CHECK_AND_PRINT_I(ACTIVE), 234 CHECK_AND_PRINT_I(RADAR), 235 CHECK_AND_PRINT_I(INDOOR_ONLY), 236 CHECK_AND_PRINT_I(GO_CONCURRENT), 237 CHECK_AND_PRINT_I(UNIFORM), 238 CHECK_AND_PRINT_I(20MHZ), 239 CHECK_AND_PRINT_I(40MHZ), 240 CHECK_AND_PRINT_I(80MHZ), 241 CHECK_AND_PRINT_I(160MHZ), 242 CHECK_AND_PRINT_I(DC_HIGH)); 243 #undef CHECK_AND_PRINT_I 244 } 245 246 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz, 247 u16 nvm_flags, const struct iwl_cfg *cfg) 248 { 249 u32 flags = IEEE80211_CHAN_NO_HT40; 250 u32 last_5ghz_ht = LAST_5GHZ_HT; 251 252 if (cfg->nvm_type == IWL_NVM_EXT) 253 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 254 255 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) { 256 if (ch_num <= LAST_2GHZ_HT_PLUS) 257 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 258 if (ch_num >= FIRST_2GHZ_HT_MINUS) 259 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 260 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) { 261 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 262 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 263 else 264 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 265 } 266 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 267 flags |= IEEE80211_CHAN_NO_80MHZ; 268 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 269 flags |= IEEE80211_CHAN_NO_160MHZ; 270 271 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 272 flags |= IEEE80211_CHAN_NO_IR; 273 274 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 275 flags |= IEEE80211_CHAN_NO_IR; 276 277 if (nvm_flags & NVM_CHANNEL_RADAR) 278 flags |= IEEE80211_CHAN_RADAR; 279 280 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 281 flags |= IEEE80211_CHAN_INDOOR_ONLY; 282 283 /* Set the GO concurrent flag only in case that NO_IR is set. 284 * Otherwise it is meaningless 285 */ 286 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 287 (flags & IEEE80211_CHAN_NO_IR)) 288 flags |= IEEE80211_CHAN_IR_CONCURRENT; 289 290 return flags; 291 } 292 293 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 294 struct iwl_nvm_data *data, 295 const __le16 * const nvm_ch_flags, 296 u32 sbands_flags) 297 { 298 int ch_idx; 299 int n_channels = 0; 300 struct ieee80211_channel *channel; 301 u16 ch_flags; 302 int num_of_ch, num_2ghz_channels; 303 const u8 *nvm_chan; 304 305 if (cfg->nvm_type != IWL_NVM_EXT) { 306 num_of_ch = IWL_NVM_NUM_CHANNELS; 307 nvm_chan = &iwl_nvm_channels[0]; 308 num_2ghz_channels = NUM_2GHZ_CHANNELS; 309 } else { 310 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 311 nvm_chan = &iwl_ext_nvm_channels[0]; 312 num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT; 313 } 314 315 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 316 bool is_5ghz = (ch_idx >= num_2ghz_channels); 317 318 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx); 319 320 if (is_5ghz && !data->sku_cap_band_52ghz_enable) 321 continue; 322 323 /* workaround to disable wide channels in 5GHz */ 324 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 325 is_5ghz) { 326 ch_flags &= ~(NVM_CHANNEL_40MHZ | 327 NVM_CHANNEL_80MHZ | 328 NVM_CHANNEL_160MHZ); 329 } 330 331 if (ch_flags & NVM_CHANNEL_160MHZ) 332 data->vht160_supported = true; 333 334 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 335 !(ch_flags & NVM_CHANNEL_VALID)) { 336 /* 337 * Channels might become valid later if lar is 338 * supported, hence we still want to add them to 339 * the list of supported channels to cfg80211. 340 */ 341 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 342 nvm_chan[ch_idx], ch_flags); 343 continue; 344 } 345 346 channel = &data->channels[n_channels]; 347 n_channels++; 348 349 channel->hw_value = nvm_chan[ch_idx]; 350 channel->band = is_5ghz ? 351 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ; 352 channel->center_freq = 353 ieee80211_channel_to_frequency( 354 channel->hw_value, channel->band); 355 356 /* Initialize regulatory-based run-time data */ 357 358 /* 359 * Default value - highest tx power value. max_power 360 * is not used in mvm, and is used for backwards compatibility 361 */ 362 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 363 364 /* don't put limitations in case we're using LAR */ 365 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 366 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 367 ch_idx, is_5ghz, 368 ch_flags, cfg); 369 else 370 channel->flags = 0; 371 372 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 373 channel->hw_value, ch_flags); 374 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 375 channel->hw_value, channel->max_power); 376 } 377 378 return n_channels; 379 } 380 381 static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg, 382 struct iwl_nvm_data *data, 383 struct ieee80211_sta_vht_cap *vht_cap, 384 u8 tx_chains, u8 rx_chains) 385 { 386 int num_rx_ants = num_of_ant(rx_chains); 387 int num_tx_ants = num_of_ant(tx_chains); 388 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?: 389 IEEE80211_VHT_MAX_AMPDU_1024K); 390 391 vht_cap->vht_supported = true; 392 393 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 394 IEEE80211_VHT_CAP_RXSTBC_1 | 395 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 396 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 397 max_ampdu_exponent << 398 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 399 400 if (data->vht160_supported) 401 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 402 IEEE80211_VHT_CAP_SHORT_GI_160; 403 404 if (cfg->vht_mu_mimo_supported) 405 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 406 407 if (cfg->ht_params->ldpc) 408 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 409 410 if (data->sku_cap_mimo_disabled) { 411 num_rx_ants = 1; 412 num_tx_ants = 1; 413 } 414 415 if (num_tx_ants > 1) 416 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 417 else 418 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 419 420 switch (iwlwifi_mod_params.amsdu_size) { 421 case IWL_AMSDU_DEF: 422 if (cfg->mq_rx_supported) 423 vht_cap->cap |= 424 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 425 else 426 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 427 break; 428 case IWL_AMSDU_2K: 429 if (cfg->mq_rx_supported) 430 vht_cap->cap |= 431 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 432 else 433 WARN(1, "RB size of 2K is not supported by this device\n"); 434 break; 435 case IWL_AMSDU_4K: 436 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 437 break; 438 case IWL_AMSDU_8K: 439 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 440 break; 441 case IWL_AMSDU_12K: 442 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 443 break; 444 default: 445 break; 446 } 447 448 vht_cap->vht_mcs.rx_mcs_map = 449 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 450 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 451 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 452 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 453 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 454 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 455 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 456 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 457 458 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 459 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 460 /* this works because NOT_SUPPORTED == 3 */ 461 vht_cap->vht_mcs.rx_mcs_map |= 462 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 463 } 464 465 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 466 } 467 468 static struct ieee80211_sband_iftype_data iwl_he_capa = { 469 .types_mask = BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP), 470 .he_cap = { 471 .has_he = true, 472 .he_cap_elem = { 473 .mac_cap_info[0] = 474 IEEE80211_HE_MAC_CAP0_HTC_HE | 475 IEEE80211_HE_MAC_CAP0_TWT_REQ, 476 .mac_cap_info[1] = 477 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 478 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 479 .mac_cap_info[2] = 480 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP | 481 IEEE80211_HE_MAC_CAP2_MU_CASCADING | 482 IEEE80211_HE_MAC_CAP2_ACK_EN, 483 .mac_cap_info[3] = 484 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 485 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 486 .mac_cap_info[4] = 487 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU | 488 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 489 .mac_cap_info[5] = 490 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 491 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 492 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU, 493 .phy_cap_info[0] = 494 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 495 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 496 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 497 .phy_cap_info[1] = 498 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 499 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 500 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 501 IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS, 502 .phy_cap_info[2] = 503 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 504 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 505 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 506 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 507 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO, 508 .phy_cap_info[3] = 509 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 510 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 511 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 512 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 513 .phy_cap_info[4] = 514 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 515 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 516 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 517 .phy_cap_info[5] = 518 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 519 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2 | 520 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 521 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK, 522 .phy_cap_info[6] = 523 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 524 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 525 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB | 526 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB | 527 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 528 IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO | 529 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 530 .phy_cap_info[7] = 531 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR | 532 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 533 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 534 .phy_cap_info[8] = 535 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 536 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 537 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 538 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 539 IEEE80211_HE_PHY_CAP8_DCM_MAX_BW_160_OR_80P80_MHZ, 540 .phy_cap_info[9] = 541 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 542 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 543 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB, 544 }, 545 /* 546 * Set default Tx/Rx HE MCS NSS Support field. Indicate support 547 * for up to 2 spatial streams and all MCS, without any special 548 * cases 549 */ 550 .he_mcs_nss_supp = { 551 .rx_mcs_80 = cpu_to_le16(0xfffa), 552 .tx_mcs_80 = cpu_to_le16(0xfffa), 553 .rx_mcs_160 = cpu_to_le16(0xfffa), 554 .tx_mcs_160 = cpu_to_le16(0xfffa), 555 .rx_mcs_80p80 = cpu_to_le16(0xffff), 556 .tx_mcs_80p80 = cpu_to_le16(0xffff), 557 }, 558 /* 559 * Set default PPE thresholds, with PPET16 set to 0, PPET8 set 560 * to 7 561 */ 562 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 563 }, 564 }; 565 566 static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband, 567 u8 tx_chains, u8 rx_chains) 568 { 569 if (sband->band == NL80211_BAND_2GHZ || 570 sband->band == NL80211_BAND_5GHZ) 571 sband->iftype_data = &iwl_he_capa; 572 else 573 return; 574 575 sband->n_iftype_data = 1; 576 577 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */ 578 if ((tx_chains & rx_chains) != ANT_AB) { 579 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[1] &= 580 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 581 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[2] &= 582 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 583 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[7] &= 584 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 585 } 586 } 587 588 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg, 589 struct iwl_nvm_data *data, 590 const __le16 *nvm_ch_flags, u8 tx_chains, 591 u8 rx_chains, u32 sbands_flags) 592 { 593 int n_channels; 594 int n_used = 0; 595 struct ieee80211_supported_band *sband; 596 597 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 598 sbands_flags); 599 sband = &data->bands[NL80211_BAND_2GHZ]; 600 sband->band = NL80211_BAND_2GHZ; 601 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 602 sband->n_bitrates = N_RATES_24; 603 n_used += iwl_init_sband_channels(data, sband, n_channels, 604 NL80211_BAND_2GHZ); 605 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ, 606 tx_chains, rx_chains); 607 608 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 609 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 610 611 sband = &data->bands[NL80211_BAND_5GHZ]; 612 sband->band = NL80211_BAND_5GHZ; 613 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 614 sband->n_bitrates = N_RATES_52; 615 n_used += iwl_init_sband_channels(data, sband, n_channels, 616 NL80211_BAND_5GHZ); 617 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ, 618 tx_chains, rx_chains); 619 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 620 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap, 621 tx_chains, rx_chains); 622 623 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 624 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 625 626 if (n_channels != n_used) 627 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 628 n_used, n_channels); 629 } 630 631 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 632 const __le16 *phy_sku) 633 { 634 if (cfg->nvm_type != IWL_NVM_EXT) 635 return le16_to_cpup(nvm_sw + SKU); 636 637 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 638 } 639 640 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 641 { 642 if (cfg->nvm_type != IWL_NVM_EXT) 643 return le16_to_cpup(nvm_sw + NVM_VERSION); 644 else 645 return le32_to_cpup((__le32 *)(nvm_sw + 646 NVM_VERSION_EXT_NVM)); 647 } 648 649 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 650 const __le16 *phy_sku) 651 { 652 if (cfg->nvm_type != IWL_NVM_EXT) 653 return le16_to_cpup(nvm_sw + RADIO_CFG); 654 655 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 656 657 } 658 659 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 660 { 661 int n_hw_addr; 662 663 if (cfg->nvm_type != IWL_NVM_EXT) 664 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 665 666 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 667 668 return n_hw_addr & N_HW_ADDR_MASK; 669 } 670 671 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 672 struct iwl_nvm_data *data, 673 u32 radio_cfg) 674 { 675 if (cfg->nvm_type != IWL_NVM_EXT) { 676 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 677 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 678 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 679 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 680 return; 681 } 682 683 /* set the radio configuration for family 8000 */ 684 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 685 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 686 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 687 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 688 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 689 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 690 } 691 692 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 693 { 694 const u8 *hw_addr; 695 696 hw_addr = (const u8 *)&mac_addr0; 697 dest[0] = hw_addr[3]; 698 dest[1] = hw_addr[2]; 699 dest[2] = hw_addr[1]; 700 dest[3] = hw_addr[0]; 701 702 hw_addr = (const u8 *)&mac_addr1; 703 dest[4] = hw_addr[1]; 704 dest[5] = hw_addr[0]; 705 } 706 707 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 708 struct iwl_nvm_data *data) 709 { 710 __le32 mac_addr0 = 711 cpu_to_le32(iwl_read32(trans, 712 trans->cfg->csr->mac_addr0_strap)); 713 __le32 mac_addr1 = 714 cpu_to_le32(iwl_read32(trans, 715 trans->cfg->csr->mac_addr1_strap)); 716 717 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 718 /* 719 * If the OEM fused a valid address, use it instead of the one in the 720 * OTP 721 */ 722 if (is_valid_ether_addr(data->hw_addr)) 723 return; 724 725 mac_addr0 = cpu_to_le32(iwl_read32(trans, 726 trans->cfg->csr->mac_addr0_otp)); 727 mac_addr1 = cpu_to_le32(iwl_read32(trans, 728 trans->cfg->csr->mac_addr1_otp)); 729 730 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 731 } 732 733 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 734 const struct iwl_cfg *cfg, 735 struct iwl_nvm_data *data, 736 const __le16 *mac_override, 737 const __be16 *nvm_hw) 738 { 739 const u8 *hw_addr; 740 741 if (mac_override) { 742 static const u8 reserved_mac[] = { 743 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 744 }; 745 746 hw_addr = (const u8 *)(mac_override + 747 MAC_ADDRESS_OVERRIDE_EXT_NVM); 748 749 /* 750 * Store the MAC address from MAO section. 751 * No byte swapping is required in MAO section 752 */ 753 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 754 755 /* 756 * Force the use of the OTP MAC address in case of reserved MAC 757 * address in the NVM, or if address is given but invalid. 758 */ 759 if (is_valid_ether_addr(data->hw_addr) && 760 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 761 return; 762 763 IWL_ERR(trans, 764 "mac address from nvm override section is not valid\n"); 765 } 766 767 if (nvm_hw) { 768 /* read the mac address from WFMP registers */ 769 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 770 WFMP_MAC_ADDR_0)); 771 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 772 WFMP_MAC_ADDR_1)); 773 774 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 775 776 return; 777 } 778 779 IWL_ERR(trans, "mac address is not found\n"); 780 } 781 782 static int iwl_set_hw_address(struct iwl_trans *trans, 783 const struct iwl_cfg *cfg, 784 struct iwl_nvm_data *data, const __be16 *nvm_hw, 785 const __le16 *mac_override) 786 { 787 if (cfg->mac_addr_from_csr) { 788 iwl_set_hw_address_from_csr(trans, data); 789 } else if (cfg->nvm_type != IWL_NVM_EXT) { 790 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 791 792 /* The byte order is little endian 16 bit, meaning 214365 */ 793 data->hw_addr[0] = hw_addr[1]; 794 data->hw_addr[1] = hw_addr[0]; 795 data->hw_addr[2] = hw_addr[3]; 796 data->hw_addr[3] = hw_addr[2]; 797 data->hw_addr[4] = hw_addr[5]; 798 data->hw_addr[5] = hw_addr[4]; 799 } else { 800 iwl_set_hw_address_family_8000(trans, cfg, data, 801 mac_override, nvm_hw); 802 } 803 804 if (!is_valid_ether_addr(data->hw_addr)) { 805 IWL_ERR(trans, "no valid mac address was found\n"); 806 return -EINVAL; 807 } 808 809 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 810 811 return 0; 812 } 813 814 static bool 815 iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg, 816 const __be16 *nvm_hw) 817 { 818 /* 819 * Workaround a bug in Indonesia SKUs where the regulatory in 820 * some 7000-family OTPs erroneously allow wide channels in 821 * 5GHz. To check for Indonesia, we take the SKU value from 822 * bits 1-4 in the subsystem ID and check if it is either 5 or 823 * 9. In those cases, we need to force-disable wide channels 824 * in 5GHz otherwise the FW will throw a sysassert when we try 825 * to use them. 826 */ 827 if (cfg->device_family == IWL_DEVICE_FAMILY_7000) { 828 /* 829 * Unlike the other sections in the NVM, the hw 830 * section uses big-endian. 831 */ 832 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 833 u8 sku = (subsystem_id & 0x1e) >> 1; 834 835 if (sku == 5 || sku == 9) { 836 IWL_DEBUG_EEPROM(dev, 837 "disabling wide channels in 5GHz (0x%0x %d)\n", 838 subsystem_id, sku); 839 return true; 840 } 841 } 842 843 return false; 844 } 845 846 struct iwl_nvm_data * 847 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 848 const __be16 *nvm_hw, const __le16 *nvm_sw, 849 const __le16 *nvm_calib, const __le16 *regulatory, 850 const __le16 *mac_override, const __le16 *phy_sku, 851 u8 tx_chains, u8 rx_chains, bool lar_fw_supported) 852 { 853 struct device *dev = trans->dev; 854 struct iwl_nvm_data *data; 855 bool lar_enabled; 856 u32 sku, radio_cfg; 857 u32 sbands_flags = 0; 858 u16 lar_config; 859 const __le16 *ch_section; 860 861 if (cfg->nvm_type != IWL_NVM_EXT) 862 data = kzalloc(sizeof(*data) + 863 sizeof(struct ieee80211_channel) * 864 IWL_NVM_NUM_CHANNELS, 865 GFP_KERNEL); 866 else 867 data = kzalloc(sizeof(*data) + 868 sizeof(struct ieee80211_channel) * 869 IWL_NVM_NUM_CHANNELS_EXT, 870 GFP_KERNEL); 871 if (!data) 872 return NULL; 873 874 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 875 876 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 877 iwl_set_radio_cfg(cfg, data, radio_cfg); 878 if (data->valid_tx_ant) 879 tx_chains &= data->valid_tx_ant; 880 if (data->valid_rx_ant) 881 rx_chains &= data->valid_rx_ant; 882 883 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 884 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 885 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 886 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 887 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 888 data->sku_cap_11n_enable = false; 889 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 890 (sku & NVM_SKU_CAP_11AC_ENABLE); 891 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 892 893 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 894 895 if (cfg->nvm_type != IWL_NVM_EXT) { 896 /* Checking for required sections */ 897 if (!nvm_calib) { 898 IWL_ERR(trans, 899 "Can't parse empty Calib NVM sections\n"); 900 kfree(data); 901 return NULL; 902 } 903 904 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 905 ®ulatory[NVM_CHANNELS_SDP] : 906 &nvm_sw[NVM_CHANNELS]; 907 908 /* in family 8000 Xtal calibration values moved to OTP */ 909 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 910 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 911 lar_enabled = true; 912 } else { 913 u16 lar_offset = data->nvm_version < 0xE39 ? 914 NVM_LAR_OFFSET_OLD : 915 NVM_LAR_OFFSET; 916 917 lar_config = le16_to_cpup(regulatory + lar_offset); 918 data->lar_enabled = !!(lar_config & 919 NVM_LAR_ENABLED); 920 lar_enabled = data->lar_enabled; 921 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 922 } 923 924 /* If no valid mac address was found - bail out */ 925 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 926 kfree(data); 927 return NULL; 928 } 929 930 if (lar_fw_supported && lar_enabled) 931 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 932 933 if (iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw)) 934 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 935 936 iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains, 937 sbands_flags); 938 data->calib_version = 255; 939 940 return data; 941 } 942 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 943 944 static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan, 945 int ch_idx, u16 nvm_flags, 946 const struct iwl_cfg *cfg) 947 { 948 u32 flags = NL80211_RRF_NO_HT40; 949 u32 last_5ghz_ht = LAST_5GHZ_HT; 950 951 if (cfg->nvm_type == IWL_NVM_EXT) 952 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 953 954 if (ch_idx < NUM_2GHZ_CHANNELS && 955 (nvm_flags & NVM_CHANNEL_40MHZ)) { 956 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 957 flags &= ~NL80211_RRF_NO_HT40PLUS; 958 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 959 flags &= ~NL80211_RRF_NO_HT40MINUS; 960 } else if (nvm_chan[ch_idx] <= last_5ghz_ht && 961 (nvm_flags & NVM_CHANNEL_40MHZ)) { 962 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 963 flags &= ~NL80211_RRF_NO_HT40PLUS; 964 else 965 flags &= ~NL80211_RRF_NO_HT40MINUS; 966 } 967 968 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 969 flags |= NL80211_RRF_NO_80MHZ; 970 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 971 flags |= NL80211_RRF_NO_160MHZ; 972 973 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 974 flags |= NL80211_RRF_NO_IR; 975 976 if (nvm_flags & NVM_CHANNEL_RADAR) 977 flags |= NL80211_RRF_DFS; 978 979 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 980 flags |= NL80211_RRF_NO_OUTDOOR; 981 982 /* Set the GO concurrent flag only in case that NO_IR is set. 983 * Otherwise it is meaningless 984 */ 985 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 986 (flags & NL80211_RRF_NO_IR)) 987 flags |= NL80211_RRF_GO_CONCURRENT; 988 989 return flags; 990 } 991 992 struct regdb_ptrs { 993 struct ieee80211_wmm_rule *rule; 994 u32 token; 995 }; 996 997 struct ieee80211_regdomain * 998 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 999 int num_of_ch, __le32 *channels, u16 fw_mcc, 1000 u16 geo_info) 1001 { 1002 int ch_idx; 1003 u16 ch_flags; 1004 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1005 const u8 *nvm_chan = cfg->nvm_type == IWL_NVM_EXT ? 1006 iwl_ext_nvm_channels : iwl_nvm_channels; 1007 struct ieee80211_regdomain *regd, *copy_rd; 1008 int size_of_regd, regd_to_copy; 1009 struct ieee80211_reg_rule *rule; 1010 struct regdb_ptrs *regdb_ptrs; 1011 enum nl80211_band band; 1012 int center_freq, prev_center_freq = 0; 1013 int valid_rules = 0; 1014 bool new_rule; 1015 int max_num_ch = cfg->nvm_type == IWL_NVM_EXT ? 1016 IWL_NVM_NUM_CHANNELS_EXT : IWL_NVM_NUM_CHANNELS; 1017 1018 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1019 return ERR_PTR(-EINVAL); 1020 1021 if (WARN_ON(num_of_ch > max_num_ch)) 1022 num_of_ch = max_num_ch; 1023 1024 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1025 num_of_ch); 1026 1027 /* build a regdomain rule for every valid channel */ 1028 size_of_regd = 1029 sizeof(struct ieee80211_regdomain) + 1030 num_of_ch * sizeof(struct ieee80211_reg_rule); 1031 1032 regd = kzalloc(size_of_regd, GFP_KERNEL); 1033 if (!regd) 1034 return ERR_PTR(-ENOMEM); 1035 1036 regdb_ptrs = kcalloc(num_of_ch, sizeof(*regdb_ptrs), GFP_KERNEL); 1037 if (!regdb_ptrs) { 1038 copy_rd = ERR_PTR(-ENOMEM); 1039 goto out; 1040 } 1041 1042 /* set alpha2 from FW. */ 1043 regd->alpha2[0] = fw_mcc >> 8; 1044 regd->alpha2[1] = fw_mcc & 0xff; 1045 1046 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1047 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1048 band = (ch_idx < NUM_2GHZ_CHANNELS) ? 1049 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1050 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1051 band); 1052 new_rule = false; 1053 1054 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1055 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1056 nvm_chan[ch_idx], ch_flags); 1057 continue; 1058 } 1059 1060 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1061 ch_flags, cfg); 1062 1063 /* we can't continue the same rule */ 1064 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1065 center_freq - prev_center_freq > 20) { 1066 valid_rules++; 1067 new_rule = true; 1068 } 1069 1070 rule = ®d->reg_rules[valid_rules - 1]; 1071 1072 if (new_rule) 1073 rule->freq_range.start_freq_khz = 1074 MHZ_TO_KHZ(center_freq - 10); 1075 1076 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1077 1078 /* this doesn't matter - not used by FW */ 1079 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1080 rule->power_rule.max_eirp = 1081 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1082 1083 rule->flags = reg_rule_flags; 1084 1085 /* rely on auto-calculation to merge BW of contiguous chans */ 1086 rule->flags |= NL80211_RRF_AUTO_BW; 1087 rule->freq_range.max_bandwidth_khz = 0; 1088 1089 prev_center_freq = center_freq; 1090 prev_reg_rule_flags = reg_rule_flags; 1091 1092 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1093 nvm_chan[ch_idx], ch_flags); 1094 1095 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1096 band == NL80211_BAND_2GHZ) 1097 continue; 1098 1099 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1100 } 1101 1102 regd->n_reg_rules = valid_rules; 1103 1104 /* 1105 * Narrow down regdom for unused regulatory rules to prevent hole 1106 * between reg rules to wmm rules. 1107 */ 1108 regd_to_copy = sizeof(struct ieee80211_regdomain) + 1109 valid_rules * sizeof(struct ieee80211_reg_rule); 1110 1111 copy_rd = kzalloc(regd_to_copy, GFP_KERNEL); 1112 if (!copy_rd) { 1113 copy_rd = ERR_PTR(-ENOMEM); 1114 goto out; 1115 } 1116 1117 memcpy(copy_rd, regd, regd_to_copy); 1118 1119 out: 1120 kfree(regdb_ptrs); 1121 kfree(regd); 1122 return copy_rd; 1123 } 1124 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1125 1126 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1127 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1128 #define MAX_NVM_FILE_LEN 16384 1129 1130 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1131 unsigned int len) 1132 { 1133 #define IWL_4165_DEVICE_ID 0x5501 1134 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1135 1136 if (section == NVM_SECTION_TYPE_PHY_SKU && 1137 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1138 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1139 /* OTP 0x52 bug work around: it's a 1x1 device */ 1140 data[3] = ANT_B | (ANT_B << 4); 1141 } 1142 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1143 1144 /* 1145 * Reads external NVM from a file into mvm->nvm_sections 1146 * 1147 * HOW TO CREATE THE NVM FILE FORMAT: 1148 * ------------------------------ 1149 * 1. create hex file, format: 1150 * 3800 -> header 1151 * 0000 -> header 1152 * 5a40 -> data 1153 * 1154 * rev - 6 bit (word1) 1155 * len - 10 bit (word1) 1156 * id - 4 bit (word2) 1157 * rsv - 12 bit (word2) 1158 * 1159 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1160 * 1161 * 3. create binary file from the hex file 1162 * 1163 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1164 */ 1165 int iwl_read_external_nvm(struct iwl_trans *trans, 1166 const char *nvm_file_name, 1167 struct iwl_nvm_section *nvm_sections) 1168 { 1169 int ret, section_size; 1170 u16 section_id; 1171 const struct firmware *fw_entry; 1172 const struct { 1173 __le16 word1; 1174 __le16 word2; 1175 u8 data[]; 1176 } *file_sec; 1177 const u8 *eof; 1178 u8 *temp; 1179 int max_section_size; 1180 const __le32 *dword_buff; 1181 1182 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1183 #define NVM_WORD2_ID(x) (x >> 12) 1184 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1185 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1186 #define NVM_HEADER_0 (0x2A504C54) 1187 #define NVM_HEADER_1 (0x4E564D2A) 1188 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1189 1190 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1191 1192 /* Maximal size depends on NVM version */ 1193 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1194 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1195 else 1196 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1197 1198 /* 1199 * Obtain NVM image via request_firmware. Since we already used 1200 * request_firmware_nowait() for the firmware binary load and only 1201 * get here after that we assume the NVM request can be satisfied 1202 * synchronously. 1203 */ 1204 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1205 if (ret) { 1206 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1207 nvm_file_name, ret); 1208 return ret; 1209 } 1210 1211 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1212 nvm_file_name, fw_entry->size); 1213 1214 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1215 IWL_ERR(trans, "NVM file too large\n"); 1216 ret = -EINVAL; 1217 goto out; 1218 } 1219 1220 eof = fw_entry->data + fw_entry->size; 1221 dword_buff = (__le32 *)fw_entry->data; 1222 1223 /* some NVM file will contain a header. 1224 * The header is identified by 2 dwords header as follow: 1225 * dword[0] = 0x2A504C54 1226 * dword[1] = 0x4E564D2A 1227 * 1228 * This header must be skipped when providing the NVM data to the FW. 1229 */ 1230 if (fw_entry->size > NVM_HEADER_SIZE && 1231 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1232 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1233 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1234 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1235 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1236 le32_to_cpu(dword_buff[3])); 1237 1238 /* nvm file validation, dword_buff[2] holds the file version */ 1239 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1240 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP && 1241 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1242 ret = -EFAULT; 1243 goto out; 1244 } 1245 } else { 1246 file_sec = (void *)fw_entry->data; 1247 } 1248 1249 while (true) { 1250 if (file_sec->data > eof) { 1251 IWL_ERR(trans, 1252 "ERROR - NVM file too short for section header\n"); 1253 ret = -EINVAL; 1254 break; 1255 } 1256 1257 /* check for EOF marker */ 1258 if (!file_sec->word1 && !file_sec->word2) { 1259 ret = 0; 1260 break; 1261 } 1262 1263 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1264 section_size = 1265 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1266 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1267 } else { 1268 section_size = 2 * EXT_NVM_WORD2_LEN( 1269 le16_to_cpu(file_sec->word2)); 1270 section_id = EXT_NVM_WORD1_ID( 1271 le16_to_cpu(file_sec->word1)); 1272 } 1273 1274 if (section_size > max_section_size) { 1275 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1276 section_size); 1277 ret = -EINVAL; 1278 break; 1279 } 1280 1281 if (!section_size) { 1282 IWL_ERR(trans, "ERROR - section empty\n"); 1283 ret = -EINVAL; 1284 break; 1285 } 1286 1287 if (file_sec->data + section_size > eof) { 1288 IWL_ERR(trans, 1289 "ERROR - NVM file too short for section (%d bytes)\n", 1290 section_size); 1291 ret = -EINVAL; 1292 break; 1293 } 1294 1295 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1296 "Invalid NVM section ID %d\n", section_id)) { 1297 ret = -EINVAL; 1298 break; 1299 } 1300 1301 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1302 if (!temp) { 1303 ret = -ENOMEM; 1304 break; 1305 } 1306 1307 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1308 1309 kfree(nvm_sections[section_id].data); 1310 nvm_sections[section_id].data = temp; 1311 nvm_sections[section_id].length = section_size; 1312 1313 /* advance to the next section */ 1314 file_sec = (void *)(file_sec->data + section_size); 1315 } 1316 out: 1317 release_firmware(fw_entry); 1318 return ret; 1319 } 1320 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1321 1322 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1323 const struct iwl_fw *fw) 1324 { 1325 struct iwl_nvm_get_info cmd = {}; 1326 struct iwl_nvm_get_info_rsp *rsp; 1327 struct iwl_nvm_data *nvm; 1328 struct iwl_host_cmd hcmd = { 1329 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1330 .data = { &cmd, }, 1331 .len = { sizeof(cmd) }, 1332 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1333 }; 1334 int ret; 1335 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable && 1336 fw_has_capa(&fw->ucode_capa, 1337 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 1338 bool empty_otp; 1339 u32 mac_flags; 1340 u32 sbands_flags = 0; 1341 1342 ret = iwl_trans_send_cmd(trans, &hcmd); 1343 if (ret) 1344 return ERR_PTR(ret); 1345 1346 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp), 1347 "Invalid payload len in NVM response from FW %d", 1348 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1349 ret = -EINVAL; 1350 goto out; 1351 } 1352 1353 rsp = (void *)hcmd.resp_pkt->data; 1354 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1355 NVM_GENERAL_FLAGS_EMPTY_OTP); 1356 if (empty_otp) 1357 IWL_INFO(trans, "OTP is empty\n"); 1358 1359 nvm = kzalloc(sizeof(*nvm) + 1360 sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS, 1361 GFP_KERNEL); 1362 if (!nvm) { 1363 ret = -ENOMEM; 1364 goto out; 1365 } 1366 1367 iwl_set_hw_address_from_csr(trans, nvm); 1368 /* TODO: if platform NVM has MAC address - override it here */ 1369 1370 if (!is_valid_ether_addr(nvm->hw_addr)) { 1371 IWL_ERR(trans, "no valid mac address was found\n"); 1372 ret = -EINVAL; 1373 goto err_free; 1374 } 1375 1376 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1377 1378 /* Initialize general data */ 1379 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1380 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1381 if (nvm->n_hw_addrs == 0) 1382 IWL_WARN(trans, 1383 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1384 empty_otp); 1385 1386 /* Initialize MAC sku data */ 1387 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1388 nvm->sku_cap_11ac_enable = 1389 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1390 nvm->sku_cap_11n_enable = 1391 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1392 nvm->sku_cap_11ax_enable = 1393 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1394 nvm->sku_cap_band_24ghz_enable = 1395 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1396 nvm->sku_cap_band_52ghz_enable = 1397 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1398 nvm->sku_cap_mimo_disabled = 1399 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1400 1401 /* Initialize PHY sku data */ 1402 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1403 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1404 1405 if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) { 1406 nvm->lar_enabled = true; 1407 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1408 } 1409 1410 iwl_init_sbands(trans->dev, trans->cfg, nvm, 1411 rsp->regulatory.channel_profile, 1412 nvm->valid_tx_ant & fw->valid_tx_ant, 1413 nvm->valid_rx_ant & fw->valid_rx_ant, 1414 sbands_flags); 1415 1416 iwl_free_resp(&hcmd); 1417 return nvm; 1418 1419 err_free: 1420 kfree(nvm); 1421 out: 1422 iwl_free_resp(&hcmd); 1423 return ERR_PTR(ret); 1424 } 1425 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1426