18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 28e99ea8dSJohannes Berg /* 3*a800f958SEmmanuel Grumbach * Copyright (C) 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg */ 5e705c121SKalle Valo #ifndef __iwl_io_h__ 6e705c121SKalle Valo #define __iwl_io_h__ 7e705c121SKalle Valo 8e705c121SKalle Valo #include "iwl-devtrace.h" 9e705c121SKalle Valo #include "iwl-trans.h" 10e705c121SKalle Valo 11e705c121SKalle Valo void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val); 12e705c121SKalle Valo void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val); 1312a17458SSara Sharon void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val); 14e705c121SKalle Valo u32 iwl_read32(struct iwl_trans *trans, u32 ofs); 15e705c121SKalle Valo 16e705c121SKalle Valo static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask) 17e705c121SKalle Valo { 18e705c121SKalle Valo iwl_trans_set_bits_mask(trans, reg, mask, mask); 19e705c121SKalle Valo } 20e705c121SKalle Valo 21e705c121SKalle Valo static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask) 22e705c121SKalle Valo { 23e705c121SKalle Valo iwl_trans_set_bits_mask(trans, reg, mask, 0); 24e705c121SKalle Valo } 25e705c121SKalle Valo 26e705c121SKalle Valo int iwl_poll_bit(struct iwl_trans *trans, u32 addr, 27e705c121SKalle Valo u32 bits, u32 mask, int timeout); 28e705c121SKalle Valo int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask, 29e705c121SKalle Valo int timeout); 30e705c121SKalle Valo 31e705c121SKalle Valo u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg); 32e705c121SKalle Valo void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value); 3312a17458SSara Sharon void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value); 34e705c121SKalle Valo 35e705c121SKalle Valo 3614ef1b43SGolan Ben-Ami u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs); 37e705c121SKalle Valo u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs); 3814ef1b43SGolan Ben-Ami void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val); 3912a17458SSara Sharon void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val); 40*a800f958SEmmanuel Grumbach void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, 41*a800f958SEmmanuel Grumbach u32 val, u32 delay_ms); 42*a800f958SEmmanuel Grumbach static inline void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val) 43*a800f958SEmmanuel Grumbach { 44*a800f958SEmmanuel Grumbach iwl_write_prph_delay(trans, ofs, val, 0); 45*a800f958SEmmanuel Grumbach } 46*a800f958SEmmanuel Grumbach 47e705c121SKalle Valo int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr, 48e705c121SKalle Valo u32 bits, u32 mask, int timeout); 49e705c121SKalle Valo void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); 50e705c121SKalle Valo void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs, 51e705c121SKalle Valo u32 bits, u32 mask); 52e705c121SKalle Valo void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); 53e705c121SKalle Valo void iwl_force_nmi(struct iwl_trans *trans); 54e705c121SKalle Valo 5579b6c8feSLuca Coelho int iwl_finish_nic_init(struct iwl_trans *trans, 5679b6c8feSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans); 57c96b5eecSJohannes Berg 58e705c121SKalle Valo /* Error handling */ 59e705c121SKalle Valo int iwl_dump_fh(struct iwl_trans *trans, char **buf); 60e705c121SKalle Valo 61ea695b7cSShaul Triebitz /* 62ea695b7cSShaul Triebitz * UMAC periphery address space changed from 0xA00000 to 0xD00000 starting from 63ea695b7cSShaul Triebitz * device family AX200. So peripheries used in families above and below AX200 64ea695b7cSShaul Triebitz * should go through iwl_..._umac_..._prph. 65ea695b7cSShaul Triebitz */ 66ea695b7cSShaul Triebitz static inline u32 iwl_umac_prph(struct iwl_trans *trans, u32 ofs) 67ea695b7cSShaul Triebitz { 681fee35d0SLuca Coelho return ofs + trans->trans_cfg->umac_prph_offset; 69ea695b7cSShaul Triebitz } 70ea695b7cSShaul Triebitz 71ea695b7cSShaul Triebitz static inline u32 iwl_read_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs) 72ea695b7cSShaul Triebitz { 7379b6c8feSLuca Coelho return iwl_read_prph_no_grab(trans, ofs + 741fee35d0SLuca Coelho trans->trans_cfg->umac_prph_offset); 75ea695b7cSShaul Triebitz } 76ea695b7cSShaul Triebitz 77ea695b7cSShaul Triebitz static inline u32 iwl_read_umac_prph(struct iwl_trans *trans, u32 ofs) 78ea695b7cSShaul Triebitz { 791fee35d0SLuca Coelho return iwl_read_prph(trans, ofs + trans->trans_cfg->umac_prph_offset); 80ea695b7cSShaul Triebitz } 81ea695b7cSShaul Triebitz 82ea695b7cSShaul Triebitz static inline void iwl_write_umac_prph_no_grab(struct iwl_trans *trans, u32 ofs, 83ea695b7cSShaul Triebitz u32 val) 84ea695b7cSShaul Triebitz { 851fee35d0SLuca Coelho iwl_write_prph_no_grab(trans, ofs + trans->trans_cfg->umac_prph_offset, 8679b6c8feSLuca Coelho val); 87ea695b7cSShaul Triebitz } 88ea695b7cSShaul Triebitz 89ea695b7cSShaul Triebitz static inline void iwl_write_umac_prph(struct iwl_trans *trans, u32 ofs, 90ea695b7cSShaul Triebitz u32 val) 91ea695b7cSShaul Triebitz { 921fee35d0SLuca Coelho iwl_write_prph(trans, ofs + trans->trans_cfg->umac_prph_offset, val); 93ea695b7cSShaul Triebitz } 94ea695b7cSShaul Triebitz 95ea695b7cSShaul Triebitz static inline int iwl_poll_umac_prph_bit(struct iwl_trans *trans, u32 addr, 96ea695b7cSShaul Triebitz u32 bits, u32 mask, int timeout) 97ea695b7cSShaul Triebitz { 9879b6c8feSLuca Coelho return iwl_poll_prph_bit(trans, addr + 991fee35d0SLuca Coelho trans->trans_cfg->umac_prph_offset, 100ea695b7cSShaul Triebitz bits, mask, timeout); 101ea695b7cSShaul Triebitz } 102ea695b7cSShaul Triebitz 103e705c121SKalle Valo #endif 104