1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2003-2014, 2018-2020 Intel Corporation 4 * Copyright (C) 2015-2016 Intel Deutschland GmbH 5 */ 6 #include <linux/delay.h> 7 #include <linux/device.h> 8 #include <linux/export.h> 9 10 #include "iwl-drv.h" 11 #include "iwl-io.h" 12 #include "iwl-csr.h" 13 #include "iwl-debug.h" 14 #include "iwl-prph.h" 15 #include "iwl-fh.h" 16 17 void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val) 18 { 19 trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val); 20 iwl_trans_write8(trans, ofs, val); 21 } 22 IWL_EXPORT_SYMBOL(iwl_write8); 23 24 void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val) 25 { 26 trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val); 27 iwl_trans_write32(trans, ofs, val); 28 } 29 IWL_EXPORT_SYMBOL(iwl_write32); 30 31 void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val) 32 { 33 trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val); 34 iwl_trans_write32(trans, ofs, lower_32_bits(val)); 35 iwl_trans_write32(trans, ofs + 4, upper_32_bits(val)); 36 } 37 IWL_EXPORT_SYMBOL(iwl_write64); 38 39 u32 iwl_read32(struct iwl_trans *trans, u32 ofs) 40 { 41 u32 val = iwl_trans_read32(trans, ofs); 42 43 trace_iwlwifi_dev_ioread32(trans->dev, ofs, val); 44 return val; 45 } 46 IWL_EXPORT_SYMBOL(iwl_read32); 47 48 #define IWL_POLL_INTERVAL 10 /* microseconds */ 49 50 int iwl_poll_bit(struct iwl_trans *trans, u32 addr, 51 u32 bits, u32 mask, int timeout) 52 { 53 int t = 0; 54 55 do { 56 if ((iwl_read32(trans, addr) & mask) == (bits & mask)) 57 return t; 58 udelay(IWL_POLL_INTERVAL); 59 t += IWL_POLL_INTERVAL; 60 } while (t < timeout); 61 62 return -ETIMEDOUT; 63 } 64 IWL_EXPORT_SYMBOL(iwl_poll_bit); 65 66 u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg) 67 { 68 u32 value = 0x5a5a5a5a; 69 70 if (iwl_trans_grab_nic_access(trans)) { 71 value = iwl_read32(trans, reg); 72 iwl_trans_release_nic_access(trans); 73 } 74 75 return value; 76 } 77 IWL_EXPORT_SYMBOL(iwl_read_direct32); 78 79 void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value) 80 { 81 if (iwl_trans_grab_nic_access(trans)) { 82 iwl_write32(trans, reg, value); 83 iwl_trans_release_nic_access(trans); 84 } 85 } 86 IWL_EXPORT_SYMBOL(iwl_write_direct32); 87 88 void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value) 89 { 90 if (iwl_trans_grab_nic_access(trans)) { 91 iwl_write64(trans, reg, value); 92 iwl_trans_release_nic_access(trans); 93 } 94 } 95 IWL_EXPORT_SYMBOL(iwl_write_direct64); 96 97 int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask, 98 int timeout) 99 { 100 int t = 0; 101 102 do { 103 if ((iwl_read_direct32(trans, addr) & mask) == mask) 104 return t; 105 udelay(IWL_POLL_INTERVAL); 106 t += IWL_POLL_INTERVAL; 107 } while (t < timeout); 108 109 return -ETIMEDOUT; 110 } 111 IWL_EXPORT_SYMBOL(iwl_poll_direct_bit); 112 113 u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs) 114 { 115 u32 val = iwl_trans_read_prph(trans, ofs); 116 trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val); 117 return val; 118 } 119 IWL_EXPORT_SYMBOL(iwl_read_prph_no_grab); 120 121 void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val) 122 { 123 trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val); 124 iwl_trans_write_prph(trans, ofs, val); 125 } 126 IWL_EXPORT_SYMBOL(iwl_write_prph_no_grab); 127 128 void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val) 129 { 130 trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val); 131 iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff); 132 iwl_write_prph_no_grab(trans, ofs + 4, val >> 32); 133 } 134 IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab); 135 136 u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs) 137 { 138 u32 val = 0x5a5a5a5a; 139 140 if (iwl_trans_grab_nic_access(trans)) { 141 val = iwl_read_prph_no_grab(trans, ofs); 142 iwl_trans_release_nic_access(trans); 143 } 144 return val; 145 } 146 IWL_EXPORT_SYMBOL(iwl_read_prph); 147 148 void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms) 149 { 150 if (iwl_trans_grab_nic_access(trans)) { 151 mdelay(delay_ms); 152 iwl_write_prph_no_grab(trans, ofs, val); 153 iwl_trans_release_nic_access(trans); 154 } 155 } 156 IWL_EXPORT_SYMBOL(iwl_write_prph_delay); 157 158 int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr, 159 u32 bits, u32 mask, int timeout) 160 { 161 int t = 0; 162 163 do { 164 if ((iwl_read_prph(trans, addr) & mask) == (bits & mask)) 165 return t; 166 udelay(IWL_POLL_INTERVAL); 167 t += IWL_POLL_INTERVAL; 168 } while (t < timeout); 169 170 return -ETIMEDOUT; 171 } 172 173 void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask) 174 { 175 if (iwl_trans_grab_nic_access(trans)) { 176 iwl_write_prph_no_grab(trans, ofs, 177 iwl_read_prph_no_grab(trans, ofs) | 178 mask); 179 iwl_trans_release_nic_access(trans); 180 } 181 } 182 IWL_EXPORT_SYMBOL(iwl_set_bits_prph); 183 184 void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs, 185 u32 bits, u32 mask) 186 { 187 if (iwl_trans_grab_nic_access(trans)) { 188 iwl_write_prph_no_grab(trans, ofs, 189 (iwl_read_prph_no_grab(trans, ofs) & 190 mask) | bits); 191 iwl_trans_release_nic_access(trans); 192 } 193 } 194 IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph); 195 196 void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask) 197 { 198 u32 val; 199 200 if (iwl_trans_grab_nic_access(trans)) { 201 val = iwl_read_prph_no_grab(trans, ofs); 202 iwl_write_prph_no_grab(trans, ofs, (val & ~mask)); 203 iwl_trans_release_nic_access(trans); 204 } 205 } 206 IWL_EXPORT_SYMBOL(iwl_clear_bits_prph); 207 208 void iwl_force_nmi(struct iwl_trans *trans) 209 { 210 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000) 211 iwl_write_prph_delay(trans, DEVICE_SET_NMI_REG, 212 DEVICE_SET_NMI_VAL_DRV, 1); 213 else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 214 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, 215 UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER); 216 else 217 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 218 UREG_DOORBELL_TO_ISR6_NMI_BIT); 219 } 220 IWL_EXPORT_SYMBOL(iwl_force_nmi); 221 222 static const char *get_rfh_string(int cmd) 223 { 224 #define IWL_CMD(x) case x: return #x 225 #define IWL_CMD_MQ(arg, reg, q) { if (arg == reg(q)) return #reg; } 226 227 int i; 228 229 for (i = 0; i < IWL_MAX_RX_HW_QUEUES; i++) { 230 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_BA_LSB, i); 231 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_WIDX, i); 232 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_RIDX, i); 233 IWL_CMD_MQ(cmd, RFH_Q_URBD_STTS_WPTR_LSB, i); 234 } 235 236 switch (cmd) { 237 IWL_CMD(RFH_RXF_DMA_CFG); 238 IWL_CMD(RFH_GEN_CFG); 239 IWL_CMD(RFH_GEN_STATUS); 240 IWL_CMD(FH_TSSR_TX_STATUS_REG); 241 IWL_CMD(FH_TSSR_TX_ERROR_REG); 242 default: 243 return "UNKNOWN"; 244 } 245 #undef IWL_CMD_MQ 246 } 247 248 struct reg { 249 u32 addr; 250 bool is64; 251 }; 252 253 static int iwl_dump_rfh(struct iwl_trans *trans, char **buf) 254 { 255 int i, q; 256 int num_q = trans->num_rx_queues; 257 static const u32 rfh_tbl[] = { 258 RFH_RXF_DMA_CFG, 259 RFH_GEN_CFG, 260 RFH_GEN_STATUS, 261 FH_TSSR_TX_STATUS_REG, 262 FH_TSSR_TX_ERROR_REG, 263 }; 264 static const struct reg rfh_mq_tbl[] = { 265 { RFH_Q0_FRBDCB_BA_LSB, true }, 266 { RFH_Q0_FRBDCB_WIDX, false }, 267 { RFH_Q0_FRBDCB_RIDX, false }, 268 { RFH_Q0_URBD_STTS_WPTR_LSB, true }, 269 }; 270 271 #ifdef CONFIG_IWLWIFI_DEBUGFS 272 if (buf) { 273 int pos = 0; 274 /* 275 * Register (up to 34 for name + 8 blank/q for MQ): 40 chars 276 * Colon + space: 2 characters 277 * 0X%08x: 10 characters 278 * New line: 1 character 279 * Total of 53 characters 280 */ 281 size_t bufsz = ARRAY_SIZE(rfh_tbl) * 53 + 282 ARRAY_SIZE(rfh_mq_tbl) * 53 * num_q + 40; 283 284 *buf = kmalloc(bufsz, GFP_KERNEL); 285 if (!*buf) 286 return -ENOMEM; 287 288 pos += scnprintf(*buf + pos, bufsz - pos, 289 "RFH register values:\n"); 290 291 for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++) 292 pos += scnprintf(*buf + pos, bufsz - pos, 293 "%40s: 0X%08x\n", 294 get_rfh_string(rfh_tbl[i]), 295 iwl_read_prph(trans, rfh_tbl[i])); 296 297 for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++) 298 for (q = 0; q < num_q; q++) { 299 u32 addr = rfh_mq_tbl[i].addr; 300 301 addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4); 302 pos += scnprintf(*buf + pos, bufsz - pos, 303 "%34s(q %2d): 0X%08x\n", 304 get_rfh_string(addr), q, 305 iwl_read_prph(trans, addr)); 306 } 307 308 return pos; 309 } 310 #endif 311 312 IWL_ERR(trans, "RFH register values:\n"); 313 for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++) 314 IWL_ERR(trans, " %34s: 0X%08x\n", 315 get_rfh_string(rfh_tbl[i]), 316 iwl_read_prph(trans, rfh_tbl[i])); 317 318 for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++) 319 for (q = 0; q < num_q; q++) { 320 u32 addr = rfh_mq_tbl[i].addr; 321 322 addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4); 323 IWL_ERR(trans, " %34s(q %d): 0X%08x\n", 324 get_rfh_string(addr), q, 325 iwl_read_prph(trans, addr)); 326 } 327 328 return 0; 329 } 330 331 static const char *get_fh_string(int cmd) 332 { 333 switch (cmd) { 334 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG); 335 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG); 336 IWL_CMD(FH_RSCSR_CHNL0_WPTR); 337 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG); 338 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG); 339 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG); 340 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); 341 IWL_CMD(FH_TSSR_TX_STATUS_REG); 342 IWL_CMD(FH_TSSR_TX_ERROR_REG); 343 default: 344 return "UNKNOWN"; 345 } 346 #undef IWL_CMD 347 } 348 349 int iwl_dump_fh(struct iwl_trans *trans, char **buf) 350 { 351 int i; 352 static const u32 fh_tbl[] = { 353 FH_RSCSR_CHNL0_STTS_WPTR_REG, 354 FH_RSCSR_CHNL0_RBDCB_BASE_REG, 355 FH_RSCSR_CHNL0_WPTR, 356 FH_MEM_RCSR_CHNL0_CONFIG_REG, 357 FH_MEM_RSSR_SHARED_CTRL_REG, 358 FH_MEM_RSSR_RX_STATUS_REG, 359 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, 360 FH_TSSR_TX_STATUS_REG, 361 FH_TSSR_TX_ERROR_REG 362 }; 363 364 if (trans->trans_cfg->mq_rx_supported) 365 return iwl_dump_rfh(trans, buf); 366 367 #ifdef CONFIG_IWLWIFI_DEBUGFS 368 if (buf) { 369 int pos = 0; 370 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; 371 372 *buf = kmalloc(bufsz, GFP_KERNEL); 373 if (!*buf) 374 return -ENOMEM; 375 376 pos += scnprintf(*buf + pos, bufsz - pos, 377 "FH register values:\n"); 378 379 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) 380 pos += scnprintf(*buf + pos, bufsz - pos, 381 " %34s: 0X%08x\n", 382 get_fh_string(fh_tbl[i]), 383 iwl_read_direct32(trans, fh_tbl[i])); 384 385 return pos; 386 } 387 #endif 388 389 IWL_ERR(trans, "FH register values:\n"); 390 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) 391 IWL_ERR(trans, " %34s: 0X%08x\n", 392 get_fh_string(fh_tbl[i]), 393 iwl_read_direct32(trans, fh_tbl[i])); 394 395 return 0; 396 } 397 398 int iwl_finish_nic_init(struct iwl_trans *trans, 399 const struct iwl_cfg_trans_params *cfg_trans) 400 { 401 int err; 402 403 if (cfg_trans->bisr_workaround) { 404 /* ensure the TOP FSM isn't still in previous reset */ 405 mdelay(2); 406 } 407 408 /* 409 * Set "initialization complete" bit to move adapter from 410 * D0U* --> D0A* (powered-up active) state. 411 */ 412 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 413 414 if (cfg_trans->device_family == IWL_DEVICE_FAMILY_8000) 415 udelay(2); 416 417 /* 418 * Wait for clock stabilization; once stabilized, access to 419 * device-internal resources is supported, e.g. iwl_write_prph() 420 * and accesses to uCode SRAM. 421 */ 422 err = iwl_poll_bit(trans, CSR_GP_CNTRL, 423 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 424 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 425 25000); 426 if (err < 0) 427 IWL_DEBUG_INFO(trans, "Failed to wake NIC\n"); 428 429 if (cfg_trans->bisr_workaround) { 430 /* ensure BISR shift has finished */ 431 udelay(200); 432 } 433 434 return err < 0 ? err : 0; 435 } 436 IWL_EXPORT_SYMBOL(iwl_finish_nic_init); 437 438 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 439 u32 sw_err_bit) 440 { 441 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 442 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 443 444 /* if the interrupts were already disabled, there is no point in 445 * calling iwl_disable_interrupts 446 */ 447 if (interrupts_enabled) 448 iwl_trans_interrupts(trans, false); 449 450 iwl_force_nmi(trans); 451 while (time_after(timeout, jiffies)) { 452 u32 inta_hw = iwl_read32(trans, inta_addr); 453 454 /* Error detected by uCode */ 455 if (inta_hw & sw_err_bit) { 456 /* Clear causes register */ 457 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 458 break; 459 } 460 461 mdelay(1); 462 } 463 464 /* enable interrupts only if there were already enabled before this 465 * function to avoid a case were the driver enable interrupts before 466 * proper configurations were made 467 */ 468 if (interrupts_enabled) 469 iwl_trans_interrupts(trans, true); 470 471 iwl_trans_fw_error(trans); 472 } 473