1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 23 * USA 24 * 25 * The full GNU General Public License is included in this distribution 26 * in the file called COPYING. 27 * 28 * Contact Information: 29 * Intel Linux Wireless <linuxwifi@intel.com> 30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 31 * 32 * BSD LICENSE 33 * 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 35 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 42 * * Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * * Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in 46 * the documentation and/or other materials provided with the 47 * distribution. 48 * * Neither the name Intel Corporation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 *****************************************************************************/ 65 #ifndef __iwl_fh_h__ 66 #define __iwl_fh_h__ 67 68 #include <linux/types.h> 69 70 /****************************/ 71 /* Flow Handler Definitions */ 72 /****************************/ 73 74 /** 75 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 76 * Addresses are offsets from device's PCI hardware base address. 77 */ 78 #define FH_MEM_LOWER_BOUND (0x1000) 79 #define FH_MEM_UPPER_BOUND (0x2000) 80 81 /** 82 * Keep-Warm (KW) buffer base address. 83 * 84 * Driver must allocate a 4KByte buffer that is for keeping the 85 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 86 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 87 * from going into a power-savings mode that would cause higher DRAM latency, 88 * and possible data over/under-runs, before all Tx/Rx is complete. 89 * 90 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 91 * of the buffer, which must be 4K aligned. Once this is set up, the device 92 * automatically invokes keep-warm accesses when normal accesses might not 93 * be sufficient to maintain fast DRAM response. 94 * 95 * Bit fields: 96 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 97 */ 98 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 99 100 101 /** 102 * TFD Circular Buffers Base (CBBC) addresses 103 * 104 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 105 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 106 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 107 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 108 * aligned (address bits 0-7 must be 0). 109 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 110 * for them are in different places. 111 * 112 * Bit fields in each pointer register: 113 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 114 */ 115 #define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 116 #define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 117 #define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0) 118 #define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 119 #define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20) 120 #define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 121 /* a000 TFD table address, 64 bit */ 122 #define TFH_TFDQ_CBB_TABLE (0x1C00) 123 124 /* Find TFD CB base pointer for given queue */ 125 static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans, 126 unsigned int chnl) 127 { 128 if (trans->cfg->use_tfh) { 129 WARN_ON_ONCE(chnl >= 64); 130 return TFH_TFDQ_CBB_TABLE + 8 * chnl; 131 } 132 if (chnl < 16) 133 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 134 if (chnl < 20) 135 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 136 WARN_ON_ONCE(chnl >= 32); 137 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 138 } 139 140 /* a000 configuration registers */ 141 142 /* 143 * TFH Configuration register. 144 * 145 * BIT fields: 146 * 147 * Bits 3:0: 148 * Define the maximum number of pending read requests. 149 * Maximum configration value allowed is 0xC 150 * Bits 9:8: 151 * Define the maximum transfer size. (64 / 128 / 256) 152 * Bit 10: 153 * When bit is set and transfer size is set to 128B, the TFH will enable 154 * reading chunks of more than 64B only if the read address is aligned to 128B. 155 * In case of DRAM read address which is not aligned to 128B, the TFH will 156 * enable transfer size which doesn't cross 64B DRAM address boundary. 157 */ 158 #define TFH_TRANSFER_MODE (0x1F40) 159 #define TFH_TRANSFER_MAX_PENDING_REQ 0xc 160 #define TFH_CHUNK_SIZE_128 BIT(8) 161 #define TFH_CHUNK_SPLIT_MODE BIT(10) 162 /* 163 * Defines the offset address in dwords referring from the beginning of the 164 * Tx CMD which will be updated in DRAM. 165 * Note that the TFH offset address for Tx CMD update is always referring to 166 * the start of the TFD first TB. 167 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 168 */ 169 #define TFH_TXCMD_UPDATE_CFG (0x1F48) 170 /* 171 * Controls TX DMA operation 172 * 173 * BIT fields: 174 * 175 * Bits 31:30: Enable the SRAM DMA channel. 176 * Turning on bit 31 will kick the SRAM2DRAM DMA. 177 * Note that the sram2dram may be enabled only after configuring the DRAM and 178 * SRAM addresses registers and the byte count register. 179 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 180 * set to 1 - interrupt is sent to the driver 181 * Bit 0: Indicates the snoop configuration 182 */ 183 #define TFH_SRV_DMA_CHNL0_CTRL (0x1F60) 184 #define TFH_SRV_DMA_SNOOP BIT(0) 185 #define TFH_SRV_DMA_TO_DRIVER BIT(24) 186 #define TFH_SRV_DMA_START BIT(31) 187 188 /* Defines the DMA SRAM write start address to transfer a data block */ 189 #define TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) 190 191 /* Defines the 64bits DRAM start address to read the DMA data block from */ 192 #define TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) 193 194 /* 195 * Defines the number of bytes to transfer from DRAM to SRAM. 196 * Note that this register may be configured with non-dword aligned size. 197 */ 198 #define TFH_SRV_DMA_CHNL0_BC (0x1F70) 199 200 /** 201 * Rx SRAM Control and Status Registers (RSCSR) 202 * 203 * These registers provide handshake between driver and device for the Rx queue 204 * (this queue handles *all* command responses, notifications, Rx data, etc. 205 * sent from uCode to host driver). Unlike Tx, there is only one Rx 206 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 207 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 208 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 209 * mapping between RBDs and RBs. 210 * 211 * Driver must allocate host DRAM memory for the following, and set the 212 * physical address of each into device registers: 213 * 214 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 215 * entries (although any power of 2, up to 4096, is selectable by driver). 216 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 217 * (typically 4K, although 8K or 16K are also selectable by driver). 218 * Driver sets up RB size and number of RBDs in the CB via Rx config 219 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 220 * 221 * Bit fields within one RBD: 222 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 223 * 224 * Driver sets physical address [35:8] of base of RBD circular buffer 225 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 226 * 227 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 228 * (RBs) have been filled, via a "write pointer", actually the index of 229 * the RB's corresponding RBD within the circular buffer. Driver sets 230 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 231 * 232 * Bit fields in lower dword of Rx status buffer (upper dword not used 233 * by driver: 234 * 31-12: Not used by driver 235 * 11- 0: Index of last filled Rx buffer descriptor 236 * (device writes, driver reads this value) 237 * 238 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 239 * enter pointers to these RBs into contiguous RBD circular buffer entries, 240 * and update the device's "write" index register, 241 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 242 * 243 * This "write" index corresponds to the *next* RBD that the driver will make 244 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 245 * the circular buffer. This value should initially be 0 (before preparing any 246 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 247 * wrap back to 0 at the end of the circular buffer (but don't wrap before 248 * "read" index has advanced past 1! See below). 249 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 250 * 251 * As the device fills RBs (referenced from contiguous RBDs within the circular 252 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 253 * to tell the driver the index of the latest filled RBD. The driver must 254 * read this "read" index from DRAM after receiving an Rx interrupt from device 255 * 256 * The driver must also internally keep track of a third index, which is the 257 * next RBD to process. When receiving an Rx interrupt, driver should process 258 * all filled but unprocessed RBs up to, but not including, the RB 259 * corresponding to the "read" index. For example, if "read" index becomes "1", 260 * driver may process the RB pointed to by RBD 0. Depending on volume of 261 * traffic, there may be many RBs to process. 262 * 263 * If read index == write index, device thinks there is no room to put new data. 264 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 265 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 266 * and "read" indexes; that is, make sure that there are no more than 254 267 * buffers waiting to be filled. 268 */ 269 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 270 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 271 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 272 273 /** 274 * Physical base address of 8-byte Rx Status buffer. 275 * Bit fields: 276 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 277 */ 278 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 279 280 /** 281 * Physical base address of Rx Buffer Descriptor Circular Buffer. 282 * Bit fields: 283 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 284 */ 285 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 286 287 /** 288 * Rx write pointer (index, really!). 289 * Bit fields: 290 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 291 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 292 */ 293 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 294 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 295 296 #define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 297 #define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 298 299 /** 300 * Rx Config/Status Registers (RCSR) 301 * Rx Config Reg for channel 0 (only channel used) 302 * 303 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 304 * normal operation (see bit fields). 305 * 306 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 307 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 308 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 309 * 310 * Bit fields: 311 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 312 * '10' operate normally 313 * 29-24: reserved 314 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 315 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 316 * 19-18: reserved 317 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 318 * '10' 12K, '11' 16K. 319 * 15-14: reserved 320 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 321 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 322 * typical value 0x10 (about 1/2 msec) 323 * 3- 0: reserved 324 */ 325 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 326 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 327 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 328 329 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 330 #define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8) 331 #define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10) 332 333 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 334 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 335 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 336 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 337 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 338 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 339 340 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 341 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 342 #define RX_RB_TIMEOUT (0x11) 343 344 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 345 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 346 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 347 348 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 349 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 350 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 351 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 352 353 #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 354 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 355 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 356 357 /** 358 * Rx Shared Status Registers (RSSR) 359 * 360 * After stopping Rx DMA channel (writing 0 to 361 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 362 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 363 * 364 * Bit fields: 365 * 24: 1 = Channel 0 is idle 366 * 367 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 368 * contain default values that should not be altered by the driver. 369 */ 370 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 371 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 372 373 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 374 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 375 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 376 (FH_MEM_RSSR_LOWER_BOUND + 0x008) 377 378 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 379 380 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 381 #define FH_MEM_TB_MAX_LENGTH (0x00020000) 382 383 /* 9000 rx series registers */ 384 385 #define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 386 #define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 387 /* Write index table */ 388 #define RFH_Q0_FRBDCB_WIDX 0xA08080 389 #define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4) 390 /* Write index table - shadow registers */ 391 #define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 392 #define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 393 /* Read index table */ 394 #define RFH_Q0_FRBDCB_RIDX 0xA080C0 395 #define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4) 396 /* Used list table */ 397 #define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 398 #define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8) 399 /* Write index table */ 400 #define RFH_Q0_URBDCB_WIDX 0xA08180 401 #define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4) 402 #define RFH_Q0_URBDCB_VAID 0xA081C0 403 #define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4) 404 /* stts */ 405 #define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 406 #define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 407 408 #define RFH_Q0_ORB_WPTR_LSB 0xA08280 409 #define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8) 410 #define RFH_RBDBUF_RBD0_LSB 0xA08300 411 #define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8) 412 413 /** 414 * RFH Status Register 415 * 416 * Bit fields: 417 * 418 * Bit 29: RBD_FETCH_IDLE 419 * This status flag is set by the RFH when there is no active RBD fetch from 420 * DRAM. 421 * Once the RFH RBD controller starts fetching (or when there is a pending 422 * RBD read response from DRAM), this flag is immediately turned off. 423 * 424 * Bit 30: SRAM_DMA_IDLE 425 * This status flag is set by the RFH when there is no active transaction from 426 * SRAM to DRAM. 427 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 428 * 429 * Bit 31: RXF_DMA_IDLE 430 * This status flag is set by the RFH when there is no active transaction from 431 * RXF to DRAM. 432 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 433 */ 434 #define RFH_GEN_STATUS 0xA09808 435 #define RBD_FETCH_IDLE BIT(29) 436 #define SRAM_DMA_IDLE BIT(30) 437 #define RXF_DMA_IDLE BIT(31) 438 439 /* DMA configuration */ 440 #define RFH_RXF_DMA_CFG 0xA09820 441 /* RB size */ 442 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 443 #define RFH_RXF_DMA_RB_SIZE_POS 16 444 #define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS) 445 #define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS) 446 #define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS) 447 #define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS) 448 #define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS) 449 #define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS) 450 #define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS) 451 #define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS) 452 #define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS) 453 #define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS) 454 /* RB Circular Buffer size:defines the table sizes in RBD units */ 455 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 456 #define RFH_RXF_DMA_RBDCB_SIZE_POS 20 457 #define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS) 458 #define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS) 459 #define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS) 460 #define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 461 #define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 462 #define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS) 463 #define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS) 464 #define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS) 465 #define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS) 466 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 467 #define RFH_RXF_DMA_MIN_RB_SIZE_POS 24 468 #define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS) 469 #define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 470 #define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 471 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 472 #define RFH_DMA_EN_ENABLE_VAL BIT(31) 473 474 #define RFH_RXF_RXQ_ACTIVE 0xA0980C 475 476 #define RFH_GEN_CFG 0xA09800 477 #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0) 478 #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1) 479 #define RFH_GEN_CFG_RB_CHUNK_SIZE_POS 4 480 #define RFH_GEN_CFG_RB_CHUNK_SIZE_128 1 481 #define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0 482 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM_MASK 0xF00 483 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS 8 484 485 #define DEFAULT_RXQ_NUM 0 486 487 /* end of 9000 rx series registers */ 488 489 /* TFDB Area - TFDs buffer table */ 490 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 491 #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 492 #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 493 #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 494 #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 495 496 /** 497 * Transmit DMA Channel Control/Status Registers (TCSR) 498 * 499 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 500 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 501 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 502 * 503 * To use a Tx DMA channel, driver must initialize its 504 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 505 * 506 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 507 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 508 * 509 * All other bits should be 0. 510 * 511 * Bit fields: 512 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 513 * '10' operate normally 514 * 29- 4: Reserved, set to "0" 515 * 3: Enable internal DMA requests (1, normal operation), disable (0) 516 * 2- 0: Reserved, set to "0" 517 */ 518 #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 519 #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) 520 521 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 522 #define FH_TCSR_CHNL_NUM (8) 523 524 /* TCSR: tx_config register values */ 525 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 526 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 527 #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 528 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 529 #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 530 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 531 532 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 533 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 534 535 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 536 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 537 538 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 539 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 540 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 541 542 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 543 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 544 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 545 546 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 547 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 548 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 549 550 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 551 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 552 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 553 554 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 555 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 556 557 /** 558 * Tx Shared Status Registers (TSSR) 559 * 560 * After stopping Tx DMA channel (writing 0 to 561 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 562 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 563 * (channel's buffers empty | no pending requests). 564 * 565 * Bit fields: 566 * 31-24: 1 = Channel buffers empty (channel 7:0) 567 * 23-16: 1 = No pending requests (channel 7:0) 568 */ 569 #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) 570 #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) 571 572 #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) 573 574 /** 575 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 576 * 31: Indicates an address error when accessed to internal memory 577 * uCode/driver must write "1" in order to clear this flag 578 * 30: Indicates that Host did not send the expected number of dwords to FH 579 * uCode/driver must write "1" in order to clear this flag 580 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 581 * command was received from the scheduler while the TRB was already full 582 * with previous command 583 * uCode/driver must write "1" in order to clear this flag 584 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 585 * bit is set, it indicates that the FH has received a full indication 586 * from the RTC TxFIFO and the current value of the TxCredit counter was 587 * not equal to zero. This mean that the credit mechanism was not 588 * synchronized to the TxFIFO status 589 * uCode/driver must write "1" in order to clear this flag 590 */ 591 #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) 592 #define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008) 593 594 #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 595 596 /* Tx service channels */ 597 #define FH_SRVC_CHNL (9) 598 #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) 599 #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 600 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 601 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 602 603 #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) 604 #define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4) 605 606 /* Instruct FH to increment the retry count of a packet when 607 * it is brought from the memory to TX-FIFO 608 */ 609 #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 610 611 #define MQ_RX_TABLE_SIZE 512 612 #define MQ_RX_TABLE_MASK (MQ_RX_TABLE_SIZE - 1) 613 #define MQ_RX_NUM_RBDS (MQ_RX_TABLE_SIZE - 1) 614 #define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \ 615 IWL_MAX_RX_HW_QUEUES * \ 616 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC)) 617 618 #define RX_QUEUE_SIZE 256 619 #define RX_QUEUE_MASK 255 620 #define RX_QUEUE_SIZE_LOG 8 621 622 /** 623 * struct iwl_rb_status - reserve buffer status 624 * host memory mapped FH registers 625 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 626 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 627 * @finished_rb_num [0:11] - Indicates the index of the current RB 628 * in which the last frame was written to 629 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 630 * which was transferred 631 */ 632 struct iwl_rb_status { 633 __le16 closed_rb_num; 634 __le16 closed_fr_num; 635 __le16 finished_rb_num; 636 __le16 finished_fr_nam; 637 __le32 __unused; 638 } __packed; 639 640 641 #define TFD_QUEUE_SIZE_MAX (256) 642 #define TFD_QUEUE_SIZE_BC_DUP (64) 643 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) 644 #define IWL_TX_DMA_MASK DMA_BIT_MASK(36) 645 #define IWL_NUM_OF_TBS 20 646 #define IWL_TFH_NUM_TBS 25 647 648 static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) 649 { 650 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; 651 } 652 /** 653 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor 654 * 655 * This structure contains dma address and length of transmission address 656 * 657 * @lo: low [31:0] portion of the dma address of TX buffer 658 * every even is unaligned on 16 bit boundary 659 * @hi_n_len 0-3 [35:32] portion of dma 660 * 4-15 length of the tx buffer 661 */ 662 struct iwl_tfd_tb { 663 __le32 lo; 664 __le16 hi_n_len; 665 } __packed; 666 667 /** 668 * struct iwl_tfh_tb transmit buffer descriptor within transmit frame descriptor 669 * 670 * This structure contains dma address and length of transmission address 671 * 672 * @tb_len length of the tx buffer 673 * @addr 64 bits dma address 674 */ 675 struct iwl_tfh_tb { 676 __le16 tb_len; 677 __le64 addr; 678 } __packed; 679 680 /** 681 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 682 * Both driver and device share these circular buffers, each of which must be 683 * contiguous 256 TFDs. 684 * For pre a000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes 685 * For a000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes 686 * 687 * Driver must indicate the physical address of the base of each 688 * circular buffer via the FH_MEM_CBBC_QUEUE registers. 689 * 690 * Each TFD contains pointer/size information for up to 20 / 25 data buffers 691 * in host DRAM. These buffers collectively contain the (one) frame described 692 * by the TFD. Each buffer must be a single contiguous block of memory within 693 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 694 * of (4K - 4). The concatenates all of a TFD's buffers into a single 695 * Tx frame, up to 8 KBytes in size. 696 * 697 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 698 */ 699 700 /** 701 * struct iwl_tfd - Transmit Frame Descriptor (TFD) 702 * @ __reserved1[3] reserved 703 * @ num_tbs 0-4 number of active tbs 704 * 5 reserved 705 * 6-7 padding (not used) 706 * @ tbs[20] transmit frame buffer descriptors 707 * @ __pad padding 708 */ 709 struct iwl_tfd { 710 u8 __reserved1[3]; 711 u8 num_tbs; 712 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; 713 __le32 __pad; 714 } __packed; 715 716 /** 717 * struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD) 718 * @ num_tbs 0-4 number of active tbs 719 * 5 -15 reserved 720 * @ tbs[25] transmit frame buffer descriptors 721 * @ __pad padding 722 */ 723 struct iwl_tfh_tfd { 724 __le16 num_tbs; 725 struct iwl_tfh_tb tbs[IWL_TFH_NUM_TBS]; 726 __le32 __pad; 727 } __packed; 728 729 /* Keep Warm Size */ 730 #define IWL_KW_SIZE 0x1000 /* 4k */ 731 732 /* Fixed (non-configurable) rx data from phy */ 733 734 /** 735 * struct iwlagn_schedq_bc_tbl scheduler byte count table 736 * base physical address provided by SCD_DRAM_BASE_ADDR 737 * For devices up to a000: 738 * @tfd_offset 0-12 - tx command byte count 739 * 12-16 - station index 740 * For a000 and on: 741 * @tfd_offset 0-12 - tx command byte count 742 * 12-13 - number of 64 byte chunks 743 * 14-16 - reserved 744 */ 745 struct iwlagn_scd_bc_tbl { 746 __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; 747 } __packed; 748 749 #endif /* !__iwl_fh_h__ */ 750