1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 23 * USA 24 * 25 * The full GNU General Public License is included in this distribution 26 * in the file called COPYING. 27 * 28 * Contact Information: 29 * Intel Linux Wireless <linuxwifi@intel.com> 30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 31 * 32 * BSD LICENSE 33 * 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 35 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 42 * * Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * * Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in 46 * the documentation and/or other materials provided with the 47 * distribution. 48 * * Neither the name Intel Corporation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 *****************************************************************************/ 65 #ifndef __iwl_fh_h__ 66 #define __iwl_fh_h__ 67 68 #include <linux/types.h> 69 70 /****************************/ 71 /* Flow Handler Definitions */ 72 /****************************/ 73 74 /** 75 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 76 * Addresses are offsets from device's PCI hardware base address. 77 */ 78 #define FH_MEM_LOWER_BOUND (0x1000) 79 #define FH_MEM_UPPER_BOUND (0x2000) 80 #define TFH_MEM_LOWER_BOUND (0xA06000) 81 82 /** 83 * Keep-Warm (KW) buffer base address. 84 * 85 * Driver must allocate a 4KByte buffer that is for keeping the 86 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 87 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 88 * from going into a power-savings mode that would cause higher DRAM latency, 89 * and possible data over/under-runs, before all Tx/Rx is complete. 90 * 91 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 92 * of the buffer, which must be 4K aligned. Once this is set up, the device 93 * automatically invokes keep-warm accesses when normal accesses might not 94 * be sufficient to maintain fast DRAM response. 95 * 96 * Bit fields: 97 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 98 */ 99 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 100 101 102 /** 103 * TFD Circular Buffers Base (CBBC) addresses 104 * 105 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 106 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 107 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 108 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 109 * aligned (address bits 0-7 must be 0). 110 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 111 * for them are in different places. 112 * 113 * Bit fields in each pointer register: 114 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 115 */ 116 #define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 117 #define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 118 #define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0) 119 #define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 120 #define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20) 121 #define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 122 /* a000 TFD table address, 64 bit */ 123 #define TFH_TFDQ_CBB_TABLE (TFH_MEM_LOWER_BOUND + 0x1C00) 124 125 /* Find TFD CB base pointer for given queue */ 126 static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans, 127 unsigned int chnl) 128 { 129 if (trans->cfg->use_tfh) { 130 WARN_ON_ONCE(chnl >= 64); 131 return TFH_TFDQ_CBB_TABLE + 8 * chnl; 132 } 133 if (chnl < 16) 134 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 135 if (chnl < 20) 136 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 137 WARN_ON_ONCE(chnl >= 32); 138 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 139 } 140 141 /* a000 configuration registers */ 142 143 /* 144 * TFH Configuration register. 145 * 146 * BIT fields: 147 * 148 * Bits 3:0: 149 * Define the maximum number of pending read requests. 150 * Maximum configration value allowed is 0xC 151 * Bits 9:8: 152 * Define the maximum transfer size. (64 / 128 / 256) 153 * Bit 10: 154 * When bit is set and transfer size is set to 128B, the TFH will enable 155 * reading chunks of more than 64B only if the read address is aligned to 128B. 156 * In case of DRAM read address which is not aligned to 128B, the TFH will 157 * enable transfer size which doesn't cross 64B DRAM address boundary. 158 */ 159 #define TFH_TRANSFER_MODE (TFH_MEM_LOWER_BOUND + 0x1F40) 160 #define TFH_TRANSFER_MAX_PENDING_REQ 0xc 161 #define TFH_CHUNK_SIZE_128 BIT(8) 162 #define TFH_CHUNK_SPLIT_MODE BIT(10) 163 /* 164 * Defines the offset address in dwords referring from the beginning of the 165 * Tx CMD which will be updated in DRAM. 166 * Note that the TFH offset address for Tx CMD update is always referring to 167 * the start of the TFD first TB. 168 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 169 */ 170 #define TFH_TXCMD_UPDATE_CFG (TFH_MEM_LOWER_BOUND + 0x1F48) 171 /* 172 * Controls TX DMA operation 173 * 174 * BIT fields: 175 * 176 * Bits 31:30: Enable the SRAM DMA channel. 177 * Turning on bit 31 will kick the SRAM2DRAM DMA. 178 * Note that the sram2dram may be enabled only after configuring the DRAM and 179 * SRAM addresses registers and the byte count register. 180 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 181 * set to 1 - interrupt is sent to the driver 182 * Bit 0: Indicates the snoop configuration 183 */ 184 #define TFH_SRV_DMA_CHNL0_CTRL (TFH_MEM_LOWER_BOUND + 0x1F60) 185 #define TFH_SRV_DMA_SNOOP BIT(0) 186 #define TFH_SRV_DMA_TO_DRIVER BIT(24) 187 #define TFH_SRV_DMA_START BIT(31) 188 189 /* Defines the DMA SRAM write start address to transfer a data block */ 190 #define TFH_SRV_DMA_CHNL0_SRAM_ADDR (TFH_MEM_LOWER_BOUND + 0x1F64) 191 192 /* Defines the 64bits DRAM start address to read the DMA data block from */ 193 #define TFH_SRV_DMA_CHNL0_DRAM_ADDR (TFH_MEM_LOWER_BOUND + 0x1F68) 194 195 /* 196 * Defines the number of bytes to transfer from DRAM to SRAM. 197 * Note that this register may be configured with non-dword aligned size. 198 */ 199 #define TFH_SRV_DMA_CHNL0_BC (TFH_MEM_LOWER_BOUND + 0x1F70) 200 201 /** 202 * Rx SRAM Control and Status Registers (RSCSR) 203 * 204 * These registers provide handshake between driver and device for the Rx queue 205 * (this queue handles *all* command responses, notifications, Rx data, etc. 206 * sent from uCode to host driver). Unlike Tx, there is only one Rx 207 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 208 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 209 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 210 * mapping between RBDs and RBs. 211 * 212 * Driver must allocate host DRAM memory for the following, and set the 213 * physical address of each into device registers: 214 * 215 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 216 * entries (although any power of 2, up to 4096, is selectable by driver). 217 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 218 * (typically 4K, although 8K or 16K are also selectable by driver). 219 * Driver sets up RB size and number of RBDs in the CB via Rx config 220 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 221 * 222 * Bit fields within one RBD: 223 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 224 * 225 * Driver sets physical address [35:8] of base of RBD circular buffer 226 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 227 * 228 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 229 * (RBs) have been filled, via a "write pointer", actually the index of 230 * the RB's corresponding RBD within the circular buffer. Driver sets 231 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 232 * 233 * Bit fields in lower dword of Rx status buffer (upper dword not used 234 * by driver: 235 * 31-12: Not used by driver 236 * 11- 0: Index of last filled Rx buffer descriptor 237 * (device writes, driver reads this value) 238 * 239 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 240 * enter pointers to these RBs into contiguous RBD circular buffer entries, 241 * and update the device's "write" index register, 242 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 243 * 244 * This "write" index corresponds to the *next* RBD that the driver will make 245 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 246 * the circular buffer. This value should initially be 0 (before preparing any 247 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 248 * wrap back to 0 at the end of the circular buffer (but don't wrap before 249 * "read" index has advanced past 1! See below). 250 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 251 * 252 * As the device fills RBs (referenced from contiguous RBDs within the circular 253 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 254 * to tell the driver the index of the latest filled RBD. The driver must 255 * read this "read" index from DRAM after receiving an Rx interrupt from device 256 * 257 * The driver must also internally keep track of a third index, which is the 258 * next RBD to process. When receiving an Rx interrupt, driver should process 259 * all filled but unprocessed RBs up to, but not including, the RB 260 * corresponding to the "read" index. For example, if "read" index becomes "1", 261 * driver may process the RB pointed to by RBD 0. Depending on volume of 262 * traffic, there may be many RBs to process. 263 * 264 * If read index == write index, device thinks there is no room to put new data. 265 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 266 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 267 * and "read" indexes; that is, make sure that there are no more than 254 268 * buffers waiting to be filled. 269 */ 270 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 271 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 272 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 273 274 /** 275 * Physical base address of 8-byte Rx Status buffer. 276 * Bit fields: 277 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 278 */ 279 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 280 281 /** 282 * Physical base address of Rx Buffer Descriptor Circular Buffer. 283 * Bit fields: 284 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 285 */ 286 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 287 288 /** 289 * Rx write pointer (index, really!). 290 * Bit fields: 291 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 292 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 293 */ 294 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 295 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 296 297 #define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 298 #define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 299 300 /** 301 * Rx Config/Status Registers (RCSR) 302 * Rx Config Reg for channel 0 (only channel used) 303 * 304 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 305 * normal operation (see bit fields). 306 * 307 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 308 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 309 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 310 * 311 * Bit fields: 312 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 313 * '10' operate normally 314 * 29-24: reserved 315 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 316 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 317 * 19-18: reserved 318 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 319 * '10' 12K, '11' 16K. 320 * 15-14: reserved 321 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 322 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 323 * typical value 0x10 (about 1/2 msec) 324 * 3- 0: reserved 325 */ 326 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 327 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 328 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 329 330 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 331 #define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8) 332 #define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10) 333 334 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 335 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 336 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 337 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 338 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 339 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 340 341 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 342 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 343 #define RX_RB_TIMEOUT (0x11) 344 345 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 346 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 347 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 348 349 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 350 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 351 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 352 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 353 354 #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 355 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 356 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 357 358 /** 359 * Rx Shared Status Registers (RSSR) 360 * 361 * After stopping Rx DMA channel (writing 0 to 362 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 363 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 364 * 365 * Bit fields: 366 * 24: 1 = Channel 0 is idle 367 * 368 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 369 * contain default values that should not be altered by the driver. 370 */ 371 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 372 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 373 374 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 375 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 376 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 377 (FH_MEM_RSSR_LOWER_BOUND + 0x008) 378 379 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 380 381 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 382 #define FH_MEM_TB_MAX_LENGTH (0x00020000) 383 384 /* 9000 rx series registers */ 385 386 #define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 387 #define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 388 /* Write index table */ 389 #define RFH_Q0_FRBDCB_WIDX 0xA08080 390 #define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4) 391 /* Write index table - shadow registers */ 392 #define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 393 #define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 394 /* Read index table */ 395 #define RFH_Q0_FRBDCB_RIDX 0xA080C0 396 #define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4) 397 /* Used list table */ 398 #define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 399 #define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8) 400 /* Write index table */ 401 #define RFH_Q0_URBDCB_WIDX 0xA08180 402 #define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4) 403 #define RFH_Q0_URBDCB_VAID 0xA081C0 404 #define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4) 405 /* stts */ 406 #define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 407 #define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 408 409 #define RFH_Q0_ORB_WPTR_LSB 0xA08280 410 #define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8) 411 #define RFH_RBDBUF_RBD0_LSB 0xA08300 412 #define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8) 413 414 /** 415 * RFH Status Register 416 * 417 * Bit fields: 418 * 419 * Bit 29: RBD_FETCH_IDLE 420 * This status flag is set by the RFH when there is no active RBD fetch from 421 * DRAM. 422 * Once the RFH RBD controller starts fetching (or when there is a pending 423 * RBD read response from DRAM), this flag is immediately turned off. 424 * 425 * Bit 30: SRAM_DMA_IDLE 426 * This status flag is set by the RFH when there is no active transaction from 427 * SRAM to DRAM. 428 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 429 * 430 * Bit 31: RXF_DMA_IDLE 431 * This status flag is set by the RFH when there is no active transaction from 432 * RXF to DRAM. 433 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 434 */ 435 #define RFH_GEN_STATUS 0xA09808 436 #define RBD_FETCH_IDLE BIT(29) 437 #define SRAM_DMA_IDLE BIT(30) 438 #define RXF_DMA_IDLE BIT(31) 439 440 /* DMA configuration */ 441 #define RFH_RXF_DMA_CFG 0xA09820 442 /* RB size */ 443 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 444 #define RFH_RXF_DMA_RB_SIZE_POS 16 445 #define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS) 446 #define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS) 447 #define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS) 448 #define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS) 449 #define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS) 450 #define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS) 451 #define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS) 452 #define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS) 453 #define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS) 454 #define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS) 455 /* RB Circular Buffer size:defines the table sizes in RBD units */ 456 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 457 #define RFH_RXF_DMA_RBDCB_SIZE_POS 20 458 #define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS) 459 #define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS) 460 #define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS) 461 #define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 462 #define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 463 #define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS) 464 #define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS) 465 #define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS) 466 #define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS) 467 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 468 #define RFH_RXF_DMA_MIN_RB_SIZE_POS 24 469 #define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS) 470 #define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 471 #define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 472 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 473 #define RFH_DMA_EN_ENABLE_VAL BIT(31) 474 475 #define RFH_RXF_RXQ_ACTIVE 0xA0980C 476 477 #define RFH_GEN_CFG 0xA09800 478 #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0) 479 #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1) 480 #define RFH_GEN_CFG_RB_CHUNK_SIZE_POS 4 481 #define RFH_GEN_CFG_RB_CHUNK_SIZE_128 1 482 #define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0 483 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM_MASK 0xF00 484 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS 8 485 486 #define DEFAULT_RXQ_NUM 0 487 488 /* end of 9000 rx series registers */ 489 490 /* TFDB Area - TFDs buffer table */ 491 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 492 #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 493 #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 494 #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 495 #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 496 497 /** 498 * Transmit DMA Channel Control/Status Registers (TCSR) 499 * 500 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 501 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 502 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 503 * 504 * To use a Tx DMA channel, driver must initialize its 505 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 506 * 507 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 508 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 509 * 510 * All other bits should be 0. 511 * 512 * Bit fields: 513 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 514 * '10' operate normally 515 * 29- 4: Reserved, set to "0" 516 * 3: Enable internal DMA requests (1, normal operation), disable (0) 517 * 2- 0: Reserved, set to "0" 518 */ 519 #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 520 #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) 521 522 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 523 #define FH_TCSR_CHNL_NUM (8) 524 525 /* TCSR: tx_config register values */ 526 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 527 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 528 #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 529 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 530 #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 531 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 532 533 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 534 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 535 536 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 537 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 538 539 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 540 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 541 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 542 543 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 544 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 545 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 546 547 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 548 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 549 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 550 551 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 552 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 553 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 554 555 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 556 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 557 558 /** 559 * Tx Shared Status Registers (TSSR) 560 * 561 * After stopping Tx DMA channel (writing 0 to 562 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 563 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 564 * (channel's buffers empty | no pending requests). 565 * 566 * Bit fields: 567 * 31-24: 1 = Channel buffers empty (channel 7:0) 568 * 23-16: 1 = No pending requests (channel 7:0) 569 */ 570 #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) 571 #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) 572 573 #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) 574 575 /** 576 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 577 * 31: Indicates an address error when accessed to internal memory 578 * uCode/driver must write "1" in order to clear this flag 579 * 30: Indicates that Host did not send the expected number of dwords to FH 580 * uCode/driver must write "1" in order to clear this flag 581 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 582 * command was received from the scheduler while the TRB was already full 583 * with previous command 584 * uCode/driver must write "1" in order to clear this flag 585 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 586 * bit is set, it indicates that the FH has received a full indication 587 * from the RTC TxFIFO and the current value of the TxCredit counter was 588 * not equal to zero. This mean that the credit mechanism was not 589 * synchronized to the TxFIFO status 590 * uCode/driver must write "1" in order to clear this flag 591 */ 592 #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) 593 #define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008) 594 595 #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 596 597 /* Tx service channels */ 598 #define FH_SRVC_CHNL (9) 599 #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) 600 #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 601 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 602 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 603 604 #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) 605 #define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4) 606 607 /* Instruct FH to increment the retry count of a packet when 608 * it is brought from the memory to TX-FIFO 609 */ 610 #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 611 612 #define MQ_RX_TABLE_SIZE 512 613 #define MQ_RX_TABLE_MASK (MQ_RX_TABLE_SIZE - 1) 614 #define MQ_RX_NUM_RBDS (MQ_RX_TABLE_SIZE - 1) 615 #define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \ 616 IWL_MAX_RX_HW_QUEUES * \ 617 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC)) 618 619 #define RX_QUEUE_SIZE 256 620 #define RX_QUEUE_MASK 255 621 #define RX_QUEUE_SIZE_LOG 8 622 623 /** 624 * struct iwl_rb_status - reserve buffer status 625 * host memory mapped FH registers 626 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 627 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 628 * @finished_rb_num [0:11] - Indicates the index of the current RB 629 * in which the last frame was written to 630 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 631 * which was transferred 632 */ 633 struct iwl_rb_status { 634 __le16 closed_rb_num; 635 __le16 closed_fr_num; 636 __le16 finished_rb_num; 637 __le16 finished_fr_nam; 638 __le32 __unused; 639 } __packed; 640 641 642 #define TFD_QUEUE_SIZE_MAX (256) 643 #define TFD_QUEUE_SIZE_BC_DUP (64) 644 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) 645 #define IWL_TX_DMA_MASK DMA_BIT_MASK(36) 646 #define IWL_NUM_OF_TBS 20 647 648 static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) 649 { 650 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; 651 } 652 /** 653 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor 654 * 655 * This structure contains dma address and length of transmission address 656 * 657 * @lo: low [31:0] portion of the dma address of TX buffer 658 * every even is unaligned on 16 bit boundary 659 * @hi_n_len 0-3 [35:32] portion of dma 660 * 4-15 length of the tx buffer 661 */ 662 struct iwl_tfd_tb { 663 __le32 lo; 664 __le16 hi_n_len; 665 } __packed; 666 667 /** 668 * struct iwl_tfd 669 * 670 * Transmit Frame Descriptor (TFD) 671 * 672 * @ __reserved1[3] reserved 673 * @ num_tbs 0-4 number of active tbs 674 * 5 reserved 675 * 6-7 padding (not used) 676 * @ tbs[20] transmit frame buffer descriptors 677 * @ __pad padding 678 * 679 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 680 * Both driver and device share these circular buffers, each of which must be 681 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 682 * 683 * Driver must indicate the physical address of the base of each 684 * circular buffer via the FH_MEM_CBBC_QUEUE registers. 685 * 686 * Each TFD contains pointer/size information for up to 20 data buffers 687 * in host DRAM. These buffers collectively contain the (one) frame described 688 * by the TFD. Each buffer must be a single contiguous block of memory within 689 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 690 * of (4K - 4). The concatenates all of a TFD's buffers into a single 691 * Tx frame, up to 8 KBytes in size. 692 * 693 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 694 */ 695 struct iwl_tfd { 696 u8 __reserved1[3]; 697 u8 num_tbs; 698 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; 699 __le32 __pad; 700 } __packed; 701 702 /* Keep Warm Size */ 703 #define IWL_KW_SIZE 0x1000 /* 4k */ 704 705 /* Fixed (non-configurable) rx data from phy */ 706 707 /** 708 * struct iwlagn_schedq_bc_tbl scheduler byte count table 709 * base physical address provided by SCD_DRAM_BASE_ADDR 710 * @tfd_offset 0-12 - tx command byte count 711 * 12-16 - station index 712 */ 713 struct iwlagn_scd_bc_tbl { 714 __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; 715 } __packed; 716 717 #endif /* !__iwl_fh_h__ */ 718