1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 23 * USA 24 * 25 * The full GNU General Public License is included in this distribution 26 * in the file called COPYING. 27 * 28 * Contact Information: 29 * Intel Linux Wireless <linuxwifi@intel.com> 30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 31 * 32 * BSD LICENSE 33 * 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 35 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 42 * * Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * * Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in 46 * the documentation and/or other materials provided with the 47 * distribution. 48 * * Neither the name Intel Corporation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 *****************************************************************************/ 65 #ifndef __iwl_fh_h__ 66 #define __iwl_fh_h__ 67 68 #include <linux/types.h> 69 #include <linux/bitfield.h> 70 71 /****************************/ 72 /* Flow Handler Definitions */ 73 /****************************/ 74 75 /** 76 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 77 * Addresses are offsets from device's PCI hardware base address. 78 */ 79 #define FH_MEM_LOWER_BOUND (0x1000) 80 #define FH_MEM_UPPER_BOUND (0x2000) 81 #define FH_MEM_LOWER_BOUND_GEN2 (0xa06000) 82 #define FH_MEM_UPPER_BOUND_GEN2 (0xa08000) 83 84 /** 85 * Keep-Warm (KW) buffer base address. 86 * 87 * Driver must allocate a 4KByte buffer that is for keeping the 88 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 89 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 90 * from going into a power-savings mode that would cause higher DRAM latency, 91 * and possible data over/under-runs, before all Tx/Rx is complete. 92 * 93 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 94 * of the buffer, which must be 4K aligned. Once this is set up, the device 95 * automatically invokes keep-warm accesses when normal accesses might not 96 * be sufficient to maintain fast DRAM response. 97 * 98 * Bit fields: 99 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 100 */ 101 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 102 103 104 /** 105 * TFD Circular Buffers Base (CBBC) addresses 106 * 107 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 108 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 109 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 110 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 111 * aligned (address bits 0-7 must be 0). 112 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 113 * for them are in different places. 114 * 115 * Bit fields in each pointer register: 116 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 117 */ 118 #define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 119 #define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 120 #define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0) 121 #define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 122 #define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20) 123 #define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 124 /* 22000 TFD table address, 64 bit */ 125 #define TFH_TFDQ_CBB_TABLE (0x1C00) 126 127 /* Find TFD CB base pointer for given queue */ 128 static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans, 129 unsigned int chnl) 130 { 131 if (trans->cfg->use_tfh) { 132 WARN_ON_ONCE(chnl >= 64); 133 return TFH_TFDQ_CBB_TABLE + 8 * chnl; 134 } 135 if (chnl < 16) 136 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 137 if (chnl < 20) 138 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 139 WARN_ON_ONCE(chnl >= 32); 140 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 141 } 142 143 /* 22000 configuration registers */ 144 145 /* 146 * TFH Configuration register. 147 * 148 * BIT fields: 149 * 150 * Bits 3:0: 151 * Define the maximum number of pending read requests. 152 * Maximum configration value allowed is 0xC 153 * Bits 9:8: 154 * Define the maximum transfer size. (64 / 128 / 256) 155 * Bit 10: 156 * When bit is set and transfer size is set to 128B, the TFH will enable 157 * reading chunks of more than 64B only if the read address is aligned to 128B. 158 * In case of DRAM read address which is not aligned to 128B, the TFH will 159 * enable transfer size which doesn't cross 64B DRAM address boundary. 160 */ 161 #define TFH_TRANSFER_MODE (0x1F40) 162 #define TFH_TRANSFER_MAX_PENDING_REQ 0xc 163 #define TFH_CHUNK_SIZE_128 BIT(8) 164 #define TFH_CHUNK_SPLIT_MODE BIT(10) 165 /* 166 * Defines the offset address in dwords referring from the beginning of the 167 * Tx CMD which will be updated in DRAM. 168 * Note that the TFH offset address for Tx CMD update is always referring to 169 * the start of the TFD first TB. 170 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 171 */ 172 #define TFH_TXCMD_UPDATE_CFG (0x1F48) 173 /* 174 * Controls TX DMA operation 175 * 176 * BIT fields: 177 * 178 * Bits 31:30: Enable the SRAM DMA channel. 179 * Turning on bit 31 will kick the SRAM2DRAM DMA. 180 * Note that the sram2dram may be enabled only after configuring the DRAM and 181 * SRAM addresses registers and the byte count register. 182 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 183 * set to 1 - interrupt is sent to the driver 184 * Bit 0: Indicates the snoop configuration 185 */ 186 #define TFH_SRV_DMA_CHNL0_CTRL (0x1F60) 187 #define TFH_SRV_DMA_SNOOP BIT(0) 188 #define TFH_SRV_DMA_TO_DRIVER BIT(24) 189 #define TFH_SRV_DMA_START BIT(31) 190 191 /* Defines the DMA SRAM write start address to transfer a data block */ 192 #define TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) 193 194 /* Defines the 64bits DRAM start address to read the DMA data block from */ 195 #define TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) 196 197 /* 198 * Defines the number of bytes to transfer from DRAM to SRAM. 199 * Note that this register may be configured with non-dword aligned size. 200 */ 201 #define TFH_SRV_DMA_CHNL0_BC (0x1F70) 202 203 /** 204 * Rx SRAM Control and Status Registers (RSCSR) 205 * 206 * These registers provide handshake between driver and device for the Rx queue 207 * (this queue handles *all* command responses, notifications, Rx data, etc. 208 * sent from uCode to host driver). Unlike Tx, there is only one Rx 209 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 210 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 211 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 212 * mapping between RBDs and RBs. 213 * 214 * Driver must allocate host DRAM memory for the following, and set the 215 * physical address of each into device registers: 216 * 217 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 218 * entries (although any power of 2, up to 4096, is selectable by driver). 219 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 220 * (typically 4K, although 8K or 16K are also selectable by driver). 221 * Driver sets up RB size and number of RBDs in the CB via Rx config 222 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 223 * 224 * Bit fields within one RBD: 225 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 226 * 227 * Driver sets physical address [35:8] of base of RBD circular buffer 228 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 229 * 230 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 231 * (RBs) have been filled, via a "write pointer", actually the index of 232 * the RB's corresponding RBD within the circular buffer. Driver sets 233 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 234 * 235 * Bit fields in lower dword of Rx status buffer (upper dword not used 236 * by driver: 237 * 31-12: Not used by driver 238 * 11- 0: Index of last filled Rx buffer descriptor 239 * (device writes, driver reads this value) 240 * 241 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 242 * enter pointers to these RBs into contiguous RBD circular buffer entries, 243 * and update the device's "write" index register, 244 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 245 * 246 * This "write" index corresponds to the *next* RBD that the driver will make 247 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 248 * the circular buffer. This value should initially be 0 (before preparing any 249 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 250 * wrap back to 0 at the end of the circular buffer (but don't wrap before 251 * "read" index has advanced past 1! See below). 252 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 253 * 254 * As the device fills RBs (referenced from contiguous RBDs within the circular 255 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 256 * to tell the driver the index of the latest filled RBD. The driver must 257 * read this "read" index from DRAM after receiving an Rx interrupt from device 258 * 259 * The driver must also internally keep track of a third index, which is the 260 * next RBD to process. When receiving an Rx interrupt, driver should process 261 * all filled but unprocessed RBs up to, but not including, the RB 262 * corresponding to the "read" index. For example, if "read" index becomes "1", 263 * driver may process the RB pointed to by RBD 0. Depending on volume of 264 * traffic, there may be many RBs to process. 265 * 266 * If read index == write index, device thinks there is no room to put new data. 267 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 268 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 269 * and "read" indexes; that is, make sure that there are no more than 254 270 * buffers waiting to be filled. 271 */ 272 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 273 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 274 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 275 276 /** 277 * Physical base address of 8-byte Rx Status buffer. 278 * Bit fields: 279 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 280 */ 281 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 282 283 /** 284 * Physical base address of Rx Buffer Descriptor Circular Buffer. 285 * Bit fields: 286 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 287 */ 288 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 289 290 /** 291 * Rx write pointer (index, really!). 292 * Bit fields: 293 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 294 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 295 */ 296 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 297 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 298 299 #define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 300 #define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 301 302 /** 303 * Rx Config/Status Registers (RCSR) 304 * Rx Config Reg for channel 0 (only channel used) 305 * 306 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 307 * normal operation (see bit fields). 308 * 309 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 310 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 311 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 312 * 313 * Bit fields: 314 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 315 * '10' operate normally 316 * 29-24: reserved 317 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 318 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 319 * 19-18: reserved 320 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 321 * '10' 12K, '11' 16K. 322 * 15-14: reserved 323 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 324 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 325 * typical value 0x10 (about 1/2 msec) 326 * 3- 0: reserved 327 */ 328 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 329 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 330 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 331 332 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 333 #define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8) 334 #define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10) 335 336 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 337 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 338 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 339 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 340 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 341 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 342 343 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 344 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 345 #define RX_RB_TIMEOUT (0x11) 346 347 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 348 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 349 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 350 351 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 352 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 353 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 354 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 355 356 #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 357 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 358 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 359 360 /** 361 * Rx Shared Status Registers (RSSR) 362 * 363 * After stopping Rx DMA channel (writing 0 to 364 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 365 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 366 * 367 * Bit fields: 368 * 24: 1 = Channel 0 is idle 369 * 370 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 371 * contain default values that should not be altered by the driver. 372 */ 373 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 374 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 375 376 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 377 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 378 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 379 (FH_MEM_RSSR_LOWER_BOUND + 0x008) 380 381 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 382 383 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 384 #define FH_MEM_TB_MAX_LENGTH (0x00020000) 385 386 /* 9000 rx series registers */ 387 388 #define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 389 #define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 390 /* Write index table */ 391 #define RFH_Q0_FRBDCB_WIDX 0xA08080 392 #define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4) 393 /* Write index table - shadow registers */ 394 #define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 395 #define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 396 /* Read index table */ 397 #define RFH_Q0_FRBDCB_RIDX 0xA080C0 398 #define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4) 399 /* Used list table */ 400 #define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 401 #define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8) 402 /* Write index table */ 403 #define RFH_Q0_URBDCB_WIDX 0xA08180 404 #define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4) 405 #define RFH_Q0_URBDCB_VAID 0xA081C0 406 #define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4) 407 /* stts */ 408 #define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 409 #define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 410 411 #define RFH_Q0_ORB_WPTR_LSB 0xA08280 412 #define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8) 413 #define RFH_RBDBUF_RBD0_LSB 0xA08300 414 #define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8) 415 416 /** 417 * RFH Status Register 418 * 419 * Bit fields: 420 * 421 * Bit 29: RBD_FETCH_IDLE 422 * This status flag is set by the RFH when there is no active RBD fetch from 423 * DRAM. 424 * Once the RFH RBD controller starts fetching (or when there is a pending 425 * RBD read response from DRAM), this flag is immediately turned off. 426 * 427 * Bit 30: SRAM_DMA_IDLE 428 * This status flag is set by the RFH when there is no active transaction from 429 * SRAM to DRAM. 430 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 431 * 432 * Bit 31: RXF_DMA_IDLE 433 * This status flag is set by the RFH when there is no active transaction from 434 * RXF to DRAM. 435 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 436 */ 437 #define RFH_GEN_STATUS 0xA09808 438 #define RBD_FETCH_IDLE BIT(29) 439 #define SRAM_DMA_IDLE BIT(30) 440 #define RXF_DMA_IDLE BIT(31) 441 442 /* DMA configuration */ 443 #define RFH_RXF_DMA_CFG 0xA09820 444 /* RB size */ 445 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 446 #define RFH_RXF_DMA_RB_SIZE_POS 16 447 #define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS) 448 #define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS) 449 #define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS) 450 #define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS) 451 #define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS) 452 #define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS) 453 #define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS) 454 #define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS) 455 #define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS) 456 #define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS) 457 /* RB Circular Buffer size:defines the table sizes in RBD units */ 458 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 459 #define RFH_RXF_DMA_RBDCB_SIZE_POS 20 460 #define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS) 461 #define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS) 462 #define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS) 463 #define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 464 #define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 465 #define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS) 466 #define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS) 467 #define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS) 468 #define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS) 469 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 470 #define RFH_RXF_DMA_MIN_RB_SIZE_POS 24 471 #define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS) 472 #define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 473 #define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 474 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 475 #define RFH_DMA_EN_ENABLE_VAL BIT(31) 476 477 #define RFH_RXF_RXQ_ACTIVE 0xA0980C 478 479 #define RFH_GEN_CFG 0xA09800 480 #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0) 481 #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1) 482 #define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4) 483 #define RFH_GEN_CFG_RB_CHUNK_SIZE_128 1 484 #define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0 485 /* the driver assumes everywhere that the default RXQ is 0 */ 486 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 487 #define RFH_GEN_CFG_VAL(_n, _v) FIELD_PREP(RFH_GEN_CFG_ ## _n, _v) 488 489 /* end of 9000 rx series registers */ 490 491 /* TFDB Area - TFDs buffer table */ 492 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 493 #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 494 #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 495 #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 496 #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 497 498 /** 499 * Transmit DMA Channel Control/Status Registers (TCSR) 500 * 501 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 502 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 503 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 504 * 505 * To use a Tx DMA channel, driver must initialize its 506 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 507 * 508 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 509 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 510 * 511 * All other bits should be 0. 512 * 513 * Bit fields: 514 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 515 * '10' operate normally 516 * 29- 4: Reserved, set to "0" 517 * 3: Enable internal DMA requests (1, normal operation), disable (0) 518 * 2- 0: Reserved, set to "0" 519 */ 520 #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 521 #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) 522 523 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 524 #define FH_TCSR_CHNL_NUM (8) 525 526 /* TCSR: tx_config register values */ 527 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 528 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 529 #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 530 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 531 #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 532 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 533 534 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 535 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 536 537 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 538 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 539 540 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 541 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 542 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 543 544 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 545 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 546 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 547 548 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 549 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 550 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 551 552 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 553 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 554 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 555 556 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 557 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 558 559 /** 560 * Tx Shared Status Registers (TSSR) 561 * 562 * After stopping Tx DMA channel (writing 0 to 563 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 564 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 565 * (channel's buffers empty | no pending requests). 566 * 567 * Bit fields: 568 * 31-24: 1 = Channel buffers empty (channel 7:0) 569 * 23-16: 1 = No pending requests (channel 7:0) 570 */ 571 #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) 572 #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) 573 574 #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) 575 576 /** 577 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 578 * 31: Indicates an address error when accessed to internal memory 579 * uCode/driver must write "1" in order to clear this flag 580 * 30: Indicates that Host did not send the expected number of dwords to FH 581 * uCode/driver must write "1" in order to clear this flag 582 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 583 * command was received from the scheduler while the TRB was already full 584 * with previous command 585 * uCode/driver must write "1" in order to clear this flag 586 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 587 * bit is set, it indicates that the FH has received a full indication 588 * from the RTC TxFIFO and the current value of the TxCredit counter was 589 * not equal to zero. This mean that the credit mechanism was not 590 * synchronized to the TxFIFO status 591 * uCode/driver must write "1" in order to clear this flag 592 */ 593 #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) 594 #define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008) 595 596 #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 597 598 /* Tx service channels */ 599 #define FH_SRVC_CHNL (9) 600 #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) 601 #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 602 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 603 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 604 605 #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) 606 #define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4) 607 608 /* Instruct FH to increment the retry count of a packet when 609 * it is brought from the memory to TX-FIFO 610 */ 611 #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 612 613 #define MQ_RX_TABLE_SIZE 512 614 #define MQ_RX_TABLE_MASK (MQ_RX_TABLE_SIZE - 1) 615 #define MQ_RX_NUM_RBDS (MQ_RX_TABLE_SIZE - 1) 616 #define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \ 617 IWL_MAX_RX_HW_QUEUES * \ 618 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC)) 619 /* cb size is the exponent */ 620 #define RX_QUEUE_CB_SIZE(x) ilog2(x) 621 622 #define RX_QUEUE_SIZE 256 623 #define RX_QUEUE_MASK 255 624 #define RX_QUEUE_SIZE_LOG 8 625 626 /** 627 * struct iwl_rb_status - reserve buffer status 628 * host memory mapped FH registers 629 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 630 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 631 * @finished_rb_num [0:11] - Indicates the index of the current RB 632 * in which the last frame was written to 633 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 634 * which was transferred 635 */ 636 struct iwl_rb_status { 637 __le16 closed_rb_num; 638 __le16 closed_fr_num; 639 __le16 finished_rb_num; 640 __le16 finished_fr_nam; 641 __le32 __unused; 642 } __packed; 643 644 645 #define TFD_QUEUE_SIZE_MAX (256) 646 /* cb size is the exponent - 3 */ 647 #define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3) 648 #define TFD_QUEUE_SIZE_BC_DUP (64) 649 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) 650 #define IWL_TX_DMA_MASK DMA_BIT_MASK(36) 651 #define IWL_NUM_OF_TBS 20 652 #define IWL_TFH_NUM_TBS 25 653 654 static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) 655 { 656 return (sizeof(addr) > sizeof(u32) ? upper_32_bits(addr) : 0) & 0xF; 657 } 658 659 /** 660 * enum iwl_tfd_tb_hi_n_len - TB hi_n_len bits 661 * @TB_HI_N_LEN_ADDR_HI_MSK: high 4 bits (to make it 36) of DMA address 662 * @TB_HI_N_LEN_LEN_MSK: length of the TB 663 */ 664 enum iwl_tfd_tb_hi_n_len { 665 TB_HI_N_LEN_ADDR_HI_MSK = 0xf, 666 TB_HI_N_LEN_LEN_MSK = 0xfff0, 667 }; 668 669 /** 670 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor 671 * 672 * This structure contains dma address and length of transmission address 673 * 674 * @lo: low [31:0] portion of the dma address of TX buffer 675 * every even is unaligned on 16 bit boundary 676 * @hi_n_len: &enum iwl_tfd_tb_hi_n_len 677 */ 678 struct iwl_tfd_tb { 679 __le32 lo; 680 __le16 hi_n_len; 681 } __packed; 682 683 /** 684 * struct iwl_tfh_tb transmit buffer descriptor within transmit frame descriptor 685 * 686 * This structure contains dma address and length of transmission address 687 * 688 * @tb_len length of the tx buffer 689 * @addr 64 bits dma address 690 */ 691 struct iwl_tfh_tb { 692 __le16 tb_len; 693 __le64 addr; 694 } __packed; 695 696 /** 697 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 698 * Both driver and device share these circular buffers, each of which must be 699 * contiguous 256 TFDs. 700 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes 701 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes 702 * 703 * Driver must indicate the physical address of the base of each 704 * circular buffer via the FH_MEM_CBBC_QUEUE registers. 705 * 706 * Each TFD contains pointer/size information for up to 20 / 25 data buffers 707 * in host DRAM. These buffers collectively contain the (one) frame described 708 * by the TFD. Each buffer must be a single contiguous block of memory within 709 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 710 * of (4K - 4). The concatenates all of a TFD's buffers into a single 711 * Tx frame, up to 8 KBytes in size. 712 * 713 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 714 */ 715 716 /** 717 * struct iwl_tfd - Transmit Frame Descriptor (TFD) 718 * @ __reserved1[3] reserved 719 * @ num_tbs 0-4 number of active tbs 720 * 5 reserved 721 * 6-7 padding (not used) 722 * @ tbs[20] transmit frame buffer descriptors 723 * @ __pad padding 724 */ 725 struct iwl_tfd { 726 u8 __reserved1[3]; 727 u8 num_tbs; 728 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; 729 __le32 __pad; 730 } __packed; 731 732 /** 733 * struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD) 734 * @ num_tbs 0-4 number of active tbs 735 * 5 -15 reserved 736 * @ tbs[25] transmit frame buffer descriptors 737 * @ __pad padding 738 */ 739 struct iwl_tfh_tfd { 740 __le16 num_tbs; 741 struct iwl_tfh_tb tbs[IWL_TFH_NUM_TBS]; 742 __le32 __pad; 743 } __packed; 744 745 /* Keep Warm Size */ 746 #define IWL_KW_SIZE 0x1000 /* 4k */ 747 748 /* Fixed (non-configurable) rx data from phy */ 749 750 /** 751 * struct iwlagn_schedq_bc_tbl scheduler byte count table 752 * base physical address provided by SCD_DRAM_BASE_ADDR 753 * For devices up to 22000: 754 * @tfd_offset 0-12 - tx command byte count 755 * 12-16 - station index 756 * For 22000 and on: 757 * @tfd_offset 0-12 - tx command byte count 758 * 12-13 - number of 64 byte chunks 759 * 14-16 - reserved 760 */ 761 struct iwlagn_scd_bc_tbl { 762 __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; 763 } __packed; 764 765 #endif /* !__iwl_fh_h__ */ 766