1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
4  */
5 #include <linux/types.h>
6 #include <linux/slab.h>
7 #include <linux/export.h>
8 
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-eeprom-read.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
15 
16 /*
17  * EEPROM access time values:
18  *
19  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
20  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
21  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
22  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
23  */
24 #define IWL_EEPROM_ACCESS_TIMEOUT	5000 /* uSec */
25 
26 #define IWL_EEPROM_SEM_TIMEOUT		10   /* microseconds */
27 #define IWL_EEPROM_SEM_RETRY_LIMIT	1000 /* number of attempts (not time) */
28 
29 
30 /*
31  * The device's EEPROM semaphore prevents conflicts between driver and uCode
32  * when accessing the EEPROM; each access is a series of pulses to/from the
33  * EEPROM chip, not a single event, so even reads could conflict if they
34  * weren't arbitrated by the semaphore.
35  */
36 
37 #define	EEPROM_SEM_TIMEOUT 10		/* milliseconds */
38 #define EEPROM_SEM_RETRY_LIMIT 1000	/* number of attempts (not time) */
39 
40 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
41 {
42 	u16 count;
43 	int ret;
44 
45 	for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
46 		/* Request semaphore */
47 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
48 			    CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
49 
50 		/* See if we got it */
51 		ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
52 				CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
53 				CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
54 				EEPROM_SEM_TIMEOUT);
55 		if (ret >= 0) {
56 			IWL_DEBUG_EEPROM(trans->dev,
57 					 "Acquired semaphore after %d tries.\n",
58 					 count+1);
59 			return ret;
60 		}
61 	}
62 
63 	return ret;
64 }
65 
66 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
67 {
68 	iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
69 		      CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
70 }
71 
72 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
73 {
74 	u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
75 
76 	IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
77 
78 	switch (gp) {
79 	case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
80 		if (!nvm_is_otp) {
81 			IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
82 				gp);
83 			return -ENOENT;
84 		}
85 		return 0;
86 	case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
87 	case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
88 		if (nvm_is_otp) {
89 			IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
90 			return -ENOENT;
91 		}
92 		return 0;
93 	case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
94 	default:
95 		IWL_ERR(trans,
96 			"bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
97 			nvm_is_otp ? "OTP" : "EEPROM", gp);
98 		return -ENOENT;
99 	}
100 }
101 
102 /******************************************************************************
103  *
104  * OTP related functions
105  *
106 ******************************************************************************/
107 
108 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
109 {
110 	iwl_read32(trans, CSR_OTP_GP_REG);
111 
112 	iwl_clear_bit(trans, CSR_OTP_GP_REG,
113 		      CSR_OTP_GP_REG_OTP_ACCESS_MODE);
114 }
115 
116 static int iwl_nvm_is_otp(struct iwl_trans *trans)
117 {
118 	u32 otpgp;
119 
120 	/* OTP only valid for CP/PP and after */
121 	switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
122 	case CSR_HW_REV_TYPE_NONE:
123 		IWL_ERR(trans, "Unknown hardware type\n");
124 		return -EIO;
125 	case CSR_HW_REV_TYPE_5300:
126 	case CSR_HW_REV_TYPE_5350:
127 	case CSR_HW_REV_TYPE_5100:
128 	case CSR_HW_REV_TYPE_5150:
129 		return 0;
130 	default:
131 		otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
132 		if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
133 			return 1;
134 		return 0;
135 	}
136 }
137 
138 static int iwl_init_otp_access(struct iwl_trans *trans)
139 {
140 	int ret;
141 
142 	ret = iwl_finish_nic_init(trans);
143 	if (ret)
144 		return ret;
145 
146 	iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
147 			  APMG_PS_CTRL_VAL_RESET_REQ);
148 	udelay(5);
149 	iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
150 			    APMG_PS_CTRL_VAL_RESET_REQ);
151 
152 	/*
153 	 * CSR auto clock gate disable bit -
154 	 * this is only applicable for HW with OTP shadow RAM
155 	 */
156 	if (trans->trans_cfg->base_params->shadow_ram_support)
157 		iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
158 			    CSR_RESET_LINK_PWR_MGMT_DISABLED);
159 
160 	return 0;
161 }
162 
163 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
164 			     __le16 *eeprom_data)
165 {
166 	int ret = 0;
167 	u32 r;
168 	u32 otpgp;
169 
170 	iwl_write32(trans, CSR_EEPROM_REG,
171 		    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
172 	ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
173 				 CSR_EEPROM_REG_READ_VALID_MSK,
174 				 CSR_EEPROM_REG_READ_VALID_MSK,
175 				 IWL_EEPROM_ACCESS_TIMEOUT);
176 	if (ret < 0) {
177 		IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
178 		return ret;
179 	}
180 	r = iwl_read32(trans, CSR_EEPROM_REG);
181 	/* check for ECC errors: */
182 	otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
183 	if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
184 		/* stop in this case */
185 		/* set the uncorrectable OTP ECC bit for acknowledgment */
186 		iwl_set_bit(trans, CSR_OTP_GP_REG,
187 			    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
188 		IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
189 		return -EINVAL;
190 	}
191 	if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
192 		/* continue in this case */
193 		/* set the correctable OTP ECC bit for acknowledgment */
194 		iwl_set_bit(trans, CSR_OTP_GP_REG,
195 			    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
196 		IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
197 	}
198 	*eeprom_data = cpu_to_le16(r >> 16);
199 	return 0;
200 }
201 
202 /*
203  * iwl_is_otp_empty: check for empty OTP
204  */
205 static bool iwl_is_otp_empty(struct iwl_trans *trans)
206 {
207 	u16 next_link_addr = 0;
208 	__le16 link_value;
209 	bool is_empty = false;
210 
211 	/* locate the beginning of OTP link list */
212 	if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
213 		if (!link_value) {
214 			IWL_ERR(trans, "OTP is empty\n");
215 			is_empty = true;
216 		}
217 	} else {
218 		IWL_ERR(trans, "Unable to read first block of OTP list.\n");
219 		is_empty = true;
220 	}
221 
222 	return is_empty;
223 }
224 
225 
226 /*
227  * iwl_find_otp_image: find EEPROM image in OTP
228  *   finding the OTP block that contains the EEPROM image.
229  *   the last valid block on the link list (the block _before_ the last block)
230  *   is the block we should read and used to configure the device.
231  *   If all the available OTP blocks are full, the last block will be the block
232  *   we should read and used to configure the device.
233  *   only perform this operation if shadow RAM is disabled
234  */
235 static int iwl_find_otp_image(struct iwl_trans *trans,
236 					u16 *validblockaddr)
237 {
238 	u16 next_link_addr = 0, valid_addr;
239 	__le16 link_value = 0;
240 	int usedblocks = 0;
241 
242 	/* set addressing mode to absolute to traverse the link list */
243 	iwl_set_otp_access_absolute(trans);
244 
245 	/* checking for empty OTP or error */
246 	if (iwl_is_otp_empty(trans))
247 		return -EINVAL;
248 
249 	/*
250 	 * start traverse link list
251 	 * until reach the max number of OTP blocks
252 	 * different devices have different number of OTP blocks
253 	 */
254 	do {
255 		/* save current valid block address
256 		 * check for more block on the link list
257 		 */
258 		valid_addr = next_link_addr;
259 		next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
260 		IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
261 				 usedblocks, next_link_addr);
262 		if (iwl_read_otp_word(trans, next_link_addr, &link_value))
263 			return -EINVAL;
264 		if (!link_value) {
265 			/*
266 			 * reach the end of link list, return success and
267 			 * set address point to the starting address
268 			 * of the image
269 			 */
270 			*validblockaddr = valid_addr;
271 			/* skip first 2 bytes (link list pointer) */
272 			*validblockaddr += 2;
273 			return 0;
274 		}
275 		/* more in the link list, continue */
276 		usedblocks++;
277 	} while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);
278 
279 	/* OTP has no valid blocks */
280 	IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
281 	return -EINVAL;
282 }
283 
284 /*
285  * iwl_read_eeprom - read EEPROM contents
286  *
287  * Load the EEPROM contents from adapter and return it
288  * and its size.
289  *
290  * NOTE:  This routine uses the non-debug IO access functions.
291  */
292 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
293 {
294 	__le16 *e;
295 	u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
296 	int sz;
297 	int ret;
298 	u16 addr;
299 	u16 validblockaddr = 0;
300 	u16 cache_addr = 0;
301 	int nvm_is_otp;
302 
303 	if (!eeprom || !eeprom_size)
304 		return -EINVAL;
305 
306 	nvm_is_otp = iwl_nvm_is_otp(trans);
307 	if (nvm_is_otp < 0)
308 		return nvm_is_otp;
309 
310 	sz = trans->trans_cfg->base_params->eeprom_size;
311 	IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
312 
313 	e = kmalloc(sz, GFP_KERNEL);
314 	if (!e)
315 		return -ENOMEM;
316 
317 	ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
318 	if (ret < 0) {
319 		IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
320 		goto err_free;
321 	}
322 
323 	/* Make sure driver (instead of uCode) is allowed to read EEPROM */
324 	ret = iwl_eeprom_acquire_semaphore(trans);
325 	if (ret < 0) {
326 		IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
327 		goto err_free;
328 	}
329 
330 	if (nvm_is_otp) {
331 		ret = iwl_init_otp_access(trans);
332 		if (ret) {
333 			IWL_ERR(trans, "Failed to initialize OTP access.\n");
334 			goto err_unlock;
335 		}
336 
337 		iwl_write32(trans, CSR_EEPROM_GP,
338 			    iwl_read32(trans, CSR_EEPROM_GP) &
339 			    ~CSR_EEPROM_GP_IF_OWNER_MSK);
340 
341 		iwl_set_bit(trans, CSR_OTP_GP_REG,
342 			    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
343 			    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
344 		/* traversing the linked list if no shadow ram supported */
345 		if (!trans->trans_cfg->base_params->shadow_ram_support) {
346 			ret = iwl_find_otp_image(trans, &validblockaddr);
347 			if (ret)
348 				goto err_unlock;
349 		}
350 		for (addr = validblockaddr; addr < validblockaddr + sz;
351 		     addr += sizeof(u16)) {
352 			__le16 eeprom_data;
353 
354 			ret = iwl_read_otp_word(trans, addr, &eeprom_data);
355 			if (ret)
356 				goto err_unlock;
357 			e[cache_addr / 2] = eeprom_data;
358 			cache_addr += sizeof(u16);
359 		}
360 	} else {
361 		/* eeprom is an array of 16bit values */
362 		for (addr = 0; addr < sz; addr += sizeof(u16)) {
363 			u32 r;
364 
365 			iwl_write32(trans, CSR_EEPROM_REG,
366 				    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
367 
368 			ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
369 					   CSR_EEPROM_REG_READ_VALID_MSK,
370 					   CSR_EEPROM_REG_READ_VALID_MSK,
371 					   IWL_EEPROM_ACCESS_TIMEOUT);
372 			if (ret < 0) {
373 				IWL_ERR(trans,
374 					"Time out reading EEPROM[%d]\n", addr);
375 				goto err_unlock;
376 			}
377 			r = iwl_read32(trans, CSR_EEPROM_REG);
378 			e[addr / 2] = cpu_to_le16(r >> 16);
379 		}
380 	}
381 
382 	IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
383 			 nvm_is_otp ? "OTP" : "EEPROM");
384 
385 	iwl_eeprom_release_semaphore(trans);
386 
387 	*eeprom_size = sz;
388 	*eeprom = (u8 *)e;
389 	return 0;
390 
391  err_unlock:
392 	iwl_eeprom_release_semaphore(trans);
393  err_free:
394 	kfree(e);
395 
396 	return ret;
397 }
398 IWL_EXPORT_SYMBOL(iwl_read_eeprom);
399