1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2018 Intel Corporation 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * The full GNU General Public License is included in this distribution 21 * in the file called COPYING. 22 * 23 * Contact Information: 24 * Intel Linux Wireless <linuxwifi@intel.com> 25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 * 27 * BSD LICENSE 28 * 29 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 30 * Copyright(c) 2018 Intel Corporation 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 37 * * Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * * Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in 41 * the documentation and/or other materials provided with the 42 * distribution. 43 * * Neither the name Intel Corporation nor the names of its 44 * contributors may be used to endorse or promote products derived 45 * from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 48 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 49 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 50 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 51 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 53 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 *****************************************************************************/ 59 #include <linux/types.h> 60 #include <linux/slab.h> 61 #include <linux/export.h> 62 63 #include "iwl-drv.h" 64 #include "iwl-debug.h" 65 #include "iwl-eeprom-read.h" 66 #include "iwl-io.h" 67 #include "iwl-prph.h" 68 #include "iwl-csr.h" 69 70 /* 71 * EEPROM access time values: 72 * 73 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 74 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 75 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 76 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 77 */ 78 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 79 80 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 81 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 82 83 84 /* 85 * The device's EEPROM semaphore prevents conflicts between driver and uCode 86 * when accessing the EEPROM; each access is a series of pulses to/from the 87 * EEPROM chip, not a single event, so even reads could conflict if they 88 * weren't arbitrated by the semaphore. 89 */ 90 91 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ 92 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 93 94 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans) 95 { 96 u16 count; 97 int ret; 98 99 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { 100 /* Request semaphore */ 101 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 102 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 103 104 /* See if we got it */ 105 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 106 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 107 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 108 EEPROM_SEM_TIMEOUT); 109 if (ret >= 0) { 110 IWL_DEBUG_EEPROM(trans->dev, 111 "Acquired semaphore after %d tries.\n", 112 count+1); 113 return ret; 114 } 115 } 116 117 return ret; 118 } 119 120 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans) 121 { 122 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG, 123 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 124 } 125 126 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp) 127 { 128 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; 129 130 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); 131 132 switch (gp) { 133 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP: 134 if (!nvm_is_otp) { 135 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n", 136 gp); 137 return -ENOENT; 138 } 139 return 0; 140 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: 141 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: 142 if (nvm_is_otp) { 143 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); 144 return -ENOENT; 145 } 146 return 0; 147 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP: 148 default: 149 IWL_ERR(trans, 150 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", 151 nvm_is_otp ? "OTP" : "EEPROM", gp); 152 return -ENOENT; 153 } 154 } 155 156 /****************************************************************************** 157 * 158 * OTP related functions 159 * 160 ******************************************************************************/ 161 162 static void iwl_set_otp_access_absolute(struct iwl_trans *trans) 163 { 164 iwl_read32(trans, CSR_OTP_GP_REG); 165 166 iwl_clear_bit(trans, CSR_OTP_GP_REG, 167 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 168 } 169 170 static int iwl_nvm_is_otp(struct iwl_trans *trans) 171 { 172 u32 otpgp; 173 174 /* OTP only valid for CP/PP and after */ 175 switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) { 176 case CSR_HW_REV_TYPE_NONE: 177 IWL_ERR(trans, "Unknown hardware type\n"); 178 return -EIO; 179 case CSR_HW_REV_TYPE_5300: 180 case CSR_HW_REV_TYPE_5350: 181 case CSR_HW_REV_TYPE_5100: 182 case CSR_HW_REV_TYPE_5150: 183 return 0; 184 default: 185 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 186 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) 187 return 1; 188 return 0; 189 } 190 } 191 192 static int iwl_init_otp_access(struct iwl_trans *trans) 193 { 194 int ret; 195 196 /* Enable 40MHz radio clock */ 197 iwl_write32(trans, CSR_GP_CNTRL, 198 iwl_read32(trans, CSR_GP_CNTRL) | 199 BIT(trans->cfg->csr->flag_init_done)); 200 201 /* wait for clock to be ready */ 202 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 203 BIT(trans->cfg->csr->flag_mac_clock_ready), 204 BIT(trans->cfg->csr->flag_mac_clock_ready), 205 25000); 206 if (ret < 0) { 207 IWL_ERR(trans, "Time out access OTP\n"); 208 } else { 209 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG, 210 APMG_PS_CTRL_VAL_RESET_REQ); 211 udelay(5); 212 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG, 213 APMG_PS_CTRL_VAL_RESET_REQ); 214 215 /* 216 * CSR auto clock gate disable bit - 217 * this is only applicable for HW with OTP shadow RAM 218 */ 219 if (trans->cfg->base_params->shadow_ram_support) 220 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 221 CSR_RESET_LINK_PWR_MGMT_DISABLED); 222 } 223 return ret; 224 } 225 226 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr, 227 __le16 *eeprom_data) 228 { 229 int ret = 0; 230 u32 r; 231 u32 otpgp; 232 233 iwl_write32(trans, CSR_EEPROM_REG, 234 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 235 ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 236 CSR_EEPROM_REG_READ_VALID_MSK, 237 CSR_EEPROM_REG_READ_VALID_MSK, 238 IWL_EEPROM_ACCESS_TIMEOUT); 239 if (ret < 0) { 240 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); 241 return ret; 242 } 243 r = iwl_read32(trans, CSR_EEPROM_REG); 244 /* check for ECC errors: */ 245 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 246 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { 247 /* stop in this case */ 248 /* set the uncorrectable OTP ECC bit for acknowledgment */ 249 iwl_set_bit(trans, CSR_OTP_GP_REG, 250 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 251 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); 252 return -EINVAL; 253 } 254 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { 255 /* continue in this case */ 256 /* set the correctable OTP ECC bit for acknowledgment */ 257 iwl_set_bit(trans, CSR_OTP_GP_REG, 258 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); 259 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n"); 260 } 261 *eeprom_data = cpu_to_le16(r >> 16); 262 return 0; 263 } 264 265 /* 266 * iwl_is_otp_empty: check for empty OTP 267 */ 268 static bool iwl_is_otp_empty(struct iwl_trans *trans) 269 { 270 u16 next_link_addr = 0; 271 __le16 link_value; 272 bool is_empty = false; 273 274 /* locate the beginning of OTP link list */ 275 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) { 276 if (!link_value) { 277 IWL_ERR(trans, "OTP is empty\n"); 278 is_empty = true; 279 } 280 } else { 281 IWL_ERR(trans, "Unable to read first block of OTP list.\n"); 282 is_empty = true; 283 } 284 285 return is_empty; 286 } 287 288 289 /* 290 * iwl_find_otp_image: find EEPROM image in OTP 291 * finding the OTP block that contains the EEPROM image. 292 * the last valid block on the link list (the block _before_ the last block) 293 * is the block we should read and used to configure the device. 294 * If all the available OTP blocks are full, the last block will be the block 295 * we should read and used to configure the device. 296 * only perform this operation if shadow RAM is disabled 297 */ 298 static int iwl_find_otp_image(struct iwl_trans *trans, 299 u16 *validblockaddr) 300 { 301 u16 next_link_addr = 0, valid_addr; 302 __le16 link_value = 0; 303 int usedblocks = 0; 304 305 /* set addressing mode to absolute to traverse the link list */ 306 iwl_set_otp_access_absolute(trans); 307 308 /* checking for empty OTP or error */ 309 if (iwl_is_otp_empty(trans)) 310 return -EINVAL; 311 312 /* 313 * start traverse link list 314 * until reach the max number of OTP blocks 315 * different devices have different number of OTP blocks 316 */ 317 do { 318 /* save current valid block address 319 * check for more block on the link list 320 */ 321 valid_addr = next_link_addr; 322 next_link_addr = le16_to_cpu(link_value) * sizeof(u16); 323 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n", 324 usedblocks, next_link_addr); 325 if (iwl_read_otp_word(trans, next_link_addr, &link_value)) 326 return -EINVAL; 327 if (!link_value) { 328 /* 329 * reach the end of link list, return success and 330 * set address point to the starting address 331 * of the image 332 */ 333 *validblockaddr = valid_addr; 334 /* skip first 2 bytes (link list pointer) */ 335 *validblockaddr += 2; 336 return 0; 337 } 338 /* more in the link list, continue */ 339 usedblocks++; 340 } while (usedblocks <= trans->cfg->base_params->max_ll_items); 341 342 /* OTP has no valid blocks */ 343 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n"); 344 return -EINVAL; 345 } 346 347 /** 348 * iwl_read_eeprom - read EEPROM contents 349 * 350 * Load the EEPROM contents from adapter and return it 351 * and its size. 352 * 353 * NOTE: This routine uses the non-debug IO access functions. 354 */ 355 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size) 356 { 357 __le16 *e; 358 u32 gp = iwl_read32(trans, CSR_EEPROM_GP); 359 int sz; 360 int ret; 361 u16 addr; 362 u16 validblockaddr = 0; 363 u16 cache_addr = 0; 364 int nvm_is_otp; 365 366 if (!eeprom || !eeprom_size) 367 return -EINVAL; 368 369 nvm_is_otp = iwl_nvm_is_otp(trans); 370 if (nvm_is_otp < 0) 371 return nvm_is_otp; 372 373 sz = trans->cfg->base_params->eeprom_size; 374 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz); 375 376 e = kmalloc(sz, GFP_KERNEL); 377 if (!e) 378 return -ENOMEM; 379 380 ret = iwl_eeprom_verify_signature(trans, nvm_is_otp); 381 if (ret < 0) { 382 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); 383 goto err_free; 384 } 385 386 /* Make sure driver (instead of uCode) is allowed to read EEPROM */ 387 ret = iwl_eeprom_acquire_semaphore(trans); 388 if (ret < 0) { 389 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n"); 390 goto err_free; 391 } 392 393 if (nvm_is_otp) { 394 ret = iwl_init_otp_access(trans); 395 if (ret) { 396 IWL_ERR(trans, "Failed to initialize OTP access.\n"); 397 goto err_unlock; 398 } 399 400 iwl_write32(trans, CSR_EEPROM_GP, 401 iwl_read32(trans, CSR_EEPROM_GP) & 402 ~CSR_EEPROM_GP_IF_OWNER_MSK); 403 404 iwl_set_bit(trans, CSR_OTP_GP_REG, 405 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | 406 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 407 /* traversing the linked list if no shadow ram supported */ 408 if (!trans->cfg->base_params->shadow_ram_support) { 409 ret = iwl_find_otp_image(trans, &validblockaddr); 410 if (ret) 411 goto err_unlock; 412 } 413 for (addr = validblockaddr; addr < validblockaddr + sz; 414 addr += sizeof(u16)) { 415 __le16 eeprom_data; 416 417 ret = iwl_read_otp_word(trans, addr, &eeprom_data); 418 if (ret) 419 goto err_unlock; 420 e[cache_addr / 2] = eeprom_data; 421 cache_addr += sizeof(u16); 422 } 423 } else { 424 /* eeprom is an array of 16bit values */ 425 for (addr = 0; addr < sz; addr += sizeof(u16)) { 426 u32 r; 427 428 iwl_write32(trans, CSR_EEPROM_REG, 429 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 430 431 ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 432 CSR_EEPROM_REG_READ_VALID_MSK, 433 CSR_EEPROM_REG_READ_VALID_MSK, 434 IWL_EEPROM_ACCESS_TIMEOUT); 435 if (ret < 0) { 436 IWL_ERR(trans, 437 "Time out reading EEPROM[%d]\n", addr); 438 goto err_unlock; 439 } 440 r = iwl_read32(trans, CSR_EEPROM_REG); 441 e[addr / 2] = cpu_to_le16(r >> 16); 442 } 443 } 444 445 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n", 446 nvm_is_otp ? "OTP" : "EEPROM"); 447 448 iwl_eeprom_release_semaphore(trans); 449 450 *eeprom_size = sz; 451 *eeprom = (u8 *)e; 452 return 0; 453 454 err_unlock: 455 iwl_eeprom_release_semaphore(trans); 456 err_free: 457 kfree(e); 458 459 return ret; 460 } 461 IWL_EXPORT_SYMBOL(iwl_read_eeprom); 462