18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 3*425d66d8SJohannes Berg * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation 48e99ea8dSJohannes Berg */ 5e705c121SKalle Valo #include <linux/types.h> 6e705c121SKalle Valo #include <linux/slab.h> 7e705c121SKalle Valo #include <linux/export.h> 8e705c121SKalle Valo 9e705c121SKalle Valo #include "iwl-drv.h" 10e705c121SKalle Valo #include "iwl-debug.h" 11e705c121SKalle Valo #include "iwl-eeprom-read.h" 12e705c121SKalle Valo #include "iwl-io.h" 13e705c121SKalle Valo #include "iwl-prph.h" 14e705c121SKalle Valo #include "iwl-csr.h" 15e705c121SKalle Valo 16e705c121SKalle Valo /* 17e705c121SKalle Valo * EEPROM access time values: 18e705c121SKalle Valo * 19e705c121SKalle Valo * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 20e705c121SKalle Valo * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 21e705c121SKalle Valo * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 22e705c121SKalle Valo * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 23e705c121SKalle Valo */ 24e705c121SKalle Valo #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 25e705c121SKalle Valo 26e705c121SKalle Valo #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 27e705c121SKalle Valo #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 28e705c121SKalle Valo 29e705c121SKalle Valo 30e705c121SKalle Valo /* 31e705c121SKalle Valo * The device's EEPROM semaphore prevents conflicts between driver and uCode 32e705c121SKalle Valo * when accessing the EEPROM; each access is a series of pulses to/from the 33e705c121SKalle Valo * EEPROM chip, not a single event, so even reads could conflict if they 34e705c121SKalle Valo * weren't arbitrated by the semaphore. 35e705c121SKalle Valo */ 36e705c121SKalle Valo 37e705c121SKalle Valo #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ 38e705c121SKalle Valo #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 39e705c121SKalle Valo 40e705c121SKalle Valo static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans) 41e705c121SKalle Valo { 42e705c121SKalle Valo u16 count; 43e705c121SKalle Valo int ret; 44e705c121SKalle Valo 45e705c121SKalle Valo for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { 46e705c121SKalle Valo /* Request semaphore */ 47e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 48e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 49e705c121SKalle Valo 50e705c121SKalle Valo /* See if we got it */ 51e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 52e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 53e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 54e705c121SKalle Valo EEPROM_SEM_TIMEOUT); 55e705c121SKalle Valo if (ret >= 0) { 56e705c121SKalle Valo IWL_DEBUG_EEPROM(trans->dev, 57e705c121SKalle Valo "Acquired semaphore after %d tries.\n", 58e705c121SKalle Valo count+1); 59e705c121SKalle Valo return ret; 60e705c121SKalle Valo } 61e705c121SKalle Valo } 62e705c121SKalle Valo 63e705c121SKalle Valo return ret; 64e705c121SKalle Valo } 65e705c121SKalle Valo 66e705c121SKalle Valo static void iwl_eeprom_release_semaphore(struct iwl_trans *trans) 67e705c121SKalle Valo { 68e705c121SKalle Valo iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG, 69e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 70e705c121SKalle Valo } 71e705c121SKalle Valo 72e705c121SKalle Valo static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp) 73e705c121SKalle Valo { 74e705c121SKalle Valo u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; 75e705c121SKalle Valo 76e705c121SKalle Valo IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); 77e705c121SKalle Valo 78e705c121SKalle Valo switch (gp) { 79e705c121SKalle Valo case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP: 80e705c121SKalle Valo if (!nvm_is_otp) { 81e705c121SKalle Valo IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n", 82e705c121SKalle Valo gp); 83e705c121SKalle Valo return -ENOENT; 84e705c121SKalle Valo } 85e705c121SKalle Valo return 0; 86e705c121SKalle Valo case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: 87e705c121SKalle Valo case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: 88e705c121SKalle Valo if (nvm_is_otp) { 89e705c121SKalle Valo IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); 90e705c121SKalle Valo return -ENOENT; 91e705c121SKalle Valo } 92e705c121SKalle Valo return 0; 93e705c121SKalle Valo case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP: 94e705c121SKalle Valo default: 95e705c121SKalle Valo IWL_ERR(trans, 96e705c121SKalle Valo "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", 97e705c121SKalle Valo nvm_is_otp ? "OTP" : "EEPROM", gp); 98e705c121SKalle Valo return -ENOENT; 99e705c121SKalle Valo } 100e705c121SKalle Valo } 101e705c121SKalle Valo 102e705c121SKalle Valo /****************************************************************************** 103e705c121SKalle Valo * 104e705c121SKalle Valo * OTP related functions 105e705c121SKalle Valo * 106e705c121SKalle Valo ******************************************************************************/ 107e705c121SKalle Valo 108e705c121SKalle Valo static void iwl_set_otp_access_absolute(struct iwl_trans *trans) 109e705c121SKalle Valo { 110e705c121SKalle Valo iwl_read32(trans, CSR_OTP_GP_REG); 111e705c121SKalle Valo 112e705c121SKalle Valo iwl_clear_bit(trans, CSR_OTP_GP_REG, 113e705c121SKalle Valo CSR_OTP_GP_REG_OTP_ACCESS_MODE); 114e705c121SKalle Valo } 115e705c121SKalle Valo 116e705c121SKalle Valo static int iwl_nvm_is_otp(struct iwl_trans *trans) 117e705c121SKalle Valo { 118e705c121SKalle Valo u32 otpgp; 119e705c121SKalle Valo 120e705c121SKalle Valo /* OTP only valid for CP/PP and after */ 121e705c121SKalle Valo switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) { 122e705c121SKalle Valo case CSR_HW_REV_TYPE_NONE: 123e705c121SKalle Valo IWL_ERR(trans, "Unknown hardware type\n"); 124e705c121SKalle Valo return -EIO; 125e705c121SKalle Valo case CSR_HW_REV_TYPE_5300: 126e705c121SKalle Valo case CSR_HW_REV_TYPE_5350: 127e705c121SKalle Valo case CSR_HW_REV_TYPE_5100: 128e705c121SKalle Valo case CSR_HW_REV_TYPE_5150: 129e705c121SKalle Valo return 0; 130e705c121SKalle Valo default: 131e705c121SKalle Valo otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 132e705c121SKalle Valo if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) 133e705c121SKalle Valo return 1; 134e705c121SKalle Valo return 0; 135e705c121SKalle Valo } 136e705c121SKalle Valo } 137e705c121SKalle Valo 138e705c121SKalle Valo static int iwl_init_otp_access(struct iwl_trans *trans) 139e705c121SKalle Valo { 140e705c121SKalle Valo int ret; 141e705c121SKalle Valo 142*425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 143c96b5eecSJohannes Berg if (ret) 144c96b5eecSJohannes Berg return ret; 145e705c121SKalle Valo 146e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PS_CTRL_REG, 147e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ); 148e705c121SKalle Valo udelay(5); 149e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG, 150e705c121SKalle Valo APMG_PS_CTRL_VAL_RESET_REQ); 151e705c121SKalle Valo 152e705c121SKalle Valo /* 153e705c121SKalle Valo * CSR auto clock gate disable bit - 154e705c121SKalle Valo * this is only applicable for HW with OTP shadow RAM 155e705c121SKalle Valo */ 156286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_ram_support) 157e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 158e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 159c96b5eecSJohannes Berg 160c96b5eecSJohannes Berg return 0; 161e705c121SKalle Valo } 162e705c121SKalle Valo 163e705c121SKalle Valo static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr, 164e705c121SKalle Valo __le16 *eeprom_data) 165e705c121SKalle Valo { 166e705c121SKalle Valo int ret = 0; 167e705c121SKalle Valo u32 r; 168e705c121SKalle Valo u32 otpgp; 169e705c121SKalle Valo 170e705c121SKalle Valo iwl_write32(trans, CSR_EEPROM_REG, 171e705c121SKalle Valo CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 172e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 173e705c121SKalle Valo CSR_EEPROM_REG_READ_VALID_MSK, 174e705c121SKalle Valo CSR_EEPROM_REG_READ_VALID_MSK, 175e705c121SKalle Valo IWL_EEPROM_ACCESS_TIMEOUT); 176e705c121SKalle Valo if (ret < 0) { 177e705c121SKalle Valo IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); 178e705c121SKalle Valo return ret; 179e705c121SKalle Valo } 180e705c121SKalle Valo r = iwl_read32(trans, CSR_EEPROM_REG); 181e705c121SKalle Valo /* check for ECC errors: */ 182e705c121SKalle Valo otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 183e705c121SKalle Valo if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { 184e705c121SKalle Valo /* stop in this case */ 185e705c121SKalle Valo /* set the uncorrectable OTP ECC bit for acknowledgment */ 186e705c121SKalle Valo iwl_set_bit(trans, CSR_OTP_GP_REG, 187e705c121SKalle Valo CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 188e705c121SKalle Valo IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); 189e705c121SKalle Valo return -EINVAL; 190e705c121SKalle Valo } 191e705c121SKalle Valo if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { 192e705c121SKalle Valo /* continue in this case */ 193e705c121SKalle Valo /* set the correctable OTP ECC bit for acknowledgment */ 194e705c121SKalle Valo iwl_set_bit(trans, CSR_OTP_GP_REG, 195e705c121SKalle Valo CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); 196e705c121SKalle Valo IWL_ERR(trans, "Correctable OTP ECC error, continue read\n"); 197e705c121SKalle Valo } 198e705c121SKalle Valo *eeprom_data = cpu_to_le16(r >> 16); 199e705c121SKalle Valo return 0; 200e705c121SKalle Valo } 201e705c121SKalle Valo 202e705c121SKalle Valo /* 203e705c121SKalle Valo * iwl_is_otp_empty: check for empty OTP 204e705c121SKalle Valo */ 205e705c121SKalle Valo static bool iwl_is_otp_empty(struct iwl_trans *trans) 206e705c121SKalle Valo { 207e705c121SKalle Valo u16 next_link_addr = 0; 208e705c121SKalle Valo __le16 link_value; 209e705c121SKalle Valo bool is_empty = false; 210e705c121SKalle Valo 211e705c121SKalle Valo /* locate the beginning of OTP link list */ 212e705c121SKalle Valo if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) { 213e705c121SKalle Valo if (!link_value) { 214e705c121SKalle Valo IWL_ERR(trans, "OTP is empty\n"); 215e705c121SKalle Valo is_empty = true; 216e705c121SKalle Valo } 217e705c121SKalle Valo } else { 218e705c121SKalle Valo IWL_ERR(trans, "Unable to read first block of OTP list.\n"); 219e705c121SKalle Valo is_empty = true; 220e705c121SKalle Valo } 221e705c121SKalle Valo 222e705c121SKalle Valo return is_empty; 223e705c121SKalle Valo } 224e705c121SKalle Valo 225e705c121SKalle Valo 226e705c121SKalle Valo /* 227e705c121SKalle Valo * iwl_find_otp_image: find EEPROM image in OTP 228e705c121SKalle Valo * finding the OTP block that contains the EEPROM image. 229e705c121SKalle Valo * the last valid block on the link list (the block _before_ the last block) 230e705c121SKalle Valo * is the block we should read and used to configure the device. 231e705c121SKalle Valo * If all the available OTP blocks are full, the last block will be the block 232e705c121SKalle Valo * we should read and used to configure the device. 233e705c121SKalle Valo * only perform this operation if shadow RAM is disabled 234e705c121SKalle Valo */ 235e705c121SKalle Valo static int iwl_find_otp_image(struct iwl_trans *trans, 236e705c121SKalle Valo u16 *validblockaddr) 237e705c121SKalle Valo { 238e705c121SKalle Valo u16 next_link_addr = 0, valid_addr; 239e705c121SKalle Valo __le16 link_value = 0; 240e705c121SKalle Valo int usedblocks = 0; 241e705c121SKalle Valo 242e705c121SKalle Valo /* set addressing mode to absolute to traverse the link list */ 243e705c121SKalle Valo iwl_set_otp_access_absolute(trans); 244e705c121SKalle Valo 245e705c121SKalle Valo /* checking for empty OTP or error */ 246e705c121SKalle Valo if (iwl_is_otp_empty(trans)) 247e705c121SKalle Valo return -EINVAL; 248e705c121SKalle Valo 249e705c121SKalle Valo /* 250e705c121SKalle Valo * start traverse link list 251e705c121SKalle Valo * until reach the max number of OTP blocks 252e705c121SKalle Valo * different devices have different number of OTP blocks 253e705c121SKalle Valo */ 254e705c121SKalle Valo do { 255e705c121SKalle Valo /* save current valid block address 256e705c121SKalle Valo * check for more block on the link list 257e705c121SKalle Valo */ 258e705c121SKalle Valo valid_addr = next_link_addr; 259e705c121SKalle Valo next_link_addr = le16_to_cpu(link_value) * sizeof(u16); 260e705c121SKalle Valo IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n", 261e705c121SKalle Valo usedblocks, next_link_addr); 262e705c121SKalle Valo if (iwl_read_otp_word(trans, next_link_addr, &link_value)) 263e705c121SKalle Valo return -EINVAL; 264e705c121SKalle Valo if (!link_value) { 265e705c121SKalle Valo /* 266e705c121SKalle Valo * reach the end of link list, return success and 267e705c121SKalle Valo * set address point to the starting address 268e705c121SKalle Valo * of the image 269e705c121SKalle Valo */ 270e705c121SKalle Valo *validblockaddr = valid_addr; 271e705c121SKalle Valo /* skip first 2 bytes (link list pointer) */ 272e705c121SKalle Valo *validblockaddr += 2; 273e705c121SKalle Valo return 0; 274e705c121SKalle Valo } 275e705c121SKalle Valo /* more in the link list, continue */ 276e705c121SKalle Valo usedblocks++; 277286ca8ebSLuca Coelho } while (usedblocks <= trans->trans_cfg->base_params->max_ll_items); 278e705c121SKalle Valo 279e705c121SKalle Valo /* OTP has no valid blocks */ 280e705c121SKalle Valo IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n"); 281e705c121SKalle Valo return -EINVAL; 282e705c121SKalle Valo } 283e705c121SKalle Valo 284dde0a25dSLee Jones /* 285e705c121SKalle Valo * iwl_read_eeprom - read EEPROM contents 286e705c121SKalle Valo * 287e705c121SKalle Valo * Load the EEPROM contents from adapter and return it 288e705c121SKalle Valo * and its size. 289e705c121SKalle Valo * 290e705c121SKalle Valo * NOTE: This routine uses the non-debug IO access functions. 291e705c121SKalle Valo */ 292e705c121SKalle Valo int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size) 293e705c121SKalle Valo { 294e705c121SKalle Valo __le16 *e; 295e705c121SKalle Valo u32 gp = iwl_read32(trans, CSR_EEPROM_GP); 296e705c121SKalle Valo int sz; 297e705c121SKalle Valo int ret; 298e705c121SKalle Valo u16 addr; 299e705c121SKalle Valo u16 validblockaddr = 0; 300e705c121SKalle Valo u16 cache_addr = 0; 301e705c121SKalle Valo int nvm_is_otp; 302e705c121SKalle Valo 303e705c121SKalle Valo if (!eeprom || !eeprom_size) 304e705c121SKalle Valo return -EINVAL; 305e705c121SKalle Valo 306e705c121SKalle Valo nvm_is_otp = iwl_nvm_is_otp(trans); 307e705c121SKalle Valo if (nvm_is_otp < 0) 308e705c121SKalle Valo return nvm_is_otp; 309e705c121SKalle Valo 310286ca8ebSLuca Coelho sz = trans->trans_cfg->base_params->eeprom_size; 311e705c121SKalle Valo IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz); 312e705c121SKalle Valo 313e705c121SKalle Valo e = kmalloc(sz, GFP_KERNEL); 314e705c121SKalle Valo if (!e) 315e705c121SKalle Valo return -ENOMEM; 316e705c121SKalle Valo 317e705c121SKalle Valo ret = iwl_eeprom_verify_signature(trans, nvm_is_otp); 318e705c121SKalle Valo if (ret < 0) { 319e705c121SKalle Valo IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); 320e705c121SKalle Valo goto err_free; 321e705c121SKalle Valo } 322e705c121SKalle Valo 323e705c121SKalle Valo /* Make sure driver (instead of uCode) is allowed to read EEPROM */ 324e705c121SKalle Valo ret = iwl_eeprom_acquire_semaphore(trans); 325e705c121SKalle Valo if (ret < 0) { 326e705c121SKalle Valo IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n"); 327e705c121SKalle Valo goto err_free; 328e705c121SKalle Valo } 329e705c121SKalle Valo 330e705c121SKalle Valo if (nvm_is_otp) { 331e705c121SKalle Valo ret = iwl_init_otp_access(trans); 332e705c121SKalle Valo if (ret) { 333e705c121SKalle Valo IWL_ERR(trans, "Failed to initialize OTP access.\n"); 334e705c121SKalle Valo goto err_unlock; 335e705c121SKalle Valo } 336e705c121SKalle Valo 337e705c121SKalle Valo iwl_write32(trans, CSR_EEPROM_GP, 338e705c121SKalle Valo iwl_read32(trans, CSR_EEPROM_GP) & 339e705c121SKalle Valo ~CSR_EEPROM_GP_IF_OWNER_MSK); 340e705c121SKalle Valo 341e705c121SKalle Valo iwl_set_bit(trans, CSR_OTP_GP_REG, 342e705c121SKalle Valo CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | 343e705c121SKalle Valo CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 344e705c121SKalle Valo /* traversing the linked list if no shadow ram supported */ 345286ca8ebSLuca Coelho if (!trans->trans_cfg->base_params->shadow_ram_support) { 346e705c121SKalle Valo ret = iwl_find_otp_image(trans, &validblockaddr); 347e705c121SKalle Valo if (ret) 348e705c121SKalle Valo goto err_unlock; 349e705c121SKalle Valo } 350e705c121SKalle Valo for (addr = validblockaddr; addr < validblockaddr + sz; 351e705c121SKalle Valo addr += sizeof(u16)) { 352e705c121SKalle Valo __le16 eeprom_data; 353e705c121SKalle Valo 354e705c121SKalle Valo ret = iwl_read_otp_word(trans, addr, &eeprom_data); 355e705c121SKalle Valo if (ret) 356e705c121SKalle Valo goto err_unlock; 357e705c121SKalle Valo e[cache_addr / 2] = eeprom_data; 358e705c121SKalle Valo cache_addr += sizeof(u16); 359e705c121SKalle Valo } 360e705c121SKalle Valo } else { 361e705c121SKalle Valo /* eeprom is an array of 16bit values */ 362e705c121SKalle Valo for (addr = 0; addr < sz; addr += sizeof(u16)) { 363e705c121SKalle Valo u32 r; 364e705c121SKalle Valo 365e705c121SKalle Valo iwl_write32(trans, CSR_EEPROM_REG, 366e705c121SKalle Valo CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 367e705c121SKalle Valo 368e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 369e705c121SKalle Valo CSR_EEPROM_REG_READ_VALID_MSK, 370e705c121SKalle Valo CSR_EEPROM_REG_READ_VALID_MSK, 371e705c121SKalle Valo IWL_EEPROM_ACCESS_TIMEOUT); 372e705c121SKalle Valo if (ret < 0) { 373e705c121SKalle Valo IWL_ERR(trans, 374e705c121SKalle Valo "Time out reading EEPROM[%d]\n", addr); 375e705c121SKalle Valo goto err_unlock; 376e705c121SKalle Valo } 377e705c121SKalle Valo r = iwl_read32(trans, CSR_EEPROM_REG); 378e705c121SKalle Valo e[addr / 2] = cpu_to_le16(r >> 16); 379e705c121SKalle Valo } 380e705c121SKalle Valo } 381e705c121SKalle Valo 382e705c121SKalle Valo IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n", 383e705c121SKalle Valo nvm_is_otp ? "OTP" : "EEPROM"); 384e705c121SKalle Valo 385e705c121SKalle Valo iwl_eeprom_release_semaphore(trans); 386e705c121SKalle Valo 387e705c121SKalle Valo *eeprom_size = sz; 388e705c121SKalle Valo *eeprom = (u8 *)e; 389e705c121SKalle Valo return 0; 390e705c121SKalle Valo 391e705c121SKalle Valo err_unlock: 392e705c121SKalle Valo iwl_eeprom_release_semaphore(trans); 393e705c121SKalle Valo err_free: 394e705c121SKalle Valo kfree(e); 395e705c121SKalle Valo 396e705c121SKalle Valo return ret; 397e705c121SKalle Valo } 398e705c121SKalle Valo IWL_EXPORT_SYMBOL(iwl_read_eeprom); 399