1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9  * Copyright(c) 2015 Intel Mobile Communications GmbH
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of version 2 of the GNU General Public License as
13  * published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope that it will be useful, but
16  * WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * General Public License for more details.
19  *
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21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23  * USA
24  *
25  * The full GNU General Public License is included in this distribution
26  * in the file called COPYING.
27  *
28  * Contact Information:
29  *  Intel Linux Wireless <linuxwifi@intel.com>
30  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31  *
32  * BSD LICENSE
33  *
34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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63  *****************************************************************************/
64 #include <linux/types.h>
65 #include <linux/slab.h>
66 #include <linux/export.h>
67 #include "iwl-drv.h"
68 #include "iwl-modparams.h"
69 #include "iwl-eeprom-parse.h"
70 
71 /* EEPROM offset definitions */
72 
73 /* indirect access definitions */
74 #define ADDRESS_MSK                 0x0000FFFF
75 #define INDIRECT_TYPE_MSK           0x000F0000
76 #define INDIRECT_HOST               0x00010000
77 #define INDIRECT_GENERAL            0x00020000
78 #define INDIRECT_REGULATORY         0x00030000
79 #define INDIRECT_CALIBRATION        0x00040000
80 #define INDIRECT_PROCESS_ADJST      0x00050000
81 #define INDIRECT_OTHERS             0x00060000
82 #define INDIRECT_TXP_LIMIT          0x00070000
83 #define INDIRECT_TXP_LIMIT_SIZE     0x00080000
84 #define INDIRECT_ADDRESS            0x00100000
85 
86 /* corresponding link offsets in EEPROM */
87 #define EEPROM_LINK_HOST             (2*0x64)
88 #define EEPROM_LINK_GENERAL          (2*0x65)
89 #define EEPROM_LINK_REGULATORY       (2*0x66)
90 #define EEPROM_LINK_CALIBRATION      (2*0x67)
91 #define EEPROM_LINK_PROCESS_ADJST    (2*0x68)
92 #define EEPROM_LINK_OTHERS           (2*0x69)
93 #define EEPROM_LINK_TXP_LIMIT        (2*0x6a)
94 #define EEPROM_LINK_TXP_LIMIT_SIZE   (2*0x6b)
95 
96 /* General */
97 #define EEPROM_DEVICE_ID                    (2*0x08)	/* 2 bytes */
98 #define EEPROM_SUBSYSTEM_ID		    (2*0x0A)	/* 2 bytes */
99 #define EEPROM_MAC_ADDRESS                  (2*0x15)	/* 6  bytes */
100 #define EEPROM_BOARD_REVISION               (2*0x35)	/* 2  bytes */
101 #define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)	/* 9  bytes */
102 #define EEPROM_VERSION                      (2*0x44)	/* 2  bytes */
103 #define EEPROM_SKU_CAP                      (2*0x45)	/* 2  bytes */
104 #define EEPROM_OEM_MODE                     (2*0x46)	/* 2  bytes */
105 #define EEPROM_RADIO_CONFIG                 (2*0x48)	/* 2  bytes */
106 #define EEPROM_NUM_MAC_ADDRESS              (2*0x4C)	/* 2  bytes */
107 
108 /* calibration */
109 struct iwl_eeprom_calib_hdr {
110 	u8 version;
111 	u8 pa_type;
112 	__le16 voltage;
113 } __packed;
114 
115 #define EEPROM_CALIB_ALL	(INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
116 #define EEPROM_XTAL		((2*0x128) | EEPROM_CALIB_ALL)
117 
118 /* temperature */
119 #define EEPROM_KELVIN_TEMPERATURE	((2*0x12A) | EEPROM_CALIB_ALL)
120 #define EEPROM_RAW_TEMPERATURE		((2*0x12B) | EEPROM_CALIB_ALL)
121 
122 /* SKU Capabilities (actual values from EEPROM definition) */
123 enum eeprom_sku_bits {
124 	EEPROM_SKU_CAP_BAND_24GHZ	= BIT(4),
125 	EEPROM_SKU_CAP_BAND_52GHZ	= BIT(5),
126 	EEPROM_SKU_CAP_11N_ENABLE	= BIT(6),
127 	EEPROM_SKU_CAP_AMT_ENABLE	= BIT(7),
128 	EEPROM_SKU_CAP_IPAN_ENABLE	= BIT(8)
129 };
130 
131 /* radio config bits (actual values from EEPROM definition) */
132 #define EEPROM_RF_CFG_TYPE_MSK(x)   (x & 0x3)         /* bits 0-1   */
133 #define EEPROM_RF_CFG_STEP_MSK(x)   ((x >> 2)  & 0x3) /* bits 2-3   */
134 #define EEPROM_RF_CFG_DASH_MSK(x)   ((x >> 4)  & 0x3) /* bits 4-5   */
135 #define EEPROM_RF_CFG_PNUM_MSK(x)   ((x >> 6)  & 0x3) /* bits 6-7   */
136 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8)  & 0xF) /* bits 8-11  */
137 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
138 
139 
140 /*
141  * EEPROM bands
142  * These are the channel numbers from each band in the order
143  * that they are stored in the EEPROM band information. Note
144  * that EEPROM bands aren't the same as mac80211 bands, and
145  * there are even special "ht40 bands" in the EEPROM.
146  */
147 static const u8 iwl_eeprom_band_1[14] = { /* 2.4 GHz */
148 	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
149 };
150 
151 static const u8 iwl_eeprom_band_2[] = {	/* 4915-5080MHz */
152 	183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
153 };
154 
155 static const u8 iwl_eeprom_band_3[] = {	/* 5170-5320MHz */
156 	34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
157 };
158 
159 static const u8 iwl_eeprom_band_4[] = {	/* 5500-5700MHz */
160 	100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
161 };
162 
163 static const u8 iwl_eeprom_band_5[] = {	/* 5725-5825MHz */
164 	145, 149, 153, 157, 161, 165
165 };
166 
167 static const u8 iwl_eeprom_band_6[] = {	/* 2.4 ht40 channel */
168 	1, 2, 3, 4, 5, 6, 7
169 };
170 
171 static const u8 iwl_eeprom_band_7[] = {	/* 5.2 ht40 channel */
172 	36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
173 };
174 
175 #define IWL_NUM_CHANNELS	(ARRAY_SIZE(iwl_eeprom_band_1) + \
176 				 ARRAY_SIZE(iwl_eeprom_band_2) + \
177 				 ARRAY_SIZE(iwl_eeprom_band_3) + \
178 				 ARRAY_SIZE(iwl_eeprom_band_4) + \
179 				 ARRAY_SIZE(iwl_eeprom_band_5))
180 
181 /* rate data (static) */
182 static struct ieee80211_rate iwl_cfg80211_rates[] = {
183 	{ .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
184 	{ .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
185 	  .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
186 	{ .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
187 	  .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
188 	{ .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
189 	  .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
190 	{ .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
191 	{ .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
192 	{ .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
193 	{ .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
194 	{ .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
195 	{ .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
196 	{ .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
197 	{ .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
198 };
199 #define RATES_24_OFFS	0
200 #define N_RATES_24	ARRAY_SIZE(iwl_cfg80211_rates)
201 #define RATES_52_OFFS	4
202 #define N_RATES_52	(N_RATES_24 - RATES_52_OFFS)
203 
204 /* EEPROM reading functions */
205 
206 static u16 iwl_eeprom_query16(const u8 *eeprom, size_t eeprom_size, int offset)
207 {
208 	if (WARN_ON(offset + sizeof(u16) > eeprom_size))
209 		return 0;
210 	return le16_to_cpup((__le16 *)(eeprom + offset));
211 }
212 
213 static u32 eeprom_indirect_address(const u8 *eeprom, size_t eeprom_size,
214 				   u32 address)
215 {
216 	u16 offset = 0;
217 
218 	if ((address & INDIRECT_ADDRESS) == 0)
219 		return address;
220 
221 	switch (address & INDIRECT_TYPE_MSK) {
222 	case INDIRECT_HOST:
223 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
224 					    EEPROM_LINK_HOST);
225 		break;
226 	case INDIRECT_GENERAL:
227 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
228 					    EEPROM_LINK_GENERAL);
229 		break;
230 	case INDIRECT_REGULATORY:
231 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
232 					    EEPROM_LINK_REGULATORY);
233 		break;
234 	case INDIRECT_TXP_LIMIT:
235 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
236 					    EEPROM_LINK_TXP_LIMIT);
237 		break;
238 	case INDIRECT_TXP_LIMIT_SIZE:
239 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
240 					    EEPROM_LINK_TXP_LIMIT_SIZE);
241 		break;
242 	case INDIRECT_CALIBRATION:
243 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
244 					    EEPROM_LINK_CALIBRATION);
245 		break;
246 	case INDIRECT_PROCESS_ADJST:
247 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
248 					    EEPROM_LINK_PROCESS_ADJST);
249 		break;
250 	case INDIRECT_OTHERS:
251 		offset = iwl_eeprom_query16(eeprom, eeprom_size,
252 					    EEPROM_LINK_OTHERS);
253 		break;
254 	default:
255 		WARN_ON(1);
256 		break;
257 	}
258 
259 	/* translate the offset from words to byte */
260 	return (address & ADDRESS_MSK) + (offset << 1);
261 }
262 
263 static const u8 *iwl_eeprom_query_addr(const u8 *eeprom, size_t eeprom_size,
264 				       u32 offset)
265 {
266 	u32 address = eeprom_indirect_address(eeprom, eeprom_size, offset);
267 
268 	if (WARN_ON(address >= eeprom_size))
269 		return NULL;
270 
271 	return &eeprom[address];
272 }
273 
274 static int iwl_eeprom_read_calib(const u8 *eeprom, size_t eeprom_size,
275 				 struct iwl_nvm_data *data)
276 {
277 	struct iwl_eeprom_calib_hdr *hdr;
278 
279 	hdr = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size,
280 					    EEPROM_CALIB_ALL);
281 	if (!hdr)
282 		return -ENODATA;
283 	data->calib_version = hdr->version;
284 	data->calib_voltage = hdr->voltage;
285 
286 	return 0;
287 }
288 
289 /**
290  * enum iwl_eeprom_channel_flags - channel flags in EEPROM
291  * @EEPROM_CHANNEL_VALID: channel is usable for this SKU/geo
292  * @EEPROM_CHANNEL_IBSS: usable as an IBSS channel
293  * @EEPROM_CHANNEL_ACTIVE: active scanning allowed
294  * @EEPROM_CHANNEL_RADAR: radar detection required
295  * @EEPROM_CHANNEL_WIDE: 20 MHz channel okay (?)
296  * @EEPROM_CHANNEL_DFS: dynamic freq selection candidate
297  */
298 enum iwl_eeprom_channel_flags {
299 	EEPROM_CHANNEL_VALID = BIT(0),
300 	EEPROM_CHANNEL_IBSS = BIT(1),
301 	EEPROM_CHANNEL_ACTIVE = BIT(3),
302 	EEPROM_CHANNEL_RADAR = BIT(4),
303 	EEPROM_CHANNEL_WIDE = BIT(5),
304 	EEPROM_CHANNEL_DFS = BIT(7),
305 };
306 
307 /**
308  * struct iwl_eeprom_channel - EEPROM channel data
309  * @flags: %EEPROM_CHANNEL_* flags
310  * @max_power_avg: max power (in dBm) on this channel, at most 31 dBm
311  */
312 struct iwl_eeprom_channel {
313 	u8 flags;
314 	s8 max_power_avg;
315 } __packed;
316 
317 
318 enum iwl_eeprom_enhanced_txpwr_flags {
319 	IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
320 	IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1),
321 	IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
322 	IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3),
323 	IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4),
324 	IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5),
325 	IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6),
326 	IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7),
327 };
328 
329 /**
330  * iwl_eeprom_enhanced_txpwr structure
331  * @flags: entry flags
332  * @channel: channel number
333  * @chain_a_max_pwr: chain a max power in 1/2 dBm
334  * @chain_b_max_pwr: chain b max power in 1/2 dBm
335  * @chain_c_max_pwr: chain c max power in 1/2 dBm
336  * @delta_20_in_40: 20-in-40 deltas (hi/lo)
337  * @mimo2_max_pwr: mimo2 max power in 1/2 dBm
338  * @mimo3_max_pwr: mimo3 max power in 1/2 dBm
339  *
340  * This structure presents the enhanced regulatory tx power limit layout
341  * in an EEPROM image.
342  */
343 struct iwl_eeprom_enhanced_txpwr {
344 	u8 flags;
345 	u8 channel;
346 	s8 chain_a_max;
347 	s8 chain_b_max;
348 	s8 chain_c_max;
349 	u8 delta_20_in_40;
350 	s8 mimo2_max;
351 	s8 mimo3_max;
352 } __packed;
353 
354 static s8 iwl_get_max_txpwr_half_dbm(const struct iwl_nvm_data *data,
355 				     struct iwl_eeprom_enhanced_txpwr *txp)
356 {
357 	s8 result = 0; /* (.5 dBm) */
358 
359 	/* Take the highest tx power from any valid chains */
360 	if (data->valid_tx_ant & ANT_A && txp->chain_a_max > result)
361 		result = txp->chain_a_max;
362 
363 	if (data->valid_tx_ant & ANT_B && txp->chain_b_max > result)
364 		result = txp->chain_b_max;
365 
366 	if (data->valid_tx_ant & ANT_C && txp->chain_c_max > result)
367 		result = txp->chain_c_max;
368 
369 	if ((data->valid_tx_ant == ANT_AB ||
370 	     data->valid_tx_ant == ANT_BC ||
371 	     data->valid_tx_ant == ANT_AC) && txp->mimo2_max > result)
372 		result = txp->mimo2_max;
373 
374 	if (data->valid_tx_ant == ANT_ABC && txp->mimo3_max > result)
375 		result = txp->mimo3_max;
376 
377 	return result;
378 }
379 
380 #define EEPROM_TXP_OFFS	(0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
381 #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
382 #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
383 
384 #define TXP_CHECK_AND_PRINT(x) \
385 	((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) ? # x " " : "")
386 
387 static void
388 iwl_eeprom_enh_txp_read_element(struct iwl_nvm_data *data,
389 				struct iwl_eeprom_enhanced_txpwr *txp,
390 				int n_channels, s8 max_txpower_avg)
391 {
392 	int ch_idx;
393 	enum nl80211_band band;
394 
395 	band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ?
396 		NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
397 
398 	for (ch_idx = 0; ch_idx < n_channels; ch_idx++) {
399 		struct ieee80211_channel *chan = &data->channels[ch_idx];
400 
401 		/* update matching channel or from common data only */
402 		if (txp->channel != 0 && chan->hw_value != txp->channel)
403 			continue;
404 
405 		/* update matching band only */
406 		if (band != chan->band)
407 			continue;
408 
409 		if (chan->max_power < max_txpower_avg &&
410 		    !(txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ))
411 			chan->max_power = max_txpower_avg;
412 	}
413 }
414 
415 static void iwl_eeprom_enhanced_txpower(struct device *dev,
416 					struct iwl_nvm_data *data,
417 					const u8 *eeprom, size_t eeprom_size,
418 					int n_channels)
419 {
420 	struct iwl_eeprom_enhanced_txpwr *txp_array, *txp;
421 	int idx, entries;
422 	__le16 *txp_len;
423 	s8 max_txp_avg_halfdbm;
424 
425 	BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
426 
427 	/* the length is in 16-bit words, but we want entries */
428 	txp_len = (__le16 *)iwl_eeprom_query_addr(eeprom, eeprom_size,
429 						  EEPROM_TXP_SZ_OFFS);
430 	entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
431 
432 	txp_array = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size,
433 						  EEPROM_TXP_OFFS);
434 
435 	for (idx = 0; idx < entries; idx++) {
436 		txp = &txp_array[idx];
437 		/* skip invalid entries */
438 		if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID))
439 			continue;
440 
441 		IWL_DEBUG_EEPROM(dev, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
442 				 (txp->channel && (txp->flags &
443 					IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ?
444 					"Common " : (txp->channel) ?
445 					"Channel" : "Common",
446 				 (txp->channel),
447 				 TXP_CHECK_AND_PRINT(VALID),
448 				 TXP_CHECK_AND_PRINT(BAND_52G),
449 				 TXP_CHECK_AND_PRINT(OFDM),
450 				 TXP_CHECK_AND_PRINT(40MHZ),
451 				 TXP_CHECK_AND_PRINT(HT_AP),
452 				 TXP_CHECK_AND_PRINT(RES1),
453 				 TXP_CHECK_AND_PRINT(RES2),
454 				 TXP_CHECK_AND_PRINT(COMMON_TYPE),
455 				 txp->flags);
456 		IWL_DEBUG_EEPROM(dev,
457 				 "\t\t chain_A: %d chain_B: %d chain_C: %d\n",
458 				 txp->chain_a_max, txp->chain_b_max,
459 				 txp->chain_c_max);
460 		IWL_DEBUG_EEPROM(dev,
461 				 "\t\t MIMO2: %d MIMO3: %d High 20_on_40: 0x%02x Low 20_on_40: 0x%02x\n",
462 				 txp->mimo2_max, txp->mimo3_max,
463 				 ((txp->delta_20_in_40 & 0xf0) >> 4),
464 				 (txp->delta_20_in_40 & 0x0f));
465 
466 		max_txp_avg_halfdbm = iwl_get_max_txpwr_half_dbm(data, txp);
467 
468 		iwl_eeprom_enh_txp_read_element(data, txp, n_channels,
469 				DIV_ROUND_UP(max_txp_avg_halfdbm, 2));
470 
471 		if (max_txp_avg_halfdbm > data->max_tx_pwr_half_dbm)
472 			data->max_tx_pwr_half_dbm = max_txp_avg_halfdbm;
473 	}
474 }
475 
476 static void iwl_init_band_reference(const struct iwl_cfg *cfg,
477 				    const u8 *eeprom, size_t eeprom_size,
478 				    int eeprom_band, int *eeprom_ch_count,
479 				    const struct iwl_eeprom_channel **ch_info,
480 				    const u8 **eeprom_ch_array)
481 {
482 	u32 offset = cfg->eeprom_params->regulatory_bands[eeprom_band - 1];
483 
484 	offset |= INDIRECT_ADDRESS | INDIRECT_REGULATORY;
485 
486 	*ch_info = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, offset);
487 
488 	switch (eeprom_band) {
489 	case 1:		/* 2.4GHz band */
490 		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
491 		*eeprom_ch_array = iwl_eeprom_band_1;
492 		break;
493 	case 2:		/* 4.9GHz band */
494 		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
495 		*eeprom_ch_array = iwl_eeprom_band_2;
496 		break;
497 	case 3:		/* 5.2GHz band */
498 		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
499 		*eeprom_ch_array = iwl_eeprom_band_3;
500 		break;
501 	case 4:		/* 5.5GHz band */
502 		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
503 		*eeprom_ch_array = iwl_eeprom_band_4;
504 		break;
505 	case 5:		/* 5.7GHz band */
506 		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
507 		*eeprom_ch_array = iwl_eeprom_band_5;
508 		break;
509 	case 6:		/* 2.4GHz ht40 channels */
510 		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
511 		*eeprom_ch_array = iwl_eeprom_band_6;
512 		break;
513 	case 7:		/* 5 GHz ht40 channels */
514 		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
515 		*eeprom_ch_array = iwl_eeprom_band_7;
516 		break;
517 	default:
518 		*eeprom_ch_count = 0;
519 		*eeprom_ch_array = NULL;
520 		WARN_ON(1);
521 	}
522 }
523 
524 #define CHECK_AND_PRINT(x) \
525 	((eeprom_ch->flags & EEPROM_CHANNEL_##x) ? # x " " : "")
526 
527 static void iwl_mod_ht40_chan_info(struct device *dev,
528 				   struct iwl_nvm_data *data, int n_channels,
529 				   enum nl80211_band band, u16 channel,
530 				   const struct iwl_eeprom_channel *eeprom_ch,
531 				   u8 clear_ht40_extension_channel)
532 {
533 	struct ieee80211_channel *chan = NULL;
534 	int i;
535 
536 	for (i = 0; i < n_channels; i++) {
537 		if (data->channels[i].band != band)
538 			continue;
539 		if (data->channels[i].hw_value != channel)
540 			continue;
541 		chan = &data->channels[i];
542 		break;
543 	}
544 
545 	if (!chan)
546 		return;
547 
548 	IWL_DEBUG_EEPROM(dev,
549 			 "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
550 			 channel,
551 			 band == NL80211_BAND_5GHZ ? "5.2" : "2.4",
552 			 CHECK_AND_PRINT(IBSS),
553 			 CHECK_AND_PRINT(ACTIVE),
554 			 CHECK_AND_PRINT(RADAR),
555 			 CHECK_AND_PRINT(WIDE),
556 			 CHECK_AND_PRINT(DFS),
557 			 eeprom_ch->flags,
558 			 eeprom_ch->max_power_avg,
559 			 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
560 			  !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? ""
561 								      : "not ");
562 
563 	if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
564 		chan->flags &= ~clear_ht40_extension_channel;
565 }
566 
567 #define CHECK_AND_PRINT_I(x)	\
568 	((eeprom_ch_info[ch_idx].flags & EEPROM_CHANNEL_##x) ? # x " " : "")
569 
570 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
571 				struct iwl_nvm_data *data,
572 				const u8 *eeprom, size_t eeprom_size)
573 {
574 	int band, ch_idx;
575 	const struct iwl_eeprom_channel *eeprom_ch_info;
576 	const u8 *eeprom_ch_array;
577 	int eeprom_ch_count;
578 	int n_channels = 0;
579 
580 	/*
581 	 * Loop through the 5 EEPROM bands and add them to the parse list
582 	 */
583 	for (band = 1; band <= 5; band++) {
584 		struct ieee80211_channel *channel;
585 
586 		iwl_init_band_reference(cfg, eeprom, eeprom_size, band,
587 					&eeprom_ch_count, &eeprom_ch_info,
588 					&eeprom_ch_array);
589 
590 		/* Loop through each band adding each of the channels */
591 		for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) {
592 			const struct iwl_eeprom_channel *eeprom_ch;
593 
594 			eeprom_ch = &eeprom_ch_info[ch_idx];
595 
596 			if (!(eeprom_ch->flags & EEPROM_CHANNEL_VALID)) {
597 				IWL_DEBUG_EEPROM(dev,
598 						 "Ch. %d Flags %x [%sGHz] - No traffic\n",
599 						 eeprom_ch_array[ch_idx],
600 						 eeprom_ch_info[ch_idx].flags,
601 						 (band != 1) ? "5.2" : "2.4");
602 				continue;
603 			}
604 
605 			channel = &data->channels[n_channels];
606 			n_channels++;
607 
608 			channel->hw_value = eeprom_ch_array[ch_idx];
609 			channel->band = (band == 1) ? NL80211_BAND_2GHZ
610 						    : NL80211_BAND_5GHZ;
611 			channel->center_freq =
612 				ieee80211_channel_to_frequency(
613 					channel->hw_value, channel->band);
614 
615 			/* set no-HT40, will enable as appropriate later */
616 			channel->flags = IEEE80211_CHAN_NO_HT40;
617 
618 			if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
619 				channel->flags |= IEEE80211_CHAN_NO_IR;
620 
621 			if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
622 				channel->flags |= IEEE80211_CHAN_NO_IR;
623 
624 			if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
625 				channel->flags |= IEEE80211_CHAN_RADAR;
626 
627 			/* Initialize regulatory-based run-time data */
628 			channel->max_power =
629 				eeprom_ch_info[ch_idx].max_power_avg;
630 			IWL_DEBUG_EEPROM(dev,
631 					 "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
632 					 channel->hw_value,
633 					 (band != 1) ? "5.2" : "2.4",
634 					 CHECK_AND_PRINT_I(VALID),
635 					 CHECK_AND_PRINT_I(IBSS),
636 					 CHECK_AND_PRINT_I(ACTIVE),
637 					 CHECK_AND_PRINT_I(RADAR),
638 					 CHECK_AND_PRINT_I(WIDE),
639 					 CHECK_AND_PRINT_I(DFS),
640 					 eeprom_ch_info[ch_idx].flags,
641 					 eeprom_ch_info[ch_idx].max_power_avg,
642 					 ((eeprom_ch_info[ch_idx].flags &
643 							EEPROM_CHANNEL_IBSS) &&
644 					  !(eeprom_ch_info[ch_idx].flags &
645 							EEPROM_CHANNEL_RADAR))
646 						? "" : "not ");
647 		}
648 	}
649 
650 	if (cfg->eeprom_params->enhanced_txpower) {
651 		/*
652 		 * for newer device (6000 series and up)
653 		 * EEPROM contain enhanced tx power information
654 		 * driver need to process addition information
655 		 * to determine the max channel tx power limits
656 		 */
657 		iwl_eeprom_enhanced_txpower(dev, data, eeprom, eeprom_size,
658 					    n_channels);
659 	} else {
660 		/* All others use data from channel map */
661 		int i;
662 
663 		data->max_tx_pwr_half_dbm = -128;
664 
665 		for (i = 0; i < n_channels; i++)
666 			data->max_tx_pwr_half_dbm =
667 				max_t(s8, data->max_tx_pwr_half_dbm,
668 				      data->channels[i].max_power * 2);
669 	}
670 
671 	/* Check if we do have HT40 channels */
672 	if (cfg->eeprom_params->regulatory_bands[5] ==
673 				EEPROM_REGULATORY_BAND_NO_HT40 &&
674 	    cfg->eeprom_params->regulatory_bands[6] ==
675 				EEPROM_REGULATORY_BAND_NO_HT40)
676 		return n_channels;
677 
678 	/* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
679 	for (band = 6; band <= 7; band++) {
680 		enum nl80211_band ieeeband;
681 
682 		iwl_init_band_reference(cfg, eeprom, eeprom_size, band,
683 					&eeprom_ch_count, &eeprom_ch_info,
684 					&eeprom_ch_array);
685 
686 		/* EEPROM band 6 is 2.4, band 7 is 5 GHz */
687 		ieeeband = (band == 6) ? NL80211_BAND_2GHZ
688 				       : NL80211_BAND_5GHZ;
689 
690 		/* Loop through each band adding each of the channels */
691 		for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) {
692 			/* Set up driver's info for lower half */
693 			iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband,
694 					       eeprom_ch_array[ch_idx],
695 					       &eeprom_ch_info[ch_idx],
696 					       IEEE80211_CHAN_NO_HT40PLUS);
697 
698 			/* Set up driver's info for upper half */
699 			iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband,
700 					       eeprom_ch_array[ch_idx] + 4,
701 					       &eeprom_ch_info[ch_idx],
702 					       IEEE80211_CHAN_NO_HT40MINUS);
703 		}
704 	}
705 
706 	return n_channels;
707 }
708 
709 int iwl_init_sband_channels(struct iwl_nvm_data *data,
710 			    struct ieee80211_supported_band *sband,
711 			    int n_channels, enum nl80211_band band)
712 {
713 	struct ieee80211_channel *chan = &data->channels[0];
714 	int n = 0, idx = 0;
715 
716 	while (idx < n_channels && chan->band != band)
717 		chan = &data->channels[++idx];
718 
719 	sband->channels = &data->channels[idx];
720 
721 	while (idx < n_channels && chan->band == band) {
722 		chan = &data->channels[++idx];
723 		n++;
724 	}
725 
726 	sband->n_channels = n;
727 
728 	return n;
729 }
730 
731 #define MAX_BIT_RATE_40_MHZ	150 /* Mbps */
732 #define MAX_BIT_RATE_20_MHZ	72 /* Mbps */
733 
734 void iwl_init_ht_hw_capab(const struct iwl_cfg *cfg,
735 			  struct iwl_nvm_data *data,
736 			  struct ieee80211_sta_ht_cap *ht_info,
737 			  enum nl80211_band band,
738 			  u8 tx_chains, u8 rx_chains)
739 {
740 	int max_bit_rate = 0;
741 
742 	tx_chains = hweight8(tx_chains);
743 	if (cfg->rx_with_siso_diversity)
744 		rx_chains = 1;
745 	else
746 		rx_chains = hweight8(rx_chains);
747 
748 	if (!(data->sku_cap_11n_enable) || !cfg->ht_params) {
749 		ht_info->ht_supported = false;
750 		return;
751 	}
752 
753 	if (data->sku_cap_mimo_disabled)
754 		rx_chains = 1;
755 
756 	ht_info->ht_supported = true;
757 	ht_info->cap = IEEE80211_HT_CAP_DSSSCCK40;
758 
759 	if (cfg->ht_params->stbc) {
760 		ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
761 
762 		if (tx_chains > 1)
763 			ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
764 	}
765 
766 	if (cfg->ht_params->ldpc)
767 		ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
768 
769 	if ((cfg->mq_rx_supported &&
770 	     iwlwifi_mod_params.amsdu_size != IWL_AMSDU_4K) ||
771 	     iwlwifi_mod_params.amsdu_size >= IWL_AMSDU_8K)
772 		ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
773 
774 	ht_info->ampdu_factor = cfg->max_ht_ampdu_exponent;
775 	ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
776 
777 	ht_info->mcs.rx_mask[0] = 0xFF;
778 	if (rx_chains >= 2)
779 		ht_info->mcs.rx_mask[1] = 0xFF;
780 	if (rx_chains >= 3)
781 		ht_info->mcs.rx_mask[2] = 0xFF;
782 
783 	if (cfg->ht_params->ht_greenfield_support)
784 		ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
785 	ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
786 
787 	max_bit_rate = MAX_BIT_RATE_20_MHZ;
788 
789 	if (cfg->ht_params->ht40_bands & BIT(band)) {
790 		ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
791 		ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
792 		max_bit_rate = MAX_BIT_RATE_40_MHZ;
793 	}
794 
795 	/* Highest supported Rx data rate */
796 	max_bit_rate *= rx_chains;
797 	WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
798 	ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
799 
800 	/* Tx MCS capabilities */
801 	ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
802 	if (tx_chains != rx_chains) {
803 		ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
804 		ht_info->mcs.tx_params |= ((tx_chains - 1) <<
805 				IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
806 	}
807 }
808 
809 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
810 			    struct iwl_nvm_data *data,
811 			    const u8 *eeprom, size_t eeprom_size)
812 {
813 	int n_channels = iwl_init_channel_map(dev, cfg, data,
814 					      eeprom, eeprom_size);
815 	int n_used = 0;
816 	struct ieee80211_supported_band *sband;
817 
818 	sband = &data->bands[NL80211_BAND_2GHZ];
819 	sband->band = NL80211_BAND_2GHZ;
820 	sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
821 	sband->n_bitrates = N_RATES_24;
822 	n_used += iwl_init_sband_channels(data, sband, n_channels,
823 					  NL80211_BAND_2GHZ);
824 	iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ,
825 			     data->valid_tx_ant, data->valid_rx_ant);
826 
827 	sband = &data->bands[NL80211_BAND_5GHZ];
828 	sband->band = NL80211_BAND_5GHZ;
829 	sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
830 	sband->n_bitrates = N_RATES_52;
831 	n_used += iwl_init_sband_channels(data, sband, n_channels,
832 					  NL80211_BAND_5GHZ);
833 	iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ,
834 			     data->valid_tx_ant, data->valid_rx_ant);
835 
836 	if (n_channels != n_used)
837 		IWL_ERR_DEV(dev, "EEPROM: used only %d of %d channels\n",
838 			    n_used, n_channels);
839 }
840 
841 /* EEPROM data functions */
842 
843 struct iwl_nvm_data *
844 iwl_parse_eeprom_data(struct device *dev, const struct iwl_cfg *cfg,
845 		      const u8 *eeprom, size_t eeprom_size)
846 {
847 	struct iwl_nvm_data *data;
848 	const void *tmp;
849 	u16 radio_cfg, sku;
850 
851 	if (WARN_ON(!cfg || !cfg->eeprom_params))
852 		return NULL;
853 
854 	data = kzalloc(sizeof(*data) +
855 		       sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS,
856 		       GFP_KERNEL);
857 	if (!data)
858 		return NULL;
859 
860 	/* get MAC address(es) */
861 	tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_MAC_ADDRESS);
862 	if (!tmp)
863 		goto err_free;
864 	memcpy(data->hw_addr, tmp, ETH_ALEN);
865 	data->n_hw_addrs = iwl_eeprom_query16(eeprom, eeprom_size,
866 					      EEPROM_NUM_MAC_ADDRESS);
867 
868 	if (iwl_eeprom_read_calib(eeprom, eeprom_size, data))
869 		goto err_free;
870 
871 	tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_XTAL);
872 	if (!tmp)
873 		goto err_free;
874 	memcpy(data->xtal_calib, tmp, sizeof(data->xtal_calib));
875 
876 	tmp = iwl_eeprom_query_addr(eeprom, eeprom_size,
877 				    EEPROM_RAW_TEMPERATURE);
878 	if (!tmp)
879 		goto err_free;
880 	data->raw_temperature = *(__le16 *)tmp;
881 
882 	tmp = iwl_eeprom_query_addr(eeprom, eeprom_size,
883 				    EEPROM_KELVIN_TEMPERATURE);
884 	if (!tmp)
885 		goto err_free;
886 	data->kelvin_temperature = *(__le16 *)tmp;
887 	data->kelvin_voltage = *((__le16 *)tmp + 1);
888 
889 	radio_cfg = iwl_eeprom_query16(eeprom, eeprom_size,
890 					     EEPROM_RADIO_CONFIG);
891 	data->radio_cfg_dash = EEPROM_RF_CFG_DASH_MSK(radio_cfg);
892 	data->radio_cfg_pnum = EEPROM_RF_CFG_PNUM_MSK(radio_cfg);
893 	data->radio_cfg_step = EEPROM_RF_CFG_STEP_MSK(radio_cfg);
894 	data->radio_cfg_type = EEPROM_RF_CFG_TYPE_MSK(radio_cfg);
895 	data->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg);
896 	data->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
897 
898 	sku = iwl_eeprom_query16(eeprom, eeprom_size,
899 				 EEPROM_SKU_CAP);
900 	data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE;
901 	data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE;
902 	data->sku_cap_band_24GHz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ;
903 	data->sku_cap_band_52GHz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ;
904 	data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE;
905 	if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
906 		data->sku_cap_11n_enable = false;
907 
908 	data->nvm_version = iwl_eeprom_query16(eeprom, eeprom_size,
909 					       EEPROM_VERSION);
910 
911 	/* check overrides (some devices have wrong EEPROM) */
912 	if (cfg->valid_tx_ant)
913 		data->valid_tx_ant = cfg->valid_tx_ant;
914 	if (cfg->valid_rx_ant)
915 		data->valid_rx_ant = cfg->valid_rx_ant;
916 
917 	if (!data->valid_tx_ant || !data->valid_rx_ant) {
918 		IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n",
919 			    data->valid_tx_ant, data->valid_rx_ant);
920 		goto err_free;
921 	}
922 
923 	iwl_init_sbands(dev, cfg, data, eeprom, eeprom_size);
924 
925 	return data;
926  err_free:
927 	kfree(data);
928 	return NULL;
929 }
930 IWL_EXPORT_SYMBOL(iwl_parse_eeprom_data);
931 
932 /* helper functions */
933 int iwl_nvm_check_version(struct iwl_nvm_data *data,
934 			     struct iwl_trans *trans)
935 {
936 	if (data->nvm_version >= trans->cfg->nvm_ver ||
937 	    data->calib_version >= trans->cfg->nvm_calib_ver) {
938 		IWL_DEBUG_INFO(trans, "device EEPROM VER=0x%x, CALIB=0x%x\n",
939 			       data->nvm_version, data->calib_version);
940 		return 0;
941 	}
942 
943 	IWL_ERR(trans,
944 		"Unsupported (too old) EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
945 		data->nvm_version, trans->cfg->nvm_ver,
946 		data->calib_version,  trans->cfg->nvm_calib_ver);
947 	return -EINVAL;
948 }
949 IWL_EXPORT_SYMBOL(iwl_nvm_check_version);
950