1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2022 Intel Corporation 4 */ 5 #include <linux/firmware.h> 6 #include "iwl-drv.h" 7 #include "iwl-trans.h" 8 #include "iwl-dbg-tlv.h" 9 #include "fw/dbg.h" 10 #include "fw/runtime.h" 11 12 /** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV 20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 21 */ 22 enum iwl_dbg_tlv_type { 23 IWL_DBG_TLV_TYPE_DEBUG_INFO = 24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 25 IWL_DBG_TLV_TYPE_BUF_ALLOC, 26 IWL_DBG_TLV_TYPE_HCMD, 27 IWL_DBG_TLV_TYPE_REGION, 28 IWL_DBG_TLV_TYPE_TRIGGER, 29 IWL_DBG_TLV_TYPE_CONF_SET, 30 IWL_DBG_TLV_TYPE_NUM, 31 }; 32 33 /** 34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 35 * @min_ver: min version supported 36 * @max_ver: max version supported 37 */ 38 struct iwl_dbg_tlv_ver_data { 39 int min_ver; 40 int max_ver; 41 }; 42 43 /** 44 * struct iwl_dbg_tlv_timer_node - timer node struct 45 * @list: list of &struct iwl_dbg_tlv_timer_node 46 * @timer: timer 47 * @fwrt: &struct iwl_fw_runtime 48 * @tlv: TLV attach to the timer node 49 */ 50 struct iwl_dbg_tlv_timer_node { 51 struct list_head list; 52 struct timer_list timer; 53 struct iwl_fw_runtime *fwrt; 54 struct iwl_ucode_tlv *tlv; 55 }; 56 57 static const struct iwl_dbg_tlv_ver_data 58 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,}, 63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,}, 65 }; 66 67 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, 68 struct list_head *list) 69 { 70 u32 len = le32_to_cpu(tlv->length); 71 struct iwl_dbg_tlv_node *node; 72 73 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 74 if (!node) 75 return -ENOMEM; 76 77 memcpy(&node->tlv, tlv, sizeof(node->tlv)); 78 memcpy(node->tlv.data, tlv->data, len); 79 list_add_tail(&node->list, list); 80 81 return 0; 82 } 83 84 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) 85 { 86 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 87 u32 type = le32_to_cpu(tlv->type); 88 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 89 u32 ver = le32_to_cpu(hdr->version); 90 91 if (ver < dbg_ver_table[tlv_idx].min_ver || 92 ver > dbg_ver_table[tlv_idx].max_ver) 93 return false; 94 95 return true; 96 } 97 98 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 99 const struct iwl_ucode_tlv *tlv) 100 { 101 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; 102 103 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 104 return -EINVAL; 105 106 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 107 debug_info->debug_cfg_name); 108 109 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 110 } 111 112 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 113 const struct iwl_ucode_tlv *tlv) 114 { 115 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; 116 u32 buf_location; 117 u32 alloc_id; 118 119 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 120 return -EINVAL; 121 122 buf_location = le32_to_cpu(alloc->buf_location); 123 alloc_id = le32_to_cpu(alloc->alloc_id); 124 125 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 126 buf_location >= IWL_FW_INI_LOCATION_NUM) 127 goto err; 128 129 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 130 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 131 goto err; 132 133 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 134 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 135 goto err; 136 137 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 138 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 139 goto err; 140 141 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH && 142 alloc->req_size == 0) { 143 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n"); 144 return -EINVAL; 145 } 146 147 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 148 149 return 0; 150 err: 151 IWL_ERR(trans, 152 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 153 alloc_id, buf_location); 154 return -EINVAL; 155 } 156 157 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 158 const struct iwl_ucode_tlv *tlv) 159 { 160 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; 161 u32 tp = le32_to_cpu(hcmd->time_point); 162 163 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 164 return -EINVAL; 165 166 /* Host commands can not be sent in early time point since the FW 167 * is not ready 168 */ 169 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 170 tp >= IWL_FW_INI_TIME_POINT_NUM || 171 tp == IWL_FW_INI_TIME_POINT_EARLY) { 172 IWL_ERR(trans, 173 "WRT: Invalid time point %u for host command TLV\n", 174 tp); 175 return -EINVAL; 176 } 177 178 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 179 } 180 181 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 182 const struct iwl_ucode_tlv *tlv) 183 { 184 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; 185 struct iwl_ucode_tlv **active_reg; 186 u32 id = le32_to_cpu(reg->id); 187 u8 type = reg->type; 188 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 189 190 /* 191 * The higher part of the ID from version 2 is debug policy. 192 * The id will be only lsb 16 bits, so mask it out. 193 */ 194 if (le32_to_cpu(reg->hdr.version) >= 2) 195 id &= IWL_FW_INI_REGION_ID_MASK; 196 197 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 198 return -EINVAL; 199 200 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */ 201 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n", 202 IWL_FW_INI_MAX_NAME, reg->name); 203 204 if (id >= IWL_FW_INI_MAX_REGION_ID) { 205 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 206 return -EINVAL; 207 } 208 209 if (type <= IWL_FW_INI_REGION_INVALID || 210 type >= IWL_FW_INI_REGION_NUM) { 211 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 212 return -EINVAL; 213 } 214 215 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 216 !trans->ops->read_config32) { 217 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 218 return -EOPNOTSUPP; 219 } 220 221 if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) { 222 trans->dbg.imr_data.sram_addr = 223 le32_to_cpu(reg->internal_buffer.base_addr); 224 trans->dbg.imr_data.sram_size = 225 le32_to_cpu(reg->internal_buffer.size); 226 } 227 228 229 active_reg = &trans->dbg.active_regions[id]; 230 if (*active_reg) { 231 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 232 233 kfree(*active_reg); 234 } 235 236 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 237 if (!*active_reg) 238 return -ENOMEM; 239 240 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 241 242 return 0; 243 } 244 245 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 246 const struct iwl_ucode_tlv *tlv) 247 { 248 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; 249 struct iwl_fw_ini_trigger_tlv *dup_trig; 250 u32 tp = le32_to_cpu(trig->time_point); 251 u32 rf = le32_to_cpu(trig->reset_fw); 252 struct iwl_ucode_tlv *dup = NULL; 253 int ret; 254 255 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 256 return -EINVAL; 257 258 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 259 tp >= IWL_FW_INI_TIME_POINT_NUM) { 260 IWL_ERR(trans, 261 "WRT: Invalid time point %u for trigger TLV\n", 262 tp); 263 return -EINVAL; 264 } 265 266 IWL_DEBUG_FW(trans, 267 "WRT: time point %u for trigger TLV with reset_fw %u\n", 268 tp, rf); 269 trans->dbg.last_tp_resetfw = 0xFF; 270 if (!le32_to_cpu(trig->occurrences)) { 271 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 272 GFP_KERNEL); 273 if (!dup) 274 return -ENOMEM; 275 dup_trig = (void *)dup->data; 276 dup_trig->occurrences = cpu_to_le32(-1); 277 tlv = dup; 278 } 279 280 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 281 kfree(dup); 282 283 return ret; 284 } 285 286 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans, 287 const struct iwl_ucode_tlv *tlv) 288 { 289 const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data; 290 u32 tp = le32_to_cpu(conf_set->time_point); 291 u32 type = le32_to_cpu(conf_set->set_type); 292 293 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 294 tp >= IWL_FW_INI_TIME_POINT_NUM) { 295 IWL_DEBUG_FW(trans, 296 "WRT: Invalid time point %u for config set TLV\n", tp); 297 return -EINVAL; 298 } 299 300 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID || 301 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) { 302 IWL_DEBUG_FW(trans, 303 "WRT: Invalid config set type %u for config set TLV\n", type); 304 return -EINVAL; 305 } 306 307 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list); 308 } 309 310 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 311 const struct iwl_ucode_tlv *tlv) = { 312 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 313 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 314 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 315 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 316 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 317 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set, 318 }; 319 320 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, 321 bool ext) 322 { 323 enum iwl_ini_cfg_state *cfg_state = ext ? 324 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 325 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 326 u32 type; 327 u32 tlv_idx; 328 u32 domain; 329 int ret; 330 331 if (le32_to_cpu(tlv->length) < sizeof(*hdr)) 332 return; 333 334 type = le32_to_cpu(tlv->type); 335 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 336 domain = le32_to_cpu(hdr->domain); 337 338 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 339 !(domain & trans->dbg.domains_bitmap)) { 340 IWL_DEBUG_FW(trans, 341 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 342 domain, trans->dbg.domains_bitmap); 343 return; 344 } 345 346 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 347 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 348 goto out_err; 349 } 350 351 if (!iwl_dbg_tlv_ver_support(tlv)) { 352 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 353 le32_to_cpu(hdr->version)); 354 goto out_err; 355 } 356 357 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 358 if (ret) { 359 IWL_WARN(trans, 360 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 361 type, ret, ext); 362 goto out_err; 363 } 364 365 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 366 *cfg_state = IWL_INI_CFG_STATE_LOADED; 367 368 return; 369 370 out_err: 371 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 372 } 373 374 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 375 { 376 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 377 struct iwl_dbg_tlv_timer_node *node, *tmp; 378 379 list_for_each_entry_safe(node, tmp, timer_list, list) { 380 timer_shutdown_sync(&node->timer); 381 list_del(&node->list); 382 kfree(node); 383 } 384 } 385 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 386 387 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 388 enum iwl_fw_ini_allocation_id alloc_id) 389 { 390 struct iwl_fw_mon *fw_mon; 391 int i; 392 393 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 394 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 395 return; 396 397 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 398 399 for (i = 0; i < fw_mon->num_frags; i++) { 400 struct iwl_dram_data *frag = &fw_mon->frags[i]; 401 402 dma_free_coherent(trans->dev, frag->size, frag->block, 403 frag->physical); 404 405 frag->physical = 0; 406 frag->block = NULL; 407 frag->size = 0; 408 } 409 410 kfree(fw_mon->frags); 411 fw_mon->frags = NULL; 412 fw_mon->num_frags = 0; 413 } 414 415 void iwl_dbg_tlv_free(struct iwl_trans *trans) 416 { 417 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 418 int i; 419 420 iwl_dbg_tlv_del_timers(trans); 421 422 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 423 struct iwl_ucode_tlv **active_reg = 424 &trans->dbg.active_regions[i]; 425 426 kfree(*active_reg); 427 *active_reg = NULL; 428 } 429 430 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 431 &trans->dbg.debug_info_tlv_list, list) { 432 list_del(&tlv_node->list); 433 kfree(tlv_node); 434 } 435 436 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 437 struct iwl_dbg_tlv_time_point_data *tp = 438 &trans->dbg.time_point[i]; 439 440 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 441 list) { 442 list_del(&tlv_node->list); 443 kfree(tlv_node); 444 } 445 446 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 447 list) { 448 list_del(&tlv_node->list); 449 kfree(tlv_node); 450 } 451 452 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 453 &tp->active_trig_list, list) { 454 list_del(&tlv_node->list); 455 kfree(tlv_node); 456 } 457 458 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 459 &tp->config_list, list) { 460 list_del(&tlv_node->list); 461 kfree(tlv_node); 462 } 463 464 } 465 466 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 467 iwl_dbg_tlv_fragments_free(trans, i); 468 } 469 470 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 471 size_t len) 472 { 473 const struct iwl_ucode_tlv *tlv; 474 u32 tlv_len; 475 476 while (len >= sizeof(*tlv)) { 477 len -= sizeof(*tlv); 478 tlv = (const void *)data; 479 480 tlv_len = le32_to_cpu(tlv->length); 481 482 if (len < tlv_len) { 483 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 484 len, tlv_len); 485 return -EINVAL; 486 } 487 len -= ALIGN(tlv_len, 4); 488 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 489 490 iwl_dbg_tlv_alloc(trans, tlv, true); 491 } 492 493 return 0; 494 } 495 496 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 497 { 498 const struct firmware *fw; 499 const char *yoyo_bin = "iwl-debug-yoyo.bin"; 500 int res; 501 502 if (!iwlwifi_mod_params.enable_ini || 503 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000) 504 return; 505 506 res = firmware_request_nowarn(&fw, yoyo_bin, dev); 507 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin); 508 509 if (res) 510 return; 511 512 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 513 514 release_firmware(fw); 515 } 516 517 void iwl_dbg_tlv_init(struct iwl_trans *trans) 518 { 519 int i; 520 521 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 522 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 523 524 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 525 struct iwl_dbg_tlv_time_point_data *tp = 526 &trans->dbg.time_point[i]; 527 528 INIT_LIST_HEAD(&tp->trig_list); 529 INIT_LIST_HEAD(&tp->hcmd_list); 530 INIT_LIST_HEAD(&tp->active_trig_list); 531 INIT_LIST_HEAD(&tp->config_list); 532 } 533 } 534 535 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 536 struct iwl_dram_data *frag, u32 pages) 537 { 538 void *block = NULL; 539 dma_addr_t physical; 540 541 if (!frag || frag->size || !pages) 542 return -EIO; 543 544 /* 545 * We try to allocate as many pages as we can, starting with 546 * the requested amount and going down until we can allocate 547 * something. Because of DIV_ROUND_UP(), pages will never go 548 * down to 0 and stop the loop, so stop when pages reaches 1, 549 * which is too small anyway. 550 */ 551 while (pages > 1) { 552 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 553 &physical, 554 GFP_KERNEL | __GFP_NOWARN); 555 if (block) 556 break; 557 558 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 559 pages * PAGE_SIZE); 560 561 pages = DIV_ROUND_UP(pages, 2); 562 } 563 564 if (!block) 565 return -ENOMEM; 566 567 frag->physical = physical; 568 frag->block = block; 569 frag->size = pages * PAGE_SIZE; 570 571 return pages; 572 } 573 574 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 575 enum iwl_fw_ini_allocation_id alloc_id) 576 { 577 struct iwl_fw_mon *fw_mon; 578 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 579 u32 num_frags, remain_pages, frag_pages; 580 int i; 581 582 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 583 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 584 return -EIO; 585 586 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 587 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 588 589 if (fw_mon->num_frags || 590 fw_mon_cfg->buf_location != 591 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 592 return 0; 593 594 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 595 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 596 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 597 return -EIO; 598 num_frags = 1; 599 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ && 600 alloc_id > IWL_FW_INI_ALLOCATION_ID_DBGC3) { 601 return -EIO; 602 } 603 604 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 605 PAGE_SIZE); 606 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 607 num_frags = min_t(u32, num_frags, remain_pages); 608 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 609 610 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 611 if (!fw_mon->frags) 612 return -ENOMEM; 613 614 for (i = 0; i < num_frags; i++) { 615 int pages = min_t(u32, frag_pages, remain_pages); 616 617 IWL_DEBUG_FW(fwrt, 618 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 619 alloc_id, i, pages * PAGE_SIZE); 620 621 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 622 pages); 623 if (pages < 0) { 624 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 625 (remain_pages * PAGE_SIZE); 626 627 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 628 iwl_dbg_tlv_fragments_free(fwrt->trans, 629 alloc_id); 630 return pages; 631 } 632 break; 633 } 634 635 remain_pages -= pages; 636 fw_mon->num_frags++; 637 } 638 639 return 0; 640 } 641 642 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 643 enum iwl_fw_ini_allocation_id alloc_id) 644 { 645 struct iwl_fw_mon *fw_mon; 646 u32 remain_frags, num_commands; 647 int i, fw_mon_idx = 0; 648 649 if (!fw_has_capa(&fwrt->fw->ucode_capa, 650 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 651 return 0; 652 653 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 654 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 655 return -EIO; 656 657 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 658 IWL_FW_INI_LOCATION_DRAM_PATH) 659 return 0; 660 661 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 662 663 /* the first fragment of DBGC1 is given to the FW via register 664 * or context info 665 */ 666 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 667 fw_mon_idx++; 668 669 remain_frags = fw_mon->num_frags - fw_mon_idx; 670 if (!remain_frags) 671 return 0; 672 673 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 674 675 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 676 alloc_id); 677 678 for (i = 0; i < num_commands; i++) { 679 u32 num_frags = min_t(u32, remain_frags, 680 BUF_ALLOC_MAX_NUM_FRAGS); 681 struct iwl_buf_alloc_cmd data = { 682 .alloc_id = cpu_to_le32(alloc_id), 683 .num_frags = cpu_to_le32(num_frags), 684 .buf_location = 685 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 686 }; 687 struct iwl_host_cmd hcmd = { 688 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 689 .data[0] = &data, 690 .len[0] = sizeof(data), 691 .flags = CMD_SEND_IN_RFKILL, 692 }; 693 int ret, j; 694 695 for (j = 0; j < num_frags; j++) { 696 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 697 struct iwl_dram_data *fw_mon_frag = 698 &fw_mon->frags[fw_mon_idx++]; 699 700 frag->addr = cpu_to_le64(fw_mon_frag->physical); 701 frag->size = cpu_to_le32(fw_mon_frag->size); 702 } 703 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 704 if (ret) 705 return ret; 706 707 remain_frags -= num_frags; 708 } 709 710 return 0; 711 } 712 713 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 714 { 715 int ret, i; 716 717 if (fw_has_capa(&fwrt->fw->ucode_capa, 718 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 719 return; 720 721 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 722 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 723 if (ret) 724 IWL_WARN(fwrt, 725 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 726 i, ret); 727 } 728 } 729 730 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt, 731 enum iwl_fw_ini_allocation_id alloc_id, 732 struct iwl_dram_info *dram_info) 733 { 734 struct iwl_fw_mon *fw_mon; 735 u32 remain_frags, num_frags; 736 int j, fw_mon_idx = 0; 737 struct iwl_buf_alloc_cmd *data; 738 739 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 740 IWL_FW_INI_LOCATION_DRAM_PATH) { 741 IWL_DEBUG_FW(fwrt, "DRAM_PATH is not supported alloc_id %u\n", alloc_id); 742 return -1; 743 } 744 745 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 746 747 /* the first fragment of DBGC1 is given to the FW via register 748 * or context info 749 */ 750 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 751 fw_mon_idx++; 752 753 remain_frags = fw_mon->num_frags - fw_mon_idx; 754 if (!remain_frags) 755 return -1; 756 757 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 758 data = &dram_info->dram_frags[alloc_id - 1]; 759 data->alloc_id = cpu_to_le32(alloc_id); 760 data->num_frags = cpu_to_le32(num_frags); 761 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH); 762 763 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n", 764 cpu_to_le32(alloc_id), cpu_to_le32(num_frags)); 765 766 for (j = 0; j < num_frags; j++) { 767 struct iwl_buf_alloc_frag *frag = &data->frags[j]; 768 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; 769 770 frag->addr = cpu_to_le64(fw_mon_frag->physical); 771 frag->size = cpu_to_le32(fw_mon_frag->size); 772 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n"); 773 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n", 774 j, cpu_to_le64(fw_mon_frag->physical), 775 cpu_to_le32(fw_mon_frag->size)); 776 } 777 return 0; 778 } 779 780 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt) 781 { 782 int ret, i; 783 bool dram_alloc = false; 784 struct iwl_dram_data *frags = 785 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0]; 786 struct iwl_dram_info *dram_info; 787 788 if (!frags || !frags->block) 789 return; 790 791 dram_info = frags->block; 792 793 if (!fw_has_capa(&fwrt->fw->ucode_capa, 794 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 795 return; 796 797 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); 798 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); 799 800 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1; 801 i < IWL_FW_INI_ALLOCATION_NUM; i++) { 802 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info); 803 if (!ret) 804 dram_alloc = true; 805 else 806 IWL_INFO(fwrt, 807 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n", 808 i, ret); 809 } 810 811 if (dram_alloc) 812 IWL_DEBUG_FW(fwrt, "block data after %08x\n", 813 dram_info->first_word); 814 else 815 memset(frags->block, 0, sizeof(*dram_info)); 816 } 817 818 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 819 struct list_head *hcmd_list) 820 { 821 struct iwl_dbg_tlv_node *node; 822 823 list_for_each_entry(node, hcmd_list, list) { 824 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 825 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 826 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 827 struct iwl_host_cmd cmd = { 828 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 829 .len = { hcmd_len, }, 830 .data = { hcmd_data->data, }, 831 }; 832 833 iwl_trans_send_cmd(fwrt->trans, &cmd); 834 } 835 } 836 837 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt, 838 struct list_head *conf_list) 839 { 840 struct iwl_dbg_tlv_node *node; 841 842 list_for_each_entry(node, conf_list, list) { 843 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data; 844 u32 count, address, value; 845 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8; 846 u32 type = le32_to_cpu(config_list->set_type); 847 u32 offset = le32_to_cpu(config_list->addr_offset); 848 849 switch (type) { 850 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: { 851 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 852 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n"); 853 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n"); 854 continue; 855 } 856 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len); 857 for (count = 0; count < len; count++) { 858 address = le32_to_cpu(config_list->addr_val[count].address); 859 value = le32_to_cpu(config_list->addr_val[count].value); 860 iwl_trans_write_prph(fwrt->trans, address + offset, value); 861 } 862 iwl_trans_release_nic_access(fwrt->trans); 863 break; 864 } 865 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: { 866 for (count = 0; count < len; count++) { 867 address = le32_to_cpu(config_list->addr_val[count].address); 868 value = le32_to_cpu(config_list->addr_val[count].value); 869 iwl_trans_write_mem32(fwrt->trans, address + offset, value); 870 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n", 871 count, address, value); 872 } 873 break; 874 } 875 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: { 876 for (count = 0; count < len; count++) { 877 address = le32_to_cpu(config_list->addr_val[count].address); 878 value = le32_to_cpu(config_list->addr_val[count].value); 879 iwl_write32(fwrt->trans, address + offset, value); 880 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", 881 count, address, value); 882 } 883 break; 884 } 885 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: { 886 struct iwl_dbgc1_info dram_info = {}; 887 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0]; 888 __le64 dram_base_addr; 889 __le32 dram_size; 890 u64 dram_addr; 891 u32 ret; 892 893 if (!frags) 894 break; 895 896 dram_base_addr = cpu_to_le64(frags->physical); 897 dram_size = cpu_to_le32(frags->size); 898 dram_addr = le64_to_cpu(dram_base_addr); 899 900 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n", 901 dram_base_addr, dram_size); 902 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n", 903 le32_to_cpu(config_list->addr_offset)); 904 for (count = 0; count < len; count++) { 905 address = le32_to_cpu(config_list->addr_val[count].address); 906 dram_info.dbgc1_add_lsb = 907 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400); 908 dram_info.dbgc1_add_msb = 909 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32); 910 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400); 911 ret = iwl_trans_write_mem(fwrt->trans, 912 address + offset, &dram_info, 4); 913 if (ret) { 914 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n"); 915 break; 916 } 917 } 918 break; 919 } 920 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: { 921 u32 debug_token_config = 922 le32_to_cpu(config_list->addr_val[0].value); 923 924 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n", 925 debug_token_config); 926 fwrt->trans->dbg.ucode_preset = debug_token_config; 927 break; 928 } 929 default: 930 break; 931 } 932 } 933 } 934 935 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 936 { 937 struct iwl_dbg_tlv_timer_node *timer_node = 938 from_timer(timer_node, t, timer); 939 struct iwl_fwrt_dump_data dump_data = { 940 .trig = (void *)timer_node->tlv->data, 941 }; 942 int ret; 943 944 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false); 945 if (!ret || ret == -EBUSY) { 946 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 947 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 948 949 if (!occur) 950 return; 951 952 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 953 } 954 } 955 956 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 957 { 958 struct iwl_dbg_tlv_node *node; 959 struct list_head *trig_list = 960 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 961 962 list_for_each_entry(node, trig_list, list) { 963 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 964 struct iwl_dbg_tlv_timer_node *timer_node; 965 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 966 u32 min_interval = 100; 967 968 if (!occur) 969 continue; 970 971 /* make sure there is at least one dword of data for the 972 * interval value 973 */ 974 if (le32_to_cpu(node->tlv.length) < 975 sizeof(*trig) + sizeof(__le32)) { 976 IWL_ERR(fwrt, 977 "WRT: Invalid periodic trigger data was not given\n"); 978 continue; 979 } 980 981 if (le32_to_cpu(trig->data[0]) < min_interval) { 982 IWL_WARN(fwrt, 983 "WRT: Override min interval from %u to %u msec\n", 984 le32_to_cpu(trig->data[0]), min_interval); 985 trig->data[0] = cpu_to_le32(min_interval); 986 } 987 988 collect_interval = le32_to_cpu(trig->data[0]); 989 990 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 991 if (!timer_node) { 992 IWL_ERR(fwrt, 993 "WRT: Failed to allocate periodic trigger\n"); 994 continue; 995 } 996 997 timer_node->fwrt = fwrt; 998 timer_node->tlv = &node->tlv; 999 timer_setup(&timer_node->timer, 1000 iwl_dbg_tlv_periodic_trig_handler, 0); 1001 1002 list_add_tail(&timer_node->list, 1003 &fwrt->trans->dbg.periodic_trig_list); 1004 1005 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 1006 1007 mod_timer(&timer_node->timer, 1008 jiffies + msecs_to_jiffies(collect_interval)); 1009 } 1010 } 1011 1012 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, 1013 const struct iwl_ucode_tlv *old) 1014 { 1015 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; 1016 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; 1017 const __le32 *new_data = new_trig->data, *old_data = old_trig->data; 1018 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 1019 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 1020 int i, j; 1021 1022 for (i = 0; i < new_dwords_num; i++) { 1023 bool match = false; 1024 1025 for (j = 0; j < old_dwords_num; j++) { 1026 if (new_data[i] == old_data[j]) { 1027 match = true; 1028 break; 1029 } 1030 } 1031 if (!match) 1032 return false; 1033 } 1034 1035 return true; 1036 } 1037 1038 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 1039 struct iwl_ucode_tlv *trig_tlv, 1040 struct iwl_dbg_tlv_node *node) 1041 { 1042 struct iwl_ucode_tlv *node_tlv = &node->tlv; 1043 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 1044 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1045 u32 policy = le32_to_cpu(trig->apply_policy); 1046 u32 size = le32_to_cpu(trig_tlv->length); 1047 u32 trig_data_len = size - sizeof(*trig); 1048 u32 offset = 0; 1049 1050 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 1051 u32 data_len = le32_to_cpu(node_tlv->length) - 1052 sizeof(*node_trig); 1053 1054 IWL_DEBUG_FW(fwrt, 1055 "WRT: Appending trigger data (time point %u)\n", 1056 le32_to_cpu(trig->time_point)); 1057 1058 offset += data_len; 1059 size += data_len; 1060 } else { 1061 IWL_DEBUG_FW(fwrt, 1062 "WRT: Overriding trigger data (time point %u)\n", 1063 le32_to_cpu(trig->time_point)); 1064 } 1065 1066 if (size != le32_to_cpu(node_tlv->length)) { 1067 struct list_head *prev = node->list.prev; 1068 struct iwl_dbg_tlv_node *tmp; 1069 1070 list_del(&node->list); 1071 1072 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 1073 if (!tmp) { 1074 IWL_WARN(fwrt, 1075 "WRT: No memory to override trigger (time point %u)\n", 1076 le32_to_cpu(trig->time_point)); 1077 1078 list_add(&node->list, prev); 1079 1080 return -ENOMEM; 1081 } 1082 1083 list_add(&tmp->list, prev); 1084 node_tlv = &tmp->tlv; 1085 node_trig = (void *)node_tlv->data; 1086 } 1087 1088 memcpy(node_trig->data + offset, trig->data, trig_data_len); 1089 node_tlv->length = cpu_to_le32(size); 1090 1091 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 1092 IWL_DEBUG_FW(fwrt, 1093 "WRT: Overriding trigger configuration (time point %u)\n", 1094 le32_to_cpu(trig->time_point)); 1095 1096 /* the first 11 dwords are configuration related */ 1097 memcpy(node_trig, trig, sizeof(__le32) * 11); 1098 } 1099 1100 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 1101 IWL_DEBUG_FW(fwrt, 1102 "WRT: Overriding trigger regions (time point %u)\n", 1103 le32_to_cpu(trig->time_point)); 1104 1105 node_trig->regions_mask = trig->regions_mask; 1106 } else { 1107 IWL_DEBUG_FW(fwrt, 1108 "WRT: Appending trigger regions (time point %u)\n", 1109 le32_to_cpu(trig->time_point)); 1110 1111 node_trig->regions_mask |= trig->regions_mask; 1112 } 1113 1114 return 0; 1115 } 1116 1117 static int 1118 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 1119 struct list_head *trig_list, 1120 struct iwl_ucode_tlv *trig_tlv) 1121 { 1122 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1123 struct iwl_dbg_tlv_node *node, *match = NULL; 1124 u32 policy = le32_to_cpu(trig->apply_policy); 1125 1126 list_for_each_entry(node, trig_list, list) { 1127 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 1128 break; 1129 1130 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 1131 is_trig_data_contained(trig_tlv, &node->tlv)) { 1132 match = node; 1133 break; 1134 } 1135 } 1136 1137 if (!match) { 1138 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 1139 le32_to_cpu(trig->time_point)); 1140 return iwl_dbg_tlv_add(trig_tlv, trig_list); 1141 } 1142 1143 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 1144 } 1145 1146 static void 1147 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 1148 struct iwl_dbg_tlv_time_point_data *tp) 1149 { 1150 struct iwl_dbg_tlv_node *node; 1151 struct list_head *trig_list = &tp->trig_list; 1152 struct list_head *active_trig_list = &tp->active_trig_list; 1153 1154 list_for_each_entry(node, trig_list, list) { 1155 struct iwl_ucode_tlv *tlv = &node->tlv; 1156 1157 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 1158 } 1159 } 1160 1161 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 1162 struct iwl_fwrt_dump_data *dump_data, 1163 union iwl_dbg_tlv_tp_data *tp_data, 1164 u32 trig_data) 1165 { 1166 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 1167 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 1168 1169 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 1170 pkt->hdr.group_id == wanted_hdr->group_id)) { 1171 struct iwl_rx_packet *fw_pkt = 1172 kmemdup(pkt, 1173 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 1174 GFP_ATOMIC); 1175 1176 if (!fw_pkt) 1177 return false; 1178 1179 dump_data->fw_pkt = fw_pkt; 1180 1181 return true; 1182 } 1183 1184 return false; 1185 } 1186 1187 static int 1188 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync, 1189 struct list_head *active_trig_list, 1190 union iwl_dbg_tlv_tp_data *tp_data, 1191 bool (*data_check)(struct iwl_fw_runtime *fwrt, 1192 struct iwl_fwrt_dump_data *dump_data, 1193 union iwl_dbg_tlv_tp_data *tp_data, 1194 u32 trig_data)) 1195 { 1196 struct iwl_dbg_tlv_node *node; 1197 1198 list_for_each_entry(node, active_trig_list, list) { 1199 struct iwl_fwrt_dump_data dump_data = { 1200 .trig = (void *)node->tlv.data, 1201 }; 1202 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 1203 data); 1204 int ret, i; 1205 u32 tp = le32_to_cpu(dump_data.trig->time_point); 1206 1207 1208 if (!num_data) { 1209 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1210 if (ret) 1211 return ret; 1212 } 1213 1214 for (i = 0; i < num_data; i++) { 1215 if (!data_check || 1216 data_check(fwrt, &dump_data, tp_data, 1217 le32_to_cpu(dump_data.trig->data[i]))) { 1218 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1219 if (ret) 1220 return ret; 1221 1222 break; 1223 } 1224 } 1225 1226 fwrt->trans->dbg.restart_required = FALSE; 1227 IWL_DEBUG_FW(fwrt, "WRT: tp %d, reset_fw %d\n", 1228 tp, dump_data.trig->reset_fw); 1229 IWL_DEBUG_FW(fwrt, 1230 "WRT: restart_required %d, last_tp_resetfw %d\n", 1231 fwrt->trans->dbg.restart_required, 1232 fwrt->trans->dbg.last_tp_resetfw); 1233 1234 if (fwrt->trans->trans_cfg->device_family == 1235 IWL_DEVICE_FAMILY_9000) { 1236 fwrt->trans->dbg.restart_required = TRUE; 1237 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT && 1238 fwrt->trans->dbg.last_tp_resetfw == 1239 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1240 fwrt->trans->dbg.restart_required = FALSE; 1241 fwrt->trans->dbg.last_tp_resetfw = 0xFF; 1242 IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n"); 1243 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1244 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) { 1245 IWL_DEBUG_FW(fwrt, "WRT: stop and reload firmware\n"); 1246 fwrt->trans->dbg.restart_required = TRUE; 1247 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1248 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1249 IWL_DEBUG_FW(fwrt, 1250 "WRT: stop only and no reload firmware\n"); 1251 fwrt->trans->dbg.restart_required = FALSE; 1252 fwrt->trans->dbg.last_tp_resetfw = 1253 le32_to_cpu(dump_data.trig->reset_fw); 1254 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1255 IWL_FW_INI_RESET_FW_MODE_NOTHING) { 1256 IWL_DEBUG_FW(fwrt, 1257 "WRT: nothing need to be done after debug collection\n"); 1258 } else { 1259 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n", 1260 le32_to_cpu(dump_data.trig->reset_fw)); 1261 } 1262 } 1263 return 0; 1264 } 1265 1266 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1267 { 1268 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1269 int ret, i; 1270 u32 failed_alloc = 0; 1271 1272 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) 1273 return; 1274 1275 IWL_DEBUG_FW(fwrt, 1276 "WRT: Generating active triggers list, domain 0x%x\n", 1277 fwrt->trans->dbg.domains_bitmap); 1278 1279 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1280 struct iwl_dbg_tlv_time_point_data *tp = 1281 &fwrt->trans->dbg.time_point[i]; 1282 1283 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1284 } 1285 1286 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1287 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1288 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1289 &fwrt->trans->dbg.fw_mon_cfg[i]; 1290 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1291 1292 if (dest == IWL_FW_INI_LOCATION_INVALID) { 1293 failed_alloc |= BIT(i); 1294 continue; 1295 } 1296 1297 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1298 *ini_dest = dest; 1299 1300 if (dest != *ini_dest) 1301 continue; 1302 1303 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1304 1305 if (ret) { 1306 IWL_WARN(fwrt, 1307 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1308 i, ret); 1309 failed_alloc |= BIT(i); 1310 } 1311 } 1312 1313 if (!failed_alloc) 1314 return; 1315 1316 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { 1317 struct iwl_fw_ini_region_tlv *reg; 1318 struct iwl_ucode_tlv **active_reg = 1319 &fwrt->trans->dbg.active_regions[i]; 1320 u32 reg_type; 1321 1322 if (!*active_reg) { 1323 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1324 continue; 1325 } 1326 1327 reg = (void *)(*active_reg)->data; 1328 reg_type = reg->type; 1329 1330 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || 1331 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) 1332 continue; 1333 1334 IWL_DEBUG_FW(fwrt, 1335 "WRT: removing allocation id %d from region id %d\n", 1336 le32_to_cpu(reg->dram_alloc_id), i); 1337 1338 failed_alloc &= ~BIT(le32_to_cpu(reg->dram_alloc_id)); 1339 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1340 1341 kfree(*active_reg); 1342 *active_reg = NULL; 1343 } 1344 } 1345 1346 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1347 enum iwl_fw_ini_time_point tp_id, 1348 union iwl_dbg_tlv_tp_data *tp_data, 1349 bool sync) 1350 { 1351 struct list_head *hcmd_list, *trig_list, *conf_list; 1352 1353 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1354 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1355 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1356 return; 1357 1358 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1359 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1360 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list; 1361 1362 switch (tp_id) { 1363 case IWL_FW_INI_TIME_POINT_EARLY: 1364 iwl_dbg_tlv_init_cfg(fwrt); 1365 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1366 iwl_dbg_tlv_update_drams(fwrt); 1367 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1368 break; 1369 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1370 iwl_dbg_tlv_apply_buffers(fwrt); 1371 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1372 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1373 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1374 break; 1375 case IWL_FW_INI_TIME_POINT_PERIODIC: 1376 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1377 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1378 break; 1379 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1380 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1381 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1382 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1383 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1384 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, 1385 iwl_dbg_tlv_check_fw_pkt); 1386 break; 1387 default: 1388 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1389 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1390 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1391 break; 1392 } 1393 } 1394 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point); 1395