1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2021 Intel Corporation 4 */ 5 #include <linux/firmware.h> 6 #include "iwl-drv.h" 7 #include "iwl-trans.h" 8 #include "iwl-dbg-tlv.h" 9 #include "fw/dbg.h" 10 #include "fw/runtime.h" 11 12 /** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV 20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 21 */ 22 enum iwl_dbg_tlv_type { 23 IWL_DBG_TLV_TYPE_DEBUG_INFO = 24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 25 IWL_DBG_TLV_TYPE_BUF_ALLOC, 26 IWL_DBG_TLV_TYPE_HCMD, 27 IWL_DBG_TLV_TYPE_REGION, 28 IWL_DBG_TLV_TYPE_TRIGGER, 29 IWL_DBG_TLV_TYPE_CONF_SET, 30 IWL_DBG_TLV_TYPE_NUM, 31 }; 32 33 /** 34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 35 * @min_ver: min version supported 36 * @max_ver: max version supported 37 */ 38 struct iwl_dbg_tlv_ver_data { 39 int min_ver; 40 int max_ver; 41 }; 42 43 /** 44 * struct iwl_dbg_tlv_timer_node - timer node struct 45 * @list: list of &struct iwl_dbg_tlv_timer_node 46 * @timer: timer 47 * @fwrt: &struct iwl_fw_runtime 48 * @tlv: TLV attach to the timer node 49 */ 50 struct iwl_dbg_tlv_timer_node { 51 struct list_head list; 52 struct timer_list timer; 53 struct iwl_fw_runtime *fwrt; 54 struct iwl_ucode_tlv *tlv; 55 }; 56 57 static const struct iwl_dbg_tlv_ver_data 58 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 2,}, 63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,}, 65 }; 66 67 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, 68 struct list_head *list) 69 { 70 u32 len = le32_to_cpu(tlv->length); 71 struct iwl_dbg_tlv_node *node; 72 73 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 74 if (!node) 75 return -ENOMEM; 76 77 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len); 78 list_add_tail(&node->list, list); 79 80 return 0; 81 } 82 83 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) 84 { 85 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 86 u32 type = le32_to_cpu(tlv->type); 87 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 88 u32 ver = le32_to_cpu(hdr->version); 89 90 if (ver < dbg_ver_table[tlv_idx].min_ver || 91 ver > dbg_ver_table[tlv_idx].max_ver) 92 return false; 93 94 return true; 95 } 96 97 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 98 const struct iwl_ucode_tlv *tlv) 99 { 100 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; 101 102 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 103 return -EINVAL; 104 105 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 106 debug_info->debug_cfg_name); 107 108 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 109 } 110 111 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 112 const struct iwl_ucode_tlv *tlv) 113 { 114 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; 115 u32 buf_location; 116 u32 alloc_id; 117 118 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 119 return -EINVAL; 120 121 buf_location = le32_to_cpu(alloc->buf_location); 122 alloc_id = le32_to_cpu(alloc->alloc_id); 123 124 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 125 buf_location >= IWL_FW_INI_LOCATION_NUM) 126 goto err; 127 128 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 129 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 130 goto err; 131 132 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 133 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 134 goto err; 135 136 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 137 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 138 goto err; 139 140 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 141 142 return 0; 143 err: 144 IWL_ERR(trans, 145 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 146 alloc_id, buf_location); 147 return -EINVAL; 148 } 149 150 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 151 const struct iwl_ucode_tlv *tlv) 152 { 153 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; 154 u32 tp = le32_to_cpu(hcmd->time_point); 155 156 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 157 return -EINVAL; 158 159 /* Host commands can not be sent in early time point since the FW 160 * is not ready 161 */ 162 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 163 tp >= IWL_FW_INI_TIME_POINT_NUM || 164 tp == IWL_FW_INI_TIME_POINT_EARLY) { 165 IWL_ERR(trans, 166 "WRT: Invalid time point %u for host command TLV\n", 167 tp); 168 return -EINVAL; 169 } 170 171 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 172 } 173 174 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 175 const struct iwl_ucode_tlv *tlv) 176 { 177 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; 178 struct iwl_ucode_tlv **active_reg; 179 u32 id = le32_to_cpu(reg->id); 180 u32 type = le32_to_cpu(reg->type); 181 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 182 183 /* 184 * The higher part of the ID in version 2 is irrelevant for 185 * us, so mask it out. 186 */ 187 if (le32_to_cpu(reg->hdr.version) == 2) 188 id &= IWL_FW_INI_REGION_V2_MASK; 189 190 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 191 return -EINVAL; 192 193 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */ 194 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n", 195 IWL_FW_INI_MAX_NAME, reg->name); 196 197 if (id >= IWL_FW_INI_MAX_REGION_ID) { 198 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 199 return -EINVAL; 200 } 201 202 if (type <= IWL_FW_INI_REGION_INVALID || 203 type >= IWL_FW_INI_REGION_NUM) { 204 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 205 return -EINVAL; 206 } 207 208 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 209 !trans->ops->read_config32) { 210 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 211 return -EOPNOTSUPP; 212 } 213 214 active_reg = &trans->dbg.active_regions[id]; 215 if (*active_reg) { 216 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 217 218 kfree(*active_reg); 219 } 220 221 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 222 if (!*active_reg) 223 return -ENOMEM; 224 225 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 226 227 return 0; 228 } 229 230 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 231 const struct iwl_ucode_tlv *tlv) 232 { 233 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; 234 struct iwl_fw_ini_trigger_tlv *dup_trig; 235 u32 tp = le32_to_cpu(trig->time_point); 236 struct iwl_ucode_tlv *dup = NULL; 237 int ret; 238 239 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 240 return -EINVAL; 241 242 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 243 tp >= IWL_FW_INI_TIME_POINT_NUM) { 244 IWL_ERR(trans, 245 "WRT: Invalid time point %u for trigger TLV\n", 246 tp); 247 return -EINVAL; 248 } 249 250 if (!le32_to_cpu(trig->occurrences)) { 251 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 252 GFP_KERNEL); 253 if (!dup) 254 return -ENOMEM; 255 dup_trig = (void *)dup->data; 256 dup_trig->occurrences = cpu_to_le32(-1); 257 tlv = dup; 258 } 259 260 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 261 kfree(dup); 262 263 return ret; 264 } 265 266 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans, 267 const struct iwl_ucode_tlv *tlv) 268 { 269 struct iwl_fw_ini_conf_set_tlv *conf_set = (void *)tlv->data; 270 u32 tp = le32_to_cpu(conf_set->time_point); 271 u32 type = le32_to_cpu(conf_set->set_type); 272 273 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 274 tp >= IWL_FW_INI_TIME_POINT_NUM) { 275 IWL_DEBUG_FW(trans, 276 "WRT: Invalid time point %u for config set TLV\n", tp); 277 return -EINVAL; 278 } 279 280 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID || 281 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) { 282 IWL_DEBUG_FW(trans, 283 "WRT: Invalid config set type %u for config set TLV\n", type); 284 return -EINVAL; 285 } 286 287 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list); 288 } 289 290 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 291 const struct iwl_ucode_tlv *tlv) = { 292 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 293 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 294 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 295 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 296 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 297 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set, 298 }; 299 300 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, 301 bool ext) 302 { 303 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 304 u32 type = le32_to_cpu(tlv->type); 305 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 306 u32 domain = le32_to_cpu(hdr->domain); 307 enum iwl_ini_cfg_state *cfg_state = ext ? 308 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 309 int ret; 310 311 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 312 !(domain & trans->dbg.domains_bitmap)) { 313 IWL_DEBUG_FW(trans, 314 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 315 domain, trans->dbg.domains_bitmap); 316 return; 317 } 318 319 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 320 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 321 goto out_err; 322 } 323 324 if (!iwl_dbg_tlv_ver_support(tlv)) { 325 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 326 le32_to_cpu(hdr->version)); 327 goto out_err; 328 } 329 330 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 331 if (ret) { 332 IWL_ERR(trans, 333 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 334 type, ret, ext); 335 goto out_err; 336 } 337 338 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 339 *cfg_state = IWL_INI_CFG_STATE_LOADED; 340 341 return; 342 343 out_err: 344 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 345 } 346 347 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 348 { 349 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 350 struct iwl_dbg_tlv_timer_node *node, *tmp; 351 352 list_for_each_entry_safe(node, tmp, timer_list, list) { 353 del_timer(&node->timer); 354 list_del(&node->list); 355 kfree(node); 356 } 357 } 358 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 359 360 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 361 enum iwl_fw_ini_allocation_id alloc_id) 362 { 363 struct iwl_fw_mon *fw_mon; 364 int i; 365 366 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 367 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 368 return; 369 370 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 371 372 for (i = 0; i < fw_mon->num_frags; i++) { 373 struct iwl_dram_data *frag = &fw_mon->frags[i]; 374 375 dma_free_coherent(trans->dev, frag->size, frag->block, 376 frag->physical); 377 378 frag->physical = 0; 379 frag->block = NULL; 380 frag->size = 0; 381 } 382 383 kfree(fw_mon->frags); 384 fw_mon->frags = NULL; 385 fw_mon->num_frags = 0; 386 } 387 388 void iwl_dbg_tlv_free(struct iwl_trans *trans) 389 { 390 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 391 int i; 392 393 iwl_dbg_tlv_del_timers(trans); 394 395 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 396 struct iwl_ucode_tlv **active_reg = 397 &trans->dbg.active_regions[i]; 398 399 kfree(*active_reg); 400 *active_reg = NULL; 401 } 402 403 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 404 &trans->dbg.debug_info_tlv_list, list) { 405 list_del(&tlv_node->list); 406 kfree(tlv_node); 407 } 408 409 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 410 struct iwl_dbg_tlv_time_point_data *tp = 411 &trans->dbg.time_point[i]; 412 413 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 414 list) { 415 list_del(&tlv_node->list); 416 kfree(tlv_node); 417 } 418 419 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 420 list) { 421 list_del(&tlv_node->list); 422 kfree(tlv_node); 423 } 424 425 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 426 &tp->active_trig_list, list) { 427 list_del(&tlv_node->list); 428 kfree(tlv_node); 429 } 430 431 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 432 &tp->config_list, list) { 433 list_del(&tlv_node->list); 434 kfree(tlv_node); 435 } 436 437 } 438 439 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 440 iwl_dbg_tlv_fragments_free(trans, i); 441 } 442 443 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 444 size_t len) 445 { 446 const struct iwl_ucode_tlv *tlv; 447 u32 tlv_len; 448 449 while (len >= sizeof(*tlv)) { 450 len -= sizeof(*tlv); 451 tlv = (void *)data; 452 453 tlv_len = le32_to_cpu(tlv->length); 454 455 if (len < tlv_len) { 456 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 457 len, tlv_len); 458 return -EINVAL; 459 } 460 len -= ALIGN(tlv_len, 4); 461 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 462 463 iwl_dbg_tlv_alloc(trans, tlv, true); 464 } 465 466 return 0; 467 } 468 469 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 470 { 471 const struct firmware *fw; 472 const char *yoyo_bin = "iwl-debug-yoyo.bin"; 473 int res; 474 475 if (!iwlwifi_mod_params.enable_ini || 476 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_9000) 477 return; 478 479 res = firmware_request_nowarn(&fw, yoyo_bin, dev); 480 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin); 481 482 if (res) 483 return; 484 485 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 486 487 release_firmware(fw); 488 } 489 490 void iwl_dbg_tlv_init(struct iwl_trans *trans) 491 { 492 int i; 493 494 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 495 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 496 497 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 498 struct iwl_dbg_tlv_time_point_data *tp = 499 &trans->dbg.time_point[i]; 500 501 INIT_LIST_HEAD(&tp->trig_list); 502 INIT_LIST_HEAD(&tp->hcmd_list); 503 INIT_LIST_HEAD(&tp->active_trig_list); 504 INIT_LIST_HEAD(&tp->config_list); 505 } 506 } 507 508 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 509 struct iwl_dram_data *frag, u32 pages) 510 { 511 void *block = NULL; 512 dma_addr_t physical; 513 514 if (!frag || frag->size || !pages) 515 return -EIO; 516 517 /* 518 * We try to allocate as many pages as we can, starting with 519 * the requested amount and going down until we can allocate 520 * something. Because of DIV_ROUND_UP(), pages will never go 521 * down to 0 and stop the loop, so stop when pages reaches 1, 522 * which is too small anyway. 523 */ 524 while (pages > 1) { 525 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 526 &physical, 527 GFP_KERNEL | __GFP_NOWARN); 528 if (block) 529 break; 530 531 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 532 pages * PAGE_SIZE); 533 534 pages = DIV_ROUND_UP(pages, 2); 535 } 536 537 if (!block) 538 return -ENOMEM; 539 540 frag->physical = physical; 541 frag->block = block; 542 frag->size = pages * PAGE_SIZE; 543 544 return pages; 545 } 546 547 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 548 enum iwl_fw_ini_allocation_id alloc_id) 549 { 550 struct iwl_fw_mon *fw_mon; 551 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 552 u32 num_frags, remain_pages, frag_pages; 553 int i; 554 555 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 556 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 557 return -EIO; 558 559 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 560 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 561 562 if (fw_mon->num_frags || 563 fw_mon_cfg->buf_location != 564 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 565 return 0; 566 567 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 568 if (!fw_has_capa(&fwrt->fw->ucode_capa, 569 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) { 570 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 571 return -EIO; 572 num_frags = 1; 573 } 574 575 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 576 PAGE_SIZE); 577 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 578 num_frags = min_t(u32, num_frags, remain_pages); 579 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 580 581 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 582 if (!fw_mon->frags) 583 return -ENOMEM; 584 585 for (i = 0; i < num_frags; i++) { 586 int pages = min_t(u32, frag_pages, remain_pages); 587 588 IWL_DEBUG_FW(fwrt, 589 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 590 alloc_id, i, pages * PAGE_SIZE); 591 592 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 593 pages); 594 if (pages < 0) { 595 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 596 (remain_pages * PAGE_SIZE); 597 598 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 599 iwl_dbg_tlv_fragments_free(fwrt->trans, 600 alloc_id); 601 return pages; 602 } 603 break; 604 } 605 606 remain_pages -= pages; 607 fw_mon->num_frags++; 608 } 609 610 return 0; 611 } 612 613 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 614 enum iwl_fw_ini_allocation_id alloc_id) 615 { 616 struct iwl_fw_mon *fw_mon; 617 u32 remain_frags, num_commands; 618 int i, fw_mon_idx = 0; 619 620 if (!fw_has_capa(&fwrt->fw->ucode_capa, 621 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 622 return 0; 623 624 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 625 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 626 return -EIO; 627 628 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 629 IWL_FW_INI_LOCATION_DRAM_PATH) 630 return 0; 631 632 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 633 634 /* the first fragment of DBGC1 is given to the FW via register 635 * or context info 636 */ 637 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 638 fw_mon_idx++; 639 640 remain_frags = fw_mon->num_frags - fw_mon_idx; 641 if (!remain_frags) 642 return 0; 643 644 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 645 646 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 647 alloc_id); 648 649 for (i = 0; i < num_commands; i++) { 650 u32 num_frags = min_t(u32, remain_frags, 651 BUF_ALLOC_MAX_NUM_FRAGS); 652 struct iwl_buf_alloc_cmd data = { 653 .alloc_id = cpu_to_le32(alloc_id), 654 .num_frags = cpu_to_le32(num_frags), 655 .buf_location = 656 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 657 }; 658 struct iwl_host_cmd hcmd = { 659 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 660 .data[0] = &data, 661 .len[0] = sizeof(data), 662 .flags = CMD_SEND_IN_RFKILL, 663 }; 664 int ret, j; 665 666 for (j = 0; j < num_frags; j++) { 667 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 668 struct iwl_dram_data *fw_mon_frag = 669 &fw_mon->frags[fw_mon_idx++]; 670 671 frag->addr = cpu_to_le64(fw_mon_frag->physical); 672 frag->size = cpu_to_le32(fw_mon_frag->size); 673 } 674 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 675 if (ret) 676 return ret; 677 678 remain_frags -= num_frags; 679 } 680 681 return 0; 682 } 683 684 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 685 { 686 int ret, i; 687 688 if (fw_has_capa(&fwrt->fw->ucode_capa, 689 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 690 return; 691 692 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 693 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 694 if (ret) 695 IWL_WARN(fwrt, 696 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 697 i, ret); 698 } 699 } 700 701 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt, 702 enum iwl_fw_ini_allocation_id alloc_id, 703 struct iwl_dram_info *dram_info) 704 { 705 struct iwl_fw_mon *fw_mon; 706 u32 remain_frags, num_frags; 707 int j, fw_mon_idx = 0; 708 struct iwl_buf_alloc_cmd *data; 709 710 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 711 IWL_FW_INI_LOCATION_DRAM_PATH) { 712 IWL_DEBUG_FW(fwrt, "DRAM_PATH is not supported alloc_id %u\n", alloc_id); 713 return -1; 714 } 715 716 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 717 718 /* the first fragment of DBGC1 is given to the FW via register 719 * or context info 720 */ 721 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 722 fw_mon_idx++; 723 724 remain_frags = fw_mon->num_frags - fw_mon_idx; 725 if (!remain_frags) 726 return -1; 727 728 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 729 data = &dram_info->dram_frags[alloc_id - 1]; 730 data->alloc_id = cpu_to_le32(alloc_id); 731 data->num_frags = cpu_to_le32(num_frags); 732 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH); 733 734 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n", 735 cpu_to_le32(alloc_id), cpu_to_le32(num_frags)); 736 737 for (j = 0; j < num_frags; j++) { 738 struct iwl_buf_alloc_frag *frag = &data->frags[j]; 739 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; 740 741 frag->addr = cpu_to_le64(fw_mon_frag->physical); 742 frag->size = cpu_to_le32(fw_mon_frag->size); 743 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n"); 744 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n", 745 j, cpu_to_le64(fw_mon_frag->physical), 746 cpu_to_le32(fw_mon_frag->size)); 747 } 748 return 0; 749 } 750 751 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt) 752 { 753 int ret, i, dram_alloc = 0; 754 struct iwl_dram_info dram_info; 755 struct iwl_dram_data *frags = 756 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0]; 757 758 if (!fw_has_capa(&fwrt->fw->ucode_capa, 759 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 760 return; 761 762 dram_info.first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); 763 dram_info.second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); 764 765 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1; 766 i <= IWL_FW_INI_ALLOCATION_ID_DBGC3; i++) { 767 ret = iwl_dbg_tlv_update_dram(fwrt, i, &dram_info); 768 if (!ret) 769 dram_alloc++; 770 else 771 IWL_WARN(fwrt, 772 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n", 773 i, ret); 774 } 775 if (dram_alloc) { 776 memcpy(frags->block, &dram_info, sizeof(dram_info)); 777 IWL_DEBUG_FW(fwrt, "block data after %016x\n", 778 *((int *)fwrt->trans->dbg.fw_mon_ini[1].frags[0].block)); 779 } 780 } 781 782 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 783 struct list_head *hcmd_list) 784 { 785 struct iwl_dbg_tlv_node *node; 786 787 list_for_each_entry(node, hcmd_list, list) { 788 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 789 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 790 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 791 struct iwl_host_cmd cmd = { 792 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 793 .len = { hcmd_len, }, 794 .data = { hcmd_data->data, }, 795 }; 796 797 iwl_trans_send_cmd(fwrt->trans, &cmd); 798 } 799 } 800 801 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt, 802 struct list_head *config_list) 803 { 804 struct iwl_dbg_tlv_node *node; 805 806 list_for_each_entry(node, config_list, list) { 807 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data; 808 u32 count, address, value; 809 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8; 810 u32 type = le32_to_cpu(config_list->set_type); 811 u32 offset = le32_to_cpu(config_list->addr_offset); 812 813 switch (type) { 814 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: { 815 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 816 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n"); 817 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n"); 818 continue; 819 } 820 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len); 821 for (count = 0; count < len; count++) { 822 address = le32_to_cpu(config_list->addr_val[count].address); 823 value = le32_to_cpu(config_list->addr_val[count].value); 824 iwl_trans_write_prph(fwrt->trans, address + offset, value); 825 } 826 iwl_trans_release_nic_access(fwrt->trans); 827 break; 828 } 829 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: { 830 for (count = 0; count < len; count++) { 831 address = le32_to_cpu(config_list->addr_val[count].address); 832 value = le32_to_cpu(config_list->addr_val[count].value); 833 iwl_trans_write_mem32(fwrt->trans, address + offset, value); 834 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n", 835 count, address, value); 836 } 837 break; 838 } 839 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: { 840 for (count = 0; count < len; count++) { 841 address = le32_to_cpu(config_list->addr_val[count].address); 842 value = le32_to_cpu(config_list->addr_val[count].value); 843 iwl_write32(fwrt->trans, address + offset, value); 844 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", 845 count, address, value); 846 } 847 break; 848 } 849 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: { 850 struct iwl_dbgc1_info dram_info = {}; 851 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0]; 852 __le64 dram_base_addr = cpu_to_le64(frags->physical); 853 __le32 dram_size = cpu_to_le32(frags->size); 854 u64 dram_addr = le64_to_cpu(dram_base_addr); 855 u32 ret; 856 857 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n", 858 dram_base_addr, dram_size); 859 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n", 860 le32_to_cpu(config_list->addr_offset)); 861 for (count = 0; count < len; count++) { 862 address = le32_to_cpu(config_list->addr_val[count].address); 863 dram_info.dbgc1_add_lsb = 864 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400); 865 dram_info.dbgc1_add_msb = 866 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32); 867 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400); 868 ret = iwl_trans_write_mem(fwrt->trans, 869 address + offset, &dram_info, 4); 870 if (ret) { 871 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n"); 872 break; 873 } 874 } 875 break; 876 } 877 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: { 878 u32 debug_token_config = 879 le32_to_cpu(config_list->addr_val[0].value); 880 881 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n", 882 debug_token_config); 883 fwrt->trans->dbg.ucode_preset = debug_token_config; 884 break; 885 } 886 default: 887 break; 888 } 889 } 890 } 891 892 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 893 { 894 struct iwl_dbg_tlv_timer_node *timer_node = 895 from_timer(timer_node, t, timer); 896 struct iwl_fwrt_dump_data dump_data = { 897 .trig = (void *)timer_node->tlv->data, 898 }; 899 int ret; 900 901 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false); 902 if (!ret || ret == -EBUSY) { 903 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 904 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 905 906 if (!occur) 907 return; 908 909 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 910 } 911 } 912 913 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 914 { 915 struct iwl_dbg_tlv_node *node; 916 struct list_head *trig_list = 917 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 918 919 list_for_each_entry(node, trig_list, list) { 920 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 921 struct iwl_dbg_tlv_timer_node *timer_node; 922 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 923 u32 min_interval = 100; 924 925 if (!occur) 926 continue; 927 928 /* make sure there is at least one dword of data for the 929 * interval value 930 */ 931 if (le32_to_cpu(node->tlv.length) < 932 sizeof(*trig) + sizeof(__le32)) { 933 IWL_ERR(fwrt, 934 "WRT: Invalid periodic trigger data was not given\n"); 935 continue; 936 } 937 938 if (le32_to_cpu(trig->data[0]) < min_interval) { 939 IWL_WARN(fwrt, 940 "WRT: Override min interval from %u to %u msec\n", 941 le32_to_cpu(trig->data[0]), min_interval); 942 trig->data[0] = cpu_to_le32(min_interval); 943 } 944 945 collect_interval = le32_to_cpu(trig->data[0]); 946 947 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 948 if (!timer_node) { 949 IWL_ERR(fwrt, 950 "WRT: Failed to allocate periodic trigger\n"); 951 continue; 952 } 953 954 timer_node->fwrt = fwrt; 955 timer_node->tlv = &node->tlv; 956 timer_setup(&timer_node->timer, 957 iwl_dbg_tlv_periodic_trig_handler, 0); 958 959 list_add_tail(&timer_node->list, 960 &fwrt->trans->dbg.periodic_trig_list); 961 962 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 963 964 mod_timer(&timer_node->timer, 965 jiffies + msecs_to_jiffies(collect_interval)); 966 } 967 } 968 969 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, 970 const struct iwl_ucode_tlv *old) 971 { 972 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; 973 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; 974 const __le32 *new_data = new_trig->data, *old_data = old_trig->data; 975 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 976 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 977 int i, j; 978 979 for (i = 0; i < new_dwords_num; i++) { 980 bool match = false; 981 982 for (j = 0; j < old_dwords_num; j++) { 983 if (new_data[i] == old_data[j]) { 984 match = true; 985 break; 986 } 987 } 988 if (!match) 989 return false; 990 } 991 992 return true; 993 } 994 995 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 996 struct iwl_ucode_tlv *trig_tlv, 997 struct iwl_dbg_tlv_node *node) 998 { 999 struct iwl_ucode_tlv *node_tlv = &node->tlv; 1000 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 1001 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1002 u32 policy = le32_to_cpu(trig->apply_policy); 1003 u32 size = le32_to_cpu(trig_tlv->length); 1004 u32 trig_data_len = size - sizeof(*trig); 1005 u32 offset = 0; 1006 1007 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 1008 u32 data_len = le32_to_cpu(node_tlv->length) - 1009 sizeof(*node_trig); 1010 1011 IWL_DEBUG_FW(fwrt, 1012 "WRT: Appending trigger data (time point %u)\n", 1013 le32_to_cpu(trig->time_point)); 1014 1015 offset += data_len; 1016 size += data_len; 1017 } else { 1018 IWL_DEBUG_FW(fwrt, 1019 "WRT: Overriding trigger data (time point %u)\n", 1020 le32_to_cpu(trig->time_point)); 1021 } 1022 1023 if (size != le32_to_cpu(node_tlv->length)) { 1024 struct list_head *prev = node->list.prev; 1025 struct iwl_dbg_tlv_node *tmp; 1026 1027 list_del(&node->list); 1028 1029 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 1030 if (!tmp) { 1031 IWL_WARN(fwrt, 1032 "WRT: No memory to override trigger (time point %u)\n", 1033 le32_to_cpu(trig->time_point)); 1034 1035 list_add(&node->list, prev); 1036 1037 return -ENOMEM; 1038 } 1039 1040 list_add(&tmp->list, prev); 1041 node_tlv = &tmp->tlv; 1042 node_trig = (void *)node_tlv->data; 1043 } 1044 1045 memcpy(node_trig->data + offset, trig->data, trig_data_len); 1046 node_tlv->length = cpu_to_le32(size); 1047 1048 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 1049 IWL_DEBUG_FW(fwrt, 1050 "WRT: Overriding trigger configuration (time point %u)\n", 1051 le32_to_cpu(trig->time_point)); 1052 1053 /* the first 11 dwords are configuration related */ 1054 memcpy(node_trig, trig, sizeof(__le32) * 11); 1055 } 1056 1057 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 1058 IWL_DEBUG_FW(fwrt, 1059 "WRT: Overriding trigger regions (time point %u)\n", 1060 le32_to_cpu(trig->time_point)); 1061 1062 node_trig->regions_mask = trig->regions_mask; 1063 } else { 1064 IWL_DEBUG_FW(fwrt, 1065 "WRT: Appending trigger regions (time point %u)\n", 1066 le32_to_cpu(trig->time_point)); 1067 1068 node_trig->regions_mask |= trig->regions_mask; 1069 } 1070 1071 return 0; 1072 } 1073 1074 static int 1075 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 1076 struct list_head *trig_list, 1077 struct iwl_ucode_tlv *trig_tlv) 1078 { 1079 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1080 struct iwl_dbg_tlv_node *node, *match = NULL; 1081 u32 policy = le32_to_cpu(trig->apply_policy); 1082 1083 list_for_each_entry(node, trig_list, list) { 1084 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 1085 break; 1086 1087 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 1088 is_trig_data_contained(trig_tlv, &node->tlv)) { 1089 match = node; 1090 break; 1091 } 1092 } 1093 1094 if (!match) { 1095 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 1096 le32_to_cpu(trig->time_point)); 1097 return iwl_dbg_tlv_add(trig_tlv, trig_list); 1098 } 1099 1100 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 1101 } 1102 1103 static void 1104 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 1105 struct iwl_dbg_tlv_time_point_data *tp) 1106 { 1107 struct iwl_dbg_tlv_node *node; 1108 struct list_head *trig_list = &tp->trig_list; 1109 struct list_head *active_trig_list = &tp->active_trig_list; 1110 1111 list_for_each_entry(node, trig_list, list) { 1112 struct iwl_ucode_tlv *tlv = &node->tlv; 1113 1114 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 1115 } 1116 } 1117 1118 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 1119 struct iwl_fwrt_dump_data *dump_data, 1120 union iwl_dbg_tlv_tp_data *tp_data, 1121 u32 trig_data) 1122 { 1123 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 1124 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 1125 1126 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 1127 pkt->hdr.group_id == wanted_hdr->group_id)) { 1128 struct iwl_rx_packet *fw_pkt = 1129 kmemdup(pkt, 1130 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 1131 GFP_ATOMIC); 1132 1133 if (!fw_pkt) 1134 return false; 1135 1136 dump_data->fw_pkt = fw_pkt; 1137 1138 return true; 1139 } 1140 1141 return false; 1142 } 1143 1144 static int 1145 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync, 1146 struct list_head *active_trig_list, 1147 union iwl_dbg_tlv_tp_data *tp_data, 1148 bool (*data_check)(struct iwl_fw_runtime *fwrt, 1149 struct iwl_fwrt_dump_data *dump_data, 1150 union iwl_dbg_tlv_tp_data *tp_data, 1151 u32 trig_data)) 1152 { 1153 struct iwl_dbg_tlv_node *node; 1154 1155 list_for_each_entry(node, active_trig_list, list) { 1156 struct iwl_fwrt_dump_data dump_data = { 1157 .trig = (void *)node->tlv.data, 1158 }; 1159 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 1160 data); 1161 int ret, i; 1162 1163 if (!num_data) { 1164 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1165 if (ret) 1166 return ret; 1167 } 1168 1169 for (i = 0; i < num_data; i++) { 1170 if (!data_check || 1171 data_check(fwrt, &dump_data, tp_data, 1172 le32_to_cpu(dump_data.trig->data[i]))) { 1173 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1174 if (ret) 1175 return ret; 1176 1177 break; 1178 } 1179 } 1180 } 1181 1182 return 0; 1183 } 1184 1185 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1186 { 1187 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1188 int ret, i; 1189 u32 failed_alloc = 0; 1190 1191 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) 1192 return; 1193 1194 IWL_DEBUG_FW(fwrt, 1195 "WRT: Generating active triggers list, domain 0x%x\n", 1196 fwrt->trans->dbg.domains_bitmap); 1197 1198 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1199 struct iwl_dbg_tlv_time_point_data *tp = 1200 &fwrt->trans->dbg.time_point[i]; 1201 1202 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1203 } 1204 1205 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1206 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1207 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1208 &fwrt->trans->dbg.fw_mon_cfg[i]; 1209 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1210 1211 if (dest == IWL_FW_INI_LOCATION_INVALID) { 1212 failed_alloc |= BIT(i); 1213 continue; 1214 } 1215 1216 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1217 *ini_dest = dest; 1218 1219 if (dest != *ini_dest) 1220 continue; 1221 1222 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1223 1224 if (ret) { 1225 IWL_WARN(fwrt, 1226 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1227 i, ret); 1228 failed_alloc |= BIT(i); 1229 } 1230 } 1231 1232 if (!failed_alloc) 1233 return; 1234 1235 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { 1236 struct iwl_fw_ini_region_tlv *reg; 1237 struct iwl_ucode_tlv **active_reg = 1238 &fwrt->trans->dbg.active_regions[i]; 1239 u32 reg_type; 1240 1241 if (!*active_reg) { 1242 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1243 continue; 1244 } 1245 1246 reg = (void *)(*active_reg)->data; 1247 reg_type = le32_to_cpu(reg->type); 1248 1249 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || 1250 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) 1251 continue; 1252 1253 IWL_DEBUG_FW(fwrt, 1254 "WRT: removing allocation id %d from region id %d\n", 1255 le32_to_cpu(reg->dram_alloc_id), i); 1256 1257 failed_alloc &= ~le32_to_cpu(reg->dram_alloc_id); 1258 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1259 1260 kfree(*active_reg); 1261 *active_reg = NULL; 1262 } 1263 } 1264 1265 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1266 enum iwl_fw_ini_time_point tp_id, 1267 union iwl_dbg_tlv_tp_data *tp_data, 1268 bool sync) 1269 { 1270 struct list_head *hcmd_list, *trig_list, *conf_list; 1271 1272 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1273 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1274 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1275 return; 1276 1277 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1278 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1279 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list; 1280 1281 switch (tp_id) { 1282 case IWL_FW_INI_TIME_POINT_EARLY: 1283 iwl_dbg_tlv_init_cfg(fwrt); 1284 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1285 iwl_dbg_tlv_update_drams(fwrt); 1286 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1287 break; 1288 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1289 iwl_dbg_tlv_apply_buffers(fwrt); 1290 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1291 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1292 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1293 break; 1294 case IWL_FW_INI_TIME_POINT_PERIODIC: 1295 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1296 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1297 break; 1298 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1299 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1300 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1301 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1302 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1303 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, 1304 iwl_dbg_tlv_check_fw_pkt); 1305 break; 1306 default: 1307 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1308 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1309 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1310 break; 1311 } 1312 } 1313 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point); 1314