1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright (C) 2018 - 2019 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright (C) 2018 - 2019 Intel Corporation 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 38 * * Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * * Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in 42 * the documentation and/or other materials provided with the 43 * distribution. 44 * * Neither the name Intel Corporation nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 49 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 50 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 51 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 52 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 53 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 54 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 58 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 * 60 *****************************************************************************/ 61 62 #include <linux/firmware.h> 63 #include "iwl-drv.h" 64 #include "iwl-trans.h" 65 #include "iwl-dbg-tlv.h" 66 #include "fw/dbg.h" 67 #include "fw/runtime.h" 68 69 /** 70 * enum iwl_dbg_tlv_type - debug TLV types 71 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 72 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 73 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 74 * @IWL_DBG_TLV_TYPE_REGION: region TLV 75 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 76 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 77 */ 78 enum iwl_dbg_tlv_type { 79 IWL_DBG_TLV_TYPE_DEBUG_INFO = 80 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 81 IWL_DBG_TLV_TYPE_BUF_ALLOC, 82 IWL_DBG_TLV_TYPE_HCMD, 83 IWL_DBG_TLV_TYPE_REGION, 84 IWL_DBG_TLV_TYPE_TRIGGER, 85 IWL_DBG_TLV_TYPE_NUM, 86 }; 87 88 /** 89 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 90 * @min_ver: min version supported 91 * @max_ver: max version supported 92 */ 93 struct iwl_dbg_tlv_ver_data { 94 int min_ver; 95 int max_ver; 96 }; 97 98 /** 99 * struct iwl_dbg_tlv_timer_node - timer node struct 100 * @list: list of &struct iwl_dbg_tlv_timer_node 101 * @timer: timer 102 * @fwrt: &struct iwl_fw_runtime 103 * @tlv: TLV attach to the timer node 104 */ 105 struct iwl_dbg_tlv_timer_node { 106 struct list_head list; 107 struct timer_list timer; 108 struct iwl_fw_runtime *fwrt; 109 struct iwl_ucode_tlv *tlv; 110 }; 111 112 static const struct iwl_dbg_tlv_ver_data 113 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 114 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 115 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 116 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 117 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,}, 118 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 119 }; 120 121 static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list) 122 { 123 u32 len = le32_to_cpu(tlv->length); 124 struct iwl_dbg_tlv_node *node; 125 126 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 127 if (!node) 128 return -ENOMEM; 129 130 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len); 131 list_add_tail(&node->list, list); 132 133 return 0; 134 } 135 136 static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv) 137 { 138 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 139 u32 type = le32_to_cpu(tlv->type); 140 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 141 u32 ver = le32_to_cpu(hdr->version); 142 143 if (ver < dbg_ver_table[tlv_idx].min_ver || 144 ver > dbg_ver_table[tlv_idx].max_ver) 145 return false; 146 147 return true; 148 } 149 150 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 151 struct iwl_ucode_tlv *tlv) 152 { 153 struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data; 154 155 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 156 return -EINVAL; 157 158 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 159 debug_info->debug_cfg_name); 160 161 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 162 } 163 164 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 165 struct iwl_ucode_tlv *tlv) 166 { 167 struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data; 168 u32 buf_location = le32_to_cpu(alloc->buf_location); 169 u32 alloc_id = le32_to_cpu(alloc->alloc_id); 170 171 if (le32_to_cpu(tlv->length) != sizeof(*alloc) || 172 (buf_location != IWL_FW_INI_LOCATION_SRAM_PATH && 173 buf_location != IWL_FW_INI_LOCATION_DRAM_PATH)) 174 return -EINVAL; 175 176 if ((buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 177 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) || 178 (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH && 179 (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 180 alloc_id >= IWL_FW_INI_ALLOCATION_NUM))) { 181 IWL_ERR(trans, 182 "WRT: Invalid allocation id %u for allocation TLV\n", 183 alloc_id); 184 return -EINVAL; 185 } 186 187 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 188 189 return 0; 190 } 191 192 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 193 struct iwl_ucode_tlv *tlv) 194 { 195 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data; 196 u32 tp = le32_to_cpu(hcmd->time_point); 197 198 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 199 return -EINVAL; 200 201 /* Host commands can not be sent in early time point since the FW 202 * is not ready 203 */ 204 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 205 tp >= IWL_FW_INI_TIME_POINT_NUM || 206 tp == IWL_FW_INI_TIME_POINT_EARLY) { 207 IWL_ERR(trans, 208 "WRT: Invalid time point %u for host command TLV\n", 209 tp); 210 return -EINVAL; 211 } 212 213 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 214 } 215 216 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 217 struct iwl_ucode_tlv *tlv) 218 { 219 struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data; 220 struct iwl_ucode_tlv **active_reg; 221 u32 id = le32_to_cpu(reg->id); 222 u32 type = le32_to_cpu(reg->type); 223 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 224 225 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 226 return -EINVAL; 227 228 if (id >= IWL_FW_INI_MAX_REGION_ID) { 229 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 230 return -EINVAL; 231 } 232 233 if (type <= IWL_FW_INI_REGION_INVALID || 234 type >= IWL_FW_INI_REGION_NUM) { 235 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 236 return -EINVAL; 237 } 238 239 active_reg = &trans->dbg.active_regions[id]; 240 if (*active_reg) { 241 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 242 243 kfree(*active_reg); 244 } 245 246 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 247 if (!*active_reg) 248 return -ENOMEM; 249 250 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 251 252 return 0; 253 } 254 255 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 256 struct iwl_ucode_tlv *tlv) 257 { 258 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data; 259 u32 tp = le32_to_cpu(trig->time_point); 260 261 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 262 return -EINVAL; 263 264 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 265 tp >= IWL_FW_INI_TIME_POINT_NUM) { 266 IWL_ERR(trans, 267 "WRT: Invalid time point %u for trigger TLV\n", 268 tp); 269 return -EINVAL; 270 } 271 272 if (!le32_to_cpu(trig->occurrences)) 273 trig->occurrences = cpu_to_le32(-1); 274 275 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 276 } 277 278 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 279 struct iwl_ucode_tlv *tlv) = { 280 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 281 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 282 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 283 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 284 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 285 }; 286 287 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv, 288 bool ext) 289 { 290 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 291 u32 type = le32_to_cpu(tlv->type); 292 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 293 enum iwl_ini_cfg_state *cfg_state = ext ? 294 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 295 int ret; 296 297 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 298 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 299 goto out_err; 300 } 301 302 if (!iwl_dbg_tlv_ver_support(tlv)) { 303 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 304 le32_to_cpu(hdr->version)); 305 goto out_err; 306 } 307 308 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 309 if (ret) { 310 IWL_ERR(trans, 311 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 312 type, ret, ext); 313 goto out_err; 314 } 315 316 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 317 *cfg_state = IWL_INI_CFG_STATE_LOADED; 318 319 return; 320 321 out_err: 322 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 323 } 324 325 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 326 { 327 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 328 struct iwl_dbg_tlv_timer_node *node, *tmp; 329 330 list_for_each_entry_safe(node, tmp, timer_list, list) { 331 del_timer(&node->timer); 332 list_del(&node->list); 333 kfree(node); 334 } 335 } 336 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 337 338 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 339 enum iwl_fw_ini_allocation_id alloc_id) 340 { 341 struct iwl_fw_mon *fw_mon; 342 int i; 343 344 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 345 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 346 return; 347 348 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 349 350 for (i = 0; i < fw_mon->num_frags; i++) { 351 struct iwl_dram_data *frag = &fw_mon->frags[i]; 352 353 dma_free_coherent(trans->dev, frag->size, frag->block, 354 frag->physical); 355 356 frag->physical = 0; 357 frag->block = NULL; 358 frag->size = 0; 359 } 360 361 kfree(fw_mon->frags); 362 fw_mon->frags = NULL; 363 fw_mon->num_frags = 0; 364 } 365 366 void iwl_dbg_tlv_free(struct iwl_trans *trans) 367 { 368 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 369 int i; 370 371 iwl_dbg_tlv_del_timers(trans); 372 373 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 374 struct iwl_ucode_tlv **active_reg = 375 &trans->dbg.active_regions[i]; 376 377 kfree(*active_reg); 378 *active_reg = NULL; 379 } 380 381 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 382 &trans->dbg.debug_info_tlv_list, list) { 383 list_del(&tlv_node->list); 384 kfree(tlv_node); 385 } 386 387 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 388 struct iwl_dbg_tlv_time_point_data *tp = 389 &trans->dbg.time_point[i]; 390 391 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 392 list) { 393 list_del(&tlv_node->list); 394 kfree(tlv_node); 395 } 396 397 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 398 list) { 399 list_del(&tlv_node->list); 400 kfree(tlv_node); 401 } 402 403 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 404 &tp->active_trig_list, list) { 405 list_del(&tlv_node->list); 406 kfree(tlv_node); 407 } 408 } 409 410 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 411 iwl_dbg_tlv_fragments_free(trans, i); 412 } 413 414 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 415 size_t len) 416 { 417 struct iwl_ucode_tlv *tlv; 418 u32 tlv_len; 419 420 while (len >= sizeof(*tlv)) { 421 len -= sizeof(*tlv); 422 tlv = (void *)data; 423 424 tlv_len = le32_to_cpu(tlv->length); 425 426 if (len < tlv_len) { 427 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 428 len, tlv_len); 429 return -EINVAL; 430 } 431 len -= ALIGN(tlv_len, 4); 432 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 433 434 iwl_dbg_tlv_alloc(trans, tlv, true); 435 } 436 437 return 0; 438 } 439 440 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 441 { 442 const struct firmware *fw; 443 int res; 444 445 if (!iwlwifi_mod_params.enable_ini) 446 return; 447 448 res = request_firmware(&fw, "iwl-debug-yoyo.bin", dev); 449 if (res) 450 return; 451 452 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 453 454 release_firmware(fw); 455 } 456 457 void iwl_dbg_tlv_init(struct iwl_trans *trans) 458 { 459 int i; 460 461 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 462 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 463 464 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 465 struct iwl_dbg_tlv_time_point_data *tp = 466 &trans->dbg.time_point[i]; 467 468 INIT_LIST_HEAD(&tp->trig_list); 469 INIT_LIST_HEAD(&tp->hcmd_list); 470 INIT_LIST_HEAD(&tp->active_trig_list); 471 } 472 } 473 474 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 475 struct iwl_dram_data *frag, u32 pages) 476 { 477 void *block = NULL; 478 dma_addr_t physical; 479 480 if (!frag || frag->size || !pages) 481 return -EIO; 482 483 /* 484 * We try to allocate as many pages as we can, starting with 485 * the requested amount and going down until we can allocate 486 * something. Because of DIV_ROUND_UP(), pages will never go 487 * down to 0 and stop the loop, so stop when pages reaches 1, 488 * which is too small anyway. 489 */ 490 while (pages > 1) { 491 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 492 &physical, 493 GFP_KERNEL | __GFP_NOWARN); 494 if (block) 495 break; 496 497 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 498 pages * PAGE_SIZE); 499 500 pages = DIV_ROUND_UP(pages, 2); 501 } 502 503 if (!block) 504 return -ENOMEM; 505 506 frag->physical = physical; 507 frag->block = block; 508 frag->size = pages * PAGE_SIZE; 509 510 return pages; 511 } 512 513 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 514 enum iwl_fw_ini_allocation_id alloc_id) 515 { 516 struct iwl_fw_mon *fw_mon; 517 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 518 u32 num_frags, remain_pages, frag_pages; 519 int i; 520 521 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 522 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 523 return -EIO; 524 525 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 526 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 527 528 if (fw_mon->num_frags || 529 fw_mon_cfg->buf_location != 530 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 531 return 0; 532 533 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 534 if (!fw_has_capa(&fwrt->fw->ucode_capa, 535 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) { 536 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 537 return -EIO; 538 num_frags = 1; 539 } 540 541 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 542 PAGE_SIZE); 543 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 544 num_frags = min_t(u32, num_frags, remain_pages); 545 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 546 547 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 548 if (!fw_mon->frags) 549 return -ENOMEM; 550 551 for (i = 0; i < num_frags; i++) { 552 int pages = min_t(u32, frag_pages, remain_pages); 553 554 IWL_DEBUG_FW(fwrt, 555 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 556 alloc_id, i, pages * PAGE_SIZE); 557 558 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 559 pages); 560 if (pages < 0) { 561 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 562 (remain_pages * PAGE_SIZE); 563 564 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 565 iwl_dbg_tlv_fragments_free(fwrt->trans, 566 alloc_id); 567 return pages; 568 } 569 break; 570 } 571 572 remain_pages -= pages; 573 fw_mon->num_frags++; 574 } 575 576 return 0; 577 } 578 579 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 580 enum iwl_fw_ini_allocation_id alloc_id) 581 { 582 struct iwl_fw_mon *fw_mon; 583 u32 remain_frags, num_commands; 584 int i, fw_mon_idx = 0; 585 586 if (!fw_has_capa(&fwrt->fw->ucode_capa, 587 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 588 return 0; 589 590 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 591 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 592 return -EIO; 593 594 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 595 IWL_FW_INI_LOCATION_DRAM_PATH) 596 return 0; 597 598 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 599 600 /* the first fragment of DBGC1 is given to the FW via register 601 * or context info 602 */ 603 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 604 fw_mon_idx++; 605 606 remain_frags = fw_mon->num_frags - fw_mon_idx; 607 if (!remain_frags) 608 return 0; 609 610 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 611 612 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 613 alloc_id); 614 615 for (i = 0; i < num_commands; i++) { 616 u32 num_frags = min_t(u32, remain_frags, 617 BUF_ALLOC_MAX_NUM_FRAGS); 618 struct iwl_buf_alloc_cmd data = { 619 .alloc_id = cpu_to_le32(alloc_id), 620 .num_frags = cpu_to_le32(num_frags), 621 .buf_location = 622 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 623 }; 624 struct iwl_host_cmd hcmd = { 625 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 626 .data[0] = &data, 627 .len[0] = sizeof(data), 628 }; 629 int ret, j; 630 631 for (j = 0; j < num_frags; j++) { 632 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 633 struct iwl_dram_data *fw_mon_frag = 634 &fw_mon->frags[fw_mon_idx++]; 635 636 frag->addr = cpu_to_le64(fw_mon_frag->physical); 637 frag->size = cpu_to_le32(fw_mon_frag->size); 638 } 639 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 640 if (ret) 641 return ret; 642 643 remain_frags -= num_frags; 644 } 645 646 return 0; 647 } 648 649 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 650 { 651 int ret, i; 652 653 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 654 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 655 if (ret) 656 IWL_WARN(fwrt, 657 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 658 i, ret); 659 } 660 } 661 662 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 663 struct list_head *hcmd_list) 664 { 665 struct iwl_dbg_tlv_node *node; 666 667 list_for_each_entry(node, hcmd_list, list) { 668 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 669 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 670 u32 domain = le32_to_cpu(hcmd->hdr.domain); 671 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 672 struct iwl_host_cmd cmd = { 673 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 674 .len = { hcmd_len, }, 675 .data = { hcmd_data->data, }, 676 }; 677 678 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 679 !(domain & fwrt->trans->dbg.domains_bitmap)) 680 continue; 681 682 iwl_trans_send_cmd(fwrt->trans, &cmd); 683 } 684 } 685 686 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 687 { 688 struct iwl_dbg_tlv_timer_node *timer_node = 689 from_timer(timer_node, t, timer); 690 struct iwl_fwrt_dump_data dump_data = { 691 .trig = (void *)timer_node->tlv->data, 692 }; 693 int ret; 694 695 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data); 696 if (!ret || ret == -EBUSY) { 697 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 698 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 699 700 if (!occur) 701 return; 702 703 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 704 } 705 } 706 707 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 708 { 709 struct iwl_dbg_tlv_node *node; 710 struct list_head *trig_list = 711 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 712 713 list_for_each_entry(node, trig_list, list) { 714 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 715 struct iwl_dbg_tlv_timer_node *timer_node; 716 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 717 u32 min_interval = 100; 718 719 if (!occur) 720 continue; 721 722 /* make sure there is at least one dword of data for the 723 * interval value 724 */ 725 if (le32_to_cpu(node->tlv.length) < 726 sizeof(*trig) + sizeof(__le32)) { 727 IWL_ERR(fwrt, 728 "WRT: Invalid periodic trigger data was not given\n"); 729 continue; 730 } 731 732 if (le32_to_cpu(trig->data[0]) < min_interval) { 733 IWL_WARN(fwrt, 734 "WRT: Override min interval from %u to %u msec\n", 735 le32_to_cpu(trig->data[0]), min_interval); 736 trig->data[0] = cpu_to_le32(min_interval); 737 } 738 739 collect_interval = le32_to_cpu(trig->data[0]); 740 741 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 742 if (!timer_node) { 743 IWL_ERR(fwrt, 744 "WRT: Failed to allocate periodic trigger\n"); 745 continue; 746 } 747 748 timer_node->fwrt = fwrt; 749 timer_node->tlv = &node->tlv; 750 timer_setup(&timer_node->timer, 751 iwl_dbg_tlv_periodic_trig_handler, 0); 752 753 list_add_tail(&timer_node->list, 754 &fwrt->trans->dbg.periodic_trig_list); 755 756 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 757 758 mod_timer(&timer_node->timer, 759 jiffies + msecs_to_jiffies(collect_interval)); 760 } 761 } 762 763 static bool is_trig_data_contained(struct iwl_ucode_tlv *new, 764 struct iwl_ucode_tlv *old) 765 { 766 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data; 767 struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data; 768 __le32 *new_data = new_trig->data, *old_data = old_trig->data; 769 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 770 u32 old_dwords_num = iwl_tlv_array_len(new, new_trig, data); 771 int i, j; 772 773 for (i = 0; i < new_dwords_num; i++) { 774 bool match = false; 775 776 for (j = 0; j < old_dwords_num; j++) { 777 if (new_data[i] == old_data[j]) { 778 match = true; 779 break; 780 } 781 } 782 if (!match) 783 return false; 784 } 785 786 return true; 787 } 788 789 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 790 struct iwl_ucode_tlv *trig_tlv, 791 struct iwl_dbg_tlv_node *node) 792 { 793 struct iwl_ucode_tlv *node_tlv = &node->tlv; 794 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 795 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 796 u32 policy = le32_to_cpu(trig->apply_policy); 797 u32 size = le32_to_cpu(trig_tlv->length); 798 u32 trig_data_len = size - sizeof(*trig); 799 u32 offset = 0; 800 801 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 802 u32 data_len = le32_to_cpu(node_tlv->length) - 803 sizeof(*node_trig); 804 805 IWL_DEBUG_FW(fwrt, 806 "WRT: Appending trigger data (time point %u)\n", 807 le32_to_cpu(trig->time_point)); 808 809 offset += data_len; 810 size += data_len; 811 } else { 812 IWL_DEBUG_FW(fwrt, 813 "WRT: Overriding trigger data (time point %u)\n", 814 le32_to_cpu(trig->time_point)); 815 } 816 817 if (size != le32_to_cpu(node_tlv->length)) { 818 struct list_head *prev = node->list.prev; 819 struct iwl_dbg_tlv_node *tmp; 820 821 list_del(&node->list); 822 823 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 824 if (!tmp) { 825 IWL_WARN(fwrt, 826 "WRT: No memory to override trigger (time point %u)\n", 827 le32_to_cpu(trig->time_point)); 828 829 list_add(&node->list, prev); 830 831 return -ENOMEM; 832 } 833 834 list_add(&tmp->list, prev); 835 node_tlv = &tmp->tlv; 836 node_trig = (void *)node_tlv->data; 837 } 838 839 memcpy(node_trig->data + offset, trig->data, trig_data_len); 840 node_tlv->length = cpu_to_le32(size); 841 842 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 843 IWL_DEBUG_FW(fwrt, 844 "WRT: Overriding trigger configuration (time point %u)\n", 845 le32_to_cpu(trig->time_point)); 846 847 /* the first 11 dwords are configuration related */ 848 memcpy(node_trig, trig, sizeof(__le32) * 11); 849 } 850 851 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 852 IWL_DEBUG_FW(fwrt, 853 "WRT: Overriding trigger regions (time point %u)\n", 854 le32_to_cpu(trig->time_point)); 855 856 node_trig->regions_mask = trig->regions_mask; 857 } else { 858 IWL_DEBUG_FW(fwrt, 859 "WRT: Appending trigger regions (time point %u)\n", 860 le32_to_cpu(trig->time_point)); 861 862 node_trig->regions_mask |= trig->regions_mask; 863 } 864 865 return 0; 866 } 867 868 static int 869 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 870 struct list_head *trig_list, 871 struct iwl_ucode_tlv *trig_tlv) 872 { 873 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 874 struct iwl_dbg_tlv_node *node, *match = NULL; 875 u32 policy = le32_to_cpu(trig->apply_policy); 876 877 list_for_each_entry(node, trig_list, list) { 878 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 879 break; 880 881 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 882 is_trig_data_contained(trig_tlv, &node->tlv)) { 883 match = node; 884 break; 885 } 886 } 887 888 if (!match) { 889 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 890 le32_to_cpu(trig->time_point)); 891 return iwl_dbg_tlv_add(trig_tlv, trig_list); 892 } 893 894 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 895 } 896 897 static void 898 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 899 struct iwl_dbg_tlv_time_point_data *tp) 900 { 901 struct iwl_dbg_tlv_node *node, *tmp; 902 struct list_head *trig_list = &tp->trig_list; 903 struct list_head *active_trig_list = &tp->active_trig_list; 904 905 list_for_each_entry_safe(node, tmp, active_trig_list, list) { 906 list_del(&node->list); 907 kfree(node); 908 } 909 910 list_for_each_entry(node, trig_list, list) { 911 struct iwl_ucode_tlv *tlv = &node->tlv; 912 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data; 913 u32 domain = le32_to_cpu(trig->hdr.domain); 914 915 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 916 !(domain & fwrt->trans->dbg.domains_bitmap)) 917 continue; 918 919 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 920 } 921 } 922 923 int iwl_dbg_tlv_gen_active_trigs(struct iwl_fw_runtime *fwrt, u32 new_domain) 924 { 925 int i; 926 927 if (test_and_set_bit(STATUS_GEN_ACTIVE_TRIGS, &fwrt->status)) 928 return -EBUSY; 929 930 iwl_fw_flush_dumps(fwrt); 931 932 fwrt->trans->dbg.domains_bitmap = new_domain; 933 934 IWL_DEBUG_FW(fwrt, 935 "WRT: Generating active triggers list, domain 0x%x\n", 936 fwrt->trans->dbg.domains_bitmap); 937 938 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 939 struct iwl_dbg_tlv_time_point_data *tp = 940 &fwrt->trans->dbg.time_point[i]; 941 942 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 943 } 944 945 clear_bit(STATUS_GEN_ACTIVE_TRIGS, &fwrt->status); 946 947 return 0; 948 } 949 950 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 951 struct iwl_fwrt_dump_data *dump_data, 952 union iwl_dbg_tlv_tp_data *tp_data, 953 u32 trig_data) 954 { 955 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 956 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 957 958 if (pkt && ((wanted_hdr->cmd == 0 && wanted_hdr->group_id == 0) || 959 (pkt->hdr.cmd == wanted_hdr->cmd && 960 pkt->hdr.group_id == wanted_hdr->group_id))) { 961 struct iwl_rx_packet *fw_pkt = 962 kmemdup(pkt, 963 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 964 GFP_ATOMIC); 965 966 if (!fw_pkt) 967 return false; 968 969 dump_data->fw_pkt = fw_pkt; 970 971 return true; 972 } 973 974 return false; 975 } 976 977 static int 978 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, 979 struct list_head *active_trig_list, 980 union iwl_dbg_tlv_tp_data *tp_data, 981 bool (*data_check)(struct iwl_fw_runtime *fwrt, 982 struct iwl_fwrt_dump_data *dump_data, 983 union iwl_dbg_tlv_tp_data *tp_data, 984 u32 trig_data)) 985 { 986 struct iwl_dbg_tlv_node *node; 987 988 list_for_each_entry(node, active_trig_list, list) { 989 struct iwl_fwrt_dump_data dump_data = { 990 .trig = (void *)node->tlv.data, 991 }; 992 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 993 data); 994 int ret, i; 995 996 if (!num_data) { 997 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 998 if (ret) 999 return ret; 1000 } 1001 1002 for (i = 0; i < num_data; i++) { 1003 if (!data_check || 1004 data_check(fwrt, &dump_data, tp_data, 1005 le32_to_cpu(dump_data.trig->data[i]))) { 1006 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 1007 if (ret) 1008 return ret; 1009 1010 break; 1011 } 1012 } 1013 } 1014 1015 return 0; 1016 } 1017 1018 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1019 { 1020 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1021 int ret, i; 1022 1023 iwl_dbg_tlv_gen_active_trigs(fwrt, IWL_FW_DBG_DOMAIN); 1024 1025 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1026 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1027 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1028 &fwrt->trans->dbg.fw_mon_cfg[i]; 1029 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1030 1031 if (dest == IWL_FW_INI_LOCATION_INVALID) 1032 continue; 1033 1034 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1035 *ini_dest = dest; 1036 1037 if (dest != *ini_dest) 1038 continue; 1039 1040 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1041 if (ret) 1042 IWL_WARN(fwrt, 1043 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1044 i, ret); 1045 } 1046 } 1047 1048 void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1049 enum iwl_fw_ini_time_point tp_id, 1050 union iwl_dbg_tlv_tp_data *tp_data) 1051 { 1052 struct list_head *hcmd_list, *trig_list; 1053 1054 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1055 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1056 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1057 return; 1058 1059 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1060 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1061 1062 switch (tp_id) { 1063 case IWL_FW_INI_TIME_POINT_EARLY: 1064 iwl_dbg_tlv_init_cfg(fwrt); 1065 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1066 break; 1067 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1068 iwl_dbg_tlv_apply_buffers(fwrt); 1069 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1070 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1071 break; 1072 case IWL_FW_INI_TIME_POINT_PERIODIC: 1073 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1074 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1075 break; 1076 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1077 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1078 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1079 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, 1080 iwl_dbg_tlv_check_fw_pkt); 1081 break; 1082 default: 1083 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1084 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1085 break; 1086 } 1087 } 1088 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point); 1089