1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2020 Intel Corporation 4 */ 5 #include <linux/firmware.h> 6 #include "iwl-drv.h" 7 #include "iwl-trans.h" 8 #include "iwl-dbg-tlv.h" 9 #include "fw/dbg.h" 10 #include "fw/runtime.h" 11 12 /** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 20 */ 21 enum iwl_dbg_tlv_type { 22 IWL_DBG_TLV_TYPE_DEBUG_INFO = 23 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 24 IWL_DBG_TLV_TYPE_BUF_ALLOC, 25 IWL_DBG_TLV_TYPE_HCMD, 26 IWL_DBG_TLV_TYPE_REGION, 27 IWL_DBG_TLV_TYPE_TRIGGER, 28 IWL_DBG_TLV_TYPE_NUM, 29 }; 30 31 /** 32 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 33 * @min_ver: min version supported 34 * @max_ver: max version supported 35 */ 36 struct iwl_dbg_tlv_ver_data { 37 int min_ver; 38 int max_ver; 39 }; 40 41 /** 42 * struct iwl_dbg_tlv_timer_node - timer node struct 43 * @list: list of &struct iwl_dbg_tlv_timer_node 44 * @timer: timer 45 * @fwrt: &struct iwl_fw_runtime 46 * @tlv: TLV attach to the timer node 47 */ 48 struct iwl_dbg_tlv_timer_node { 49 struct list_head list; 50 struct timer_list timer; 51 struct iwl_fw_runtime *fwrt; 52 struct iwl_ucode_tlv *tlv; 53 }; 54 55 static const struct iwl_dbg_tlv_ver_data 56 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 57 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 58 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 59 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 62 }; 63 64 static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list) 65 { 66 u32 len = le32_to_cpu(tlv->length); 67 struct iwl_dbg_tlv_node *node; 68 69 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 70 if (!node) 71 return -ENOMEM; 72 73 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len); 74 list_add_tail(&node->list, list); 75 76 return 0; 77 } 78 79 static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv) 80 { 81 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 82 u32 type = le32_to_cpu(tlv->type); 83 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 84 u32 ver = le32_to_cpu(hdr->version); 85 86 if (ver < dbg_ver_table[tlv_idx].min_ver || 87 ver > dbg_ver_table[tlv_idx].max_ver) 88 return false; 89 90 return true; 91 } 92 93 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 94 struct iwl_ucode_tlv *tlv) 95 { 96 struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data; 97 98 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 99 return -EINVAL; 100 101 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 102 debug_info->debug_cfg_name); 103 104 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 105 } 106 107 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 108 struct iwl_ucode_tlv *tlv) 109 { 110 struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data; 111 u32 buf_location; 112 u32 alloc_id; 113 114 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 115 return -EINVAL; 116 117 buf_location = le32_to_cpu(alloc->buf_location); 118 alloc_id = le32_to_cpu(alloc->alloc_id); 119 120 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 121 buf_location >= IWL_FW_INI_LOCATION_NUM) 122 goto err; 123 124 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 125 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 126 goto err; 127 128 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 129 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 130 goto err; 131 132 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 133 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1 && 134 alloc_id != IWL_FW_INI_ALLOCATION_ID_INTERNAL) 135 goto err; 136 137 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 138 139 return 0; 140 err: 141 IWL_ERR(trans, 142 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 143 alloc_id, buf_location); 144 return -EINVAL; 145 } 146 147 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 148 struct iwl_ucode_tlv *tlv) 149 { 150 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data; 151 u32 tp = le32_to_cpu(hcmd->time_point); 152 153 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 154 return -EINVAL; 155 156 /* Host commands can not be sent in early time point since the FW 157 * is not ready 158 */ 159 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 160 tp >= IWL_FW_INI_TIME_POINT_NUM || 161 tp == IWL_FW_INI_TIME_POINT_EARLY) { 162 IWL_ERR(trans, 163 "WRT: Invalid time point %u for host command TLV\n", 164 tp); 165 return -EINVAL; 166 } 167 168 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 169 } 170 171 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 172 struct iwl_ucode_tlv *tlv) 173 { 174 struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data; 175 struct iwl_ucode_tlv **active_reg; 176 u32 id = le32_to_cpu(reg->id); 177 u32 type = le32_to_cpu(reg->type); 178 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 179 180 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 181 return -EINVAL; 182 183 if (id >= IWL_FW_INI_MAX_REGION_ID) { 184 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 185 return -EINVAL; 186 } 187 188 if (type <= IWL_FW_INI_REGION_INVALID || 189 type >= IWL_FW_INI_REGION_NUM) { 190 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 191 return -EINVAL; 192 } 193 194 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 195 !trans->ops->read_config32) { 196 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 197 return -EOPNOTSUPP; 198 } 199 200 active_reg = &trans->dbg.active_regions[id]; 201 if (*active_reg) { 202 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 203 204 kfree(*active_reg); 205 } 206 207 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 208 if (!*active_reg) 209 return -ENOMEM; 210 211 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 212 213 return 0; 214 } 215 216 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 217 struct iwl_ucode_tlv *tlv) 218 { 219 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data; 220 u32 tp = le32_to_cpu(trig->time_point); 221 struct iwl_ucode_tlv *dup = NULL; 222 int ret; 223 224 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 225 return -EINVAL; 226 227 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 228 tp >= IWL_FW_INI_TIME_POINT_NUM) { 229 IWL_ERR(trans, 230 "WRT: Invalid time point %u for trigger TLV\n", 231 tp); 232 return -EINVAL; 233 } 234 235 if (!le32_to_cpu(trig->occurrences)) { 236 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 237 GFP_KERNEL); 238 if (!dup) 239 return -ENOMEM; 240 trig = (void *)dup->data; 241 trig->occurrences = cpu_to_le32(-1); 242 tlv = dup; 243 } 244 245 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 246 kfree(dup); 247 248 return ret; 249 } 250 251 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 252 struct iwl_ucode_tlv *tlv) = { 253 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 254 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 255 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 256 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 257 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 258 }; 259 260 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv, 261 bool ext) 262 { 263 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 264 u32 type = le32_to_cpu(tlv->type); 265 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 266 u32 domain = le32_to_cpu(hdr->domain); 267 enum iwl_ini_cfg_state *cfg_state = ext ? 268 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 269 int ret; 270 271 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 272 !(domain & trans->dbg.domains_bitmap)) { 273 IWL_DEBUG_FW(trans, 274 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 275 domain, trans->dbg.domains_bitmap); 276 return; 277 } 278 279 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 280 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 281 goto out_err; 282 } 283 284 if (!iwl_dbg_tlv_ver_support(tlv)) { 285 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 286 le32_to_cpu(hdr->version)); 287 goto out_err; 288 } 289 290 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 291 if (ret) { 292 IWL_ERR(trans, 293 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 294 type, ret, ext); 295 goto out_err; 296 } 297 298 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 299 *cfg_state = IWL_INI_CFG_STATE_LOADED; 300 301 return; 302 303 out_err: 304 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 305 } 306 307 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 308 { 309 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 310 struct iwl_dbg_tlv_timer_node *node, *tmp; 311 312 list_for_each_entry_safe(node, tmp, timer_list, list) { 313 del_timer(&node->timer); 314 list_del(&node->list); 315 kfree(node); 316 } 317 } 318 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 319 320 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 321 enum iwl_fw_ini_allocation_id alloc_id) 322 { 323 struct iwl_fw_mon *fw_mon; 324 int i; 325 326 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 327 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 328 return; 329 330 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 331 332 for (i = 0; i < fw_mon->num_frags; i++) { 333 struct iwl_dram_data *frag = &fw_mon->frags[i]; 334 335 dma_free_coherent(trans->dev, frag->size, frag->block, 336 frag->physical); 337 338 frag->physical = 0; 339 frag->block = NULL; 340 frag->size = 0; 341 } 342 343 kfree(fw_mon->frags); 344 fw_mon->frags = NULL; 345 fw_mon->num_frags = 0; 346 } 347 348 void iwl_dbg_tlv_free(struct iwl_trans *trans) 349 { 350 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 351 int i; 352 353 iwl_dbg_tlv_del_timers(trans); 354 355 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 356 struct iwl_ucode_tlv **active_reg = 357 &trans->dbg.active_regions[i]; 358 359 kfree(*active_reg); 360 *active_reg = NULL; 361 } 362 363 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 364 &trans->dbg.debug_info_tlv_list, list) { 365 list_del(&tlv_node->list); 366 kfree(tlv_node); 367 } 368 369 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 370 struct iwl_dbg_tlv_time_point_data *tp = 371 &trans->dbg.time_point[i]; 372 373 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 374 list) { 375 list_del(&tlv_node->list); 376 kfree(tlv_node); 377 } 378 379 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 380 list) { 381 list_del(&tlv_node->list); 382 kfree(tlv_node); 383 } 384 385 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 386 &tp->active_trig_list, list) { 387 list_del(&tlv_node->list); 388 kfree(tlv_node); 389 } 390 } 391 392 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 393 iwl_dbg_tlv_fragments_free(trans, i); 394 } 395 396 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 397 size_t len) 398 { 399 struct iwl_ucode_tlv *tlv; 400 u32 tlv_len; 401 402 while (len >= sizeof(*tlv)) { 403 len -= sizeof(*tlv); 404 tlv = (void *)data; 405 406 tlv_len = le32_to_cpu(tlv->length); 407 408 if (len < tlv_len) { 409 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 410 len, tlv_len); 411 return -EINVAL; 412 } 413 len -= ALIGN(tlv_len, 4); 414 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 415 416 iwl_dbg_tlv_alloc(trans, tlv, true); 417 } 418 419 return 0; 420 } 421 422 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 423 { 424 const struct firmware *fw; 425 int res; 426 427 if (!iwlwifi_mod_params.enable_ini) 428 return; 429 430 res = firmware_request_nowarn(&fw, "iwl-debug-yoyo.bin", dev); 431 if (res) 432 return; 433 434 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 435 436 release_firmware(fw); 437 } 438 439 void iwl_dbg_tlv_init(struct iwl_trans *trans) 440 { 441 int i; 442 443 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 444 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 445 446 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 447 struct iwl_dbg_tlv_time_point_data *tp = 448 &trans->dbg.time_point[i]; 449 450 INIT_LIST_HEAD(&tp->trig_list); 451 INIT_LIST_HEAD(&tp->hcmd_list); 452 INIT_LIST_HEAD(&tp->active_trig_list); 453 } 454 } 455 456 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 457 struct iwl_dram_data *frag, u32 pages) 458 { 459 void *block = NULL; 460 dma_addr_t physical; 461 462 if (!frag || frag->size || !pages) 463 return -EIO; 464 465 /* 466 * We try to allocate as many pages as we can, starting with 467 * the requested amount and going down until we can allocate 468 * something. Because of DIV_ROUND_UP(), pages will never go 469 * down to 0 and stop the loop, so stop when pages reaches 1, 470 * which is too small anyway. 471 */ 472 while (pages > 1) { 473 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 474 &physical, 475 GFP_KERNEL | __GFP_NOWARN); 476 if (block) 477 break; 478 479 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 480 pages * PAGE_SIZE); 481 482 pages = DIV_ROUND_UP(pages, 2); 483 } 484 485 if (!block) 486 return -ENOMEM; 487 488 frag->physical = physical; 489 frag->block = block; 490 frag->size = pages * PAGE_SIZE; 491 492 return pages; 493 } 494 495 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 496 enum iwl_fw_ini_allocation_id alloc_id) 497 { 498 struct iwl_fw_mon *fw_mon; 499 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 500 u32 num_frags, remain_pages, frag_pages; 501 int i; 502 503 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 504 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 505 return -EIO; 506 507 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 508 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 509 510 if (fw_mon->num_frags || 511 fw_mon_cfg->buf_location != 512 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 513 return 0; 514 515 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 516 if (!fw_has_capa(&fwrt->fw->ucode_capa, 517 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) { 518 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 519 return -EIO; 520 num_frags = 1; 521 } 522 523 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 524 PAGE_SIZE); 525 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 526 num_frags = min_t(u32, num_frags, remain_pages); 527 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 528 529 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 530 if (!fw_mon->frags) 531 return -ENOMEM; 532 533 for (i = 0; i < num_frags; i++) { 534 int pages = min_t(u32, frag_pages, remain_pages); 535 536 IWL_DEBUG_FW(fwrt, 537 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 538 alloc_id, i, pages * PAGE_SIZE); 539 540 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 541 pages); 542 if (pages < 0) { 543 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 544 (remain_pages * PAGE_SIZE); 545 546 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 547 iwl_dbg_tlv_fragments_free(fwrt->trans, 548 alloc_id); 549 return pages; 550 } 551 break; 552 } 553 554 remain_pages -= pages; 555 fw_mon->num_frags++; 556 } 557 558 return 0; 559 } 560 561 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 562 enum iwl_fw_ini_allocation_id alloc_id) 563 { 564 struct iwl_fw_mon *fw_mon; 565 u32 remain_frags, num_commands; 566 int i, fw_mon_idx = 0; 567 568 if (!fw_has_capa(&fwrt->fw->ucode_capa, 569 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 570 return 0; 571 572 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 573 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 574 return -EIO; 575 576 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 577 IWL_FW_INI_LOCATION_DRAM_PATH) 578 return 0; 579 580 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 581 582 /* the first fragment of DBGC1 is given to the FW via register 583 * or context info 584 */ 585 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 586 fw_mon_idx++; 587 588 remain_frags = fw_mon->num_frags - fw_mon_idx; 589 if (!remain_frags) 590 return 0; 591 592 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 593 594 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 595 alloc_id); 596 597 for (i = 0; i < num_commands; i++) { 598 u32 num_frags = min_t(u32, remain_frags, 599 BUF_ALLOC_MAX_NUM_FRAGS); 600 struct iwl_buf_alloc_cmd data = { 601 .alloc_id = cpu_to_le32(alloc_id), 602 .num_frags = cpu_to_le32(num_frags), 603 .buf_location = 604 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 605 }; 606 struct iwl_host_cmd hcmd = { 607 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 608 .data[0] = &data, 609 .len[0] = sizeof(data), 610 }; 611 int ret, j; 612 613 for (j = 0; j < num_frags; j++) { 614 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 615 struct iwl_dram_data *fw_mon_frag = 616 &fw_mon->frags[fw_mon_idx++]; 617 618 frag->addr = cpu_to_le64(fw_mon_frag->physical); 619 frag->size = cpu_to_le32(fw_mon_frag->size); 620 } 621 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 622 if (ret) 623 return ret; 624 625 remain_frags -= num_frags; 626 } 627 628 return 0; 629 } 630 631 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 632 { 633 int ret, i; 634 635 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 636 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 637 if (ret) 638 IWL_WARN(fwrt, 639 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 640 i, ret); 641 } 642 } 643 644 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 645 struct list_head *hcmd_list) 646 { 647 struct iwl_dbg_tlv_node *node; 648 649 list_for_each_entry(node, hcmd_list, list) { 650 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 651 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 652 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 653 struct iwl_host_cmd cmd = { 654 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 655 .len = { hcmd_len, }, 656 .data = { hcmd_data->data, }, 657 }; 658 659 iwl_trans_send_cmd(fwrt->trans, &cmd); 660 } 661 } 662 663 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 664 { 665 struct iwl_dbg_tlv_timer_node *timer_node = 666 from_timer(timer_node, t, timer); 667 struct iwl_fwrt_dump_data dump_data = { 668 .trig = (void *)timer_node->tlv->data, 669 }; 670 int ret; 671 672 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data); 673 if (!ret || ret == -EBUSY) { 674 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 675 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 676 677 if (!occur) 678 return; 679 680 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 681 } 682 } 683 684 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 685 { 686 struct iwl_dbg_tlv_node *node; 687 struct list_head *trig_list = 688 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 689 690 list_for_each_entry(node, trig_list, list) { 691 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 692 struct iwl_dbg_tlv_timer_node *timer_node; 693 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 694 u32 min_interval = 100; 695 696 if (!occur) 697 continue; 698 699 /* make sure there is at least one dword of data for the 700 * interval value 701 */ 702 if (le32_to_cpu(node->tlv.length) < 703 sizeof(*trig) + sizeof(__le32)) { 704 IWL_ERR(fwrt, 705 "WRT: Invalid periodic trigger data was not given\n"); 706 continue; 707 } 708 709 if (le32_to_cpu(trig->data[0]) < min_interval) { 710 IWL_WARN(fwrt, 711 "WRT: Override min interval from %u to %u msec\n", 712 le32_to_cpu(trig->data[0]), min_interval); 713 trig->data[0] = cpu_to_le32(min_interval); 714 } 715 716 collect_interval = le32_to_cpu(trig->data[0]); 717 718 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 719 if (!timer_node) { 720 IWL_ERR(fwrt, 721 "WRT: Failed to allocate periodic trigger\n"); 722 continue; 723 } 724 725 timer_node->fwrt = fwrt; 726 timer_node->tlv = &node->tlv; 727 timer_setup(&timer_node->timer, 728 iwl_dbg_tlv_periodic_trig_handler, 0); 729 730 list_add_tail(&timer_node->list, 731 &fwrt->trans->dbg.periodic_trig_list); 732 733 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 734 735 mod_timer(&timer_node->timer, 736 jiffies + msecs_to_jiffies(collect_interval)); 737 } 738 } 739 740 static bool is_trig_data_contained(struct iwl_ucode_tlv *new, 741 struct iwl_ucode_tlv *old) 742 { 743 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data; 744 struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data; 745 __le32 *new_data = new_trig->data, *old_data = old_trig->data; 746 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 747 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 748 int i, j; 749 750 for (i = 0; i < new_dwords_num; i++) { 751 bool match = false; 752 753 for (j = 0; j < old_dwords_num; j++) { 754 if (new_data[i] == old_data[j]) { 755 match = true; 756 break; 757 } 758 } 759 if (!match) 760 return false; 761 } 762 763 return true; 764 } 765 766 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 767 struct iwl_ucode_tlv *trig_tlv, 768 struct iwl_dbg_tlv_node *node) 769 { 770 struct iwl_ucode_tlv *node_tlv = &node->tlv; 771 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 772 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 773 u32 policy = le32_to_cpu(trig->apply_policy); 774 u32 size = le32_to_cpu(trig_tlv->length); 775 u32 trig_data_len = size - sizeof(*trig); 776 u32 offset = 0; 777 778 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 779 u32 data_len = le32_to_cpu(node_tlv->length) - 780 sizeof(*node_trig); 781 782 IWL_DEBUG_FW(fwrt, 783 "WRT: Appending trigger data (time point %u)\n", 784 le32_to_cpu(trig->time_point)); 785 786 offset += data_len; 787 size += data_len; 788 } else { 789 IWL_DEBUG_FW(fwrt, 790 "WRT: Overriding trigger data (time point %u)\n", 791 le32_to_cpu(trig->time_point)); 792 } 793 794 if (size != le32_to_cpu(node_tlv->length)) { 795 struct list_head *prev = node->list.prev; 796 struct iwl_dbg_tlv_node *tmp; 797 798 list_del(&node->list); 799 800 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 801 if (!tmp) { 802 IWL_WARN(fwrt, 803 "WRT: No memory to override trigger (time point %u)\n", 804 le32_to_cpu(trig->time_point)); 805 806 list_add(&node->list, prev); 807 808 return -ENOMEM; 809 } 810 811 list_add(&tmp->list, prev); 812 node_tlv = &tmp->tlv; 813 node_trig = (void *)node_tlv->data; 814 } 815 816 memcpy(node_trig->data + offset, trig->data, trig_data_len); 817 node_tlv->length = cpu_to_le32(size); 818 819 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 820 IWL_DEBUG_FW(fwrt, 821 "WRT: Overriding trigger configuration (time point %u)\n", 822 le32_to_cpu(trig->time_point)); 823 824 /* the first 11 dwords are configuration related */ 825 memcpy(node_trig, trig, sizeof(__le32) * 11); 826 } 827 828 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 829 IWL_DEBUG_FW(fwrt, 830 "WRT: Overriding trigger regions (time point %u)\n", 831 le32_to_cpu(trig->time_point)); 832 833 node_trig->regions_mask = trig->regions_mask; 834 } else { 835 IWL_DEBUG_FW(fwrt, 836 "WRT: Appending trigger regions (time point %u)\n", 837 le32_to_cpu(trig->time_point)); 838 839 node_trig->regions_mask |= trig->regions_mask; 840 } 841 842 return 0; 843 } 844 845 static int 846 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 847 struct list_head *trig_list, 848 struct iwl_ucode_tlv *trig_tlv) 849 { 850 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 851 struct iwl_dbg_tlv_node *node, *match = NULL; 852 u32 policy = le32_to_cpu(trig->apply_policy); 853 854 list_for_each_entry(node, trig_list, list) { 855 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 856 break; 857 858 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 859 is_trig_data_contained(trig_tlv, &node->tlv)) { 860 match = node; 861 break; 862 } 863 } 864 865 if (!match) { 866 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 867 le32_to_cpu(trig->time_point)); 868 return iwl_dbg_tlv_add(trig_tlv, trig_list); 869 } 870 871 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 872 } 873 874 static void 875 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 876 struct iwl_dbg_tlv_time_point_data *tp) 877 { 878 struct iwl_dbg_tlv_node *node; 879 struct list_head *trig_list = &tp->trig_list; 880 struct list_head *active_trig_list = &tp->active_trig_list; 881 882 list_for_each_entry(node, trig_list, list) { 883 struct iwl_ucode_tlv *tlv = &node->tlv; 884 885 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 886 } 887 } 888 889 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 890 struct iwl_fwrt_dump_data *dump_data, 891 union iwl_dbg_tlv_tp_data *tp_data, 892 u32 trig_data) 893 { 894 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 895 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 896 897 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 898 pkt->hdr.group_id == wanted_hdr->group_id)) { 899 struct iwl_rx_packet *fw_pkt = 900 kmemdup(pkt, 901 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 902 GFP_ATOMIC); 903 904 if (!fw_pkt) 905 return false; 906 907 dump_data->fw_pkt = fw_pkt; 908 909 return true; 910 } 911 912 return false; 913 } 914 915 static int 916 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, 917 struct list_head *active_trig_list, 918 union iwl_dbg_tlv_tp_data *tp_data, 919 bool (*data_check)(struct iwl_fw_runtime *fwrt, 920 struct iwl_fwrt_dump_data *dump_data, 921 union iwl_dbg_tlv_tp_data *tp_data, 922 u32 trig_data)) 923 { 924 struct iwl_dbg_tlv_node *node; 925 926 list_for_each_entry(node, active_trig_list, list) { 927 struct iwl_fwrt_dump_data dump_data = { 928 .trig = (void *)node->tlv.data, 929 }; 930 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 931 data); 932 int ret, i; 933 934 if (!num_data) { 935 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 936 if (ret) 937 return ret; 938 } 939 940 for (i = 0; i < num_data; i++) { 941 if (!data_check || 942 data_check(fwrt, &dump_data, tp_data, 943 le32_to_cpu(dump_data.trig->data[i]))) { 944 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 945 if (ret) 946 return ret; 947 948 break; 949 } 950 } 951 } 952 953 return 0; 954 } 955 956 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 957 { 958 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 959 int ret, i; 960 961 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) 962 return; 963 964 IWL_DEBUG_FW(fwrt, 965 "WRT: Generating active triggers list, domain 0x%x\n", 966 fwrt->trans->dbg.domains_bitmap); 967 968 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 969 struct iwl_dbg_tlv_time_point_data *tp = 970 &fwrt->trans->dbg.time_point[i]; 971 972 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 973 } 974 975 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 976 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 977 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 978 &fwrt->trans->dbg.fw_mon_cfg[i]; 979 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 980 981 if (dest == IWL_FW_INI_LOCATION_INVALID) 982 continue; 983 984 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 985 *ini_dest = dest; 986 987 if (dest != *ini_dest) 988 continue; 989 990 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 991 if (ret) 992 IWL_WARN(fwrt, 993 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 994 i, ret); 995 } 996 } 997 998 void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 999 enum iwl_fw_ini_time_point tp_id, 1000 union iwl_dbg_tlv_tp_data *tp_data) 1001 { 1002 struct list_head *hcmd_list, *trig_list; 1003 1004 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1005 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1006 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1007 return; 1008 1009 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1010 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1011 1012 switch (tp_id) { 1013 case IWL_FW_INI_TIME_POINT_EARLY: 1014 iwl_dbg_tlv_init_cfg(fwrt); 1015 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1016 break; 1017 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1018 iwl_dbg_tlv_apply_buffers(fwrt); 1019 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1020 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1021 break; 1022 case IWL_FW_INI_TIME_POINT_PERIODIC: 1023 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1024 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1025 break; 1026 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1027 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1028 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1029 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1030 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, 1031 iwl_dbg_tlv_check_fw_pkt); 1032 break; 1033 default: 1034 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1035 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1036 break; 1037 } 1038 } 1039 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point); 1040