1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2020 Intel Corporation 4 */ 5 #include <linux/firmware.h> 6 #include "iwl-drv.h" 7 #include "iwl-trans.h" 8 #include "iwl-dbg-tlv.h" 9 #include "fw/dbg.h" 10 #include "fw/runtime.h" 11 12 /** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 20 */ 21 enum iwl_dbg_tlv_type { 22 IWL_DBG_TLV_TYPE_DEBUG_INFO = 23 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 24 IWL_DBG_TLV_TYPE_BUF_ALLOC, 25 IWL_DBG_TLV_TYPE_HCMD, 26 IWL_DBG_TLV_TYPE_REGION, 27 IWL_DBG_TLV_TYPE_TRIGGER, 28 IWL_DBG_TLV_TYPE_NUM, 29 }; 30 31 /** 32 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 33 * @min_ver: min version supported 34 * @max_ver: max version supported 35 */ 36 struct iwl_dbg_tlv_ver_data { 37 int min_ver; 38 int max_ver; 39 }; 40 41 /** 42 * struct iwl_dbg_tlv_timer_node - timer node struct 43 * @list: list of &struct iwl_dbg_tlv_timer_node 44 * @timer: timer 45 * @fwrt: &struct iwl_fw_runtime 46 * @tlv: TLV attach to the timer node 47 */ 48 struct iwl_dbg_tlv_timer_node { 49 struct list_head list; 50 struct timer_list timer; 51 struct iwl_fw_runtime *fwrt; 52 struct iwl_ucode_tlv *tlv; 53 }; 54 55 static const struct iwl_dbg_tlv_ver_data 56 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 57 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 58 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 59 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 62 }; 63 64 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, 65 struct list_head *list) 66 { 67 u32 len = le32_to_cpu(tlv->length); 68 struct iwl_dbg_tlv_node *node; 69 70 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 71 if (!node) 72 return -ENOMEM; 73 74 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len); 75 list_add_tail(&node->list, list); 76 77 return 0; 78 } 79 80 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) 81 { 82 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 83 u32 type = le32_to_cpu(tlv->type); 84 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 85 u32 ver = le32_to_cpu(hdr->version); 86 87 if (ver < dbg_ver_table[tlv_idx].min_ver || 88 ver > dbg_ver_table[tlv_idx].max_ver) 89 return false; 90 91 return true; 92 } 93 94 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 95 const struct iwl_ucode_tlv *tlv) 96 { 97 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; 98 99 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 100 return -EINVAL; 101 102 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 103 debug_info->debug_cfg_name); 104 105 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 106 } 107 108 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 109 const struct iwl_ucode_tlv *tlv) 110 { 111 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; 112 u32 buf_location; 113 u32 alloc_id; 114 115 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 116 return -EINVAL; 117 118 buf_location = le32_to_cpu(alloc->buf_location); 119 alloc_id = le32_to_cpu(alloc->alloc_id); 120 121 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 122 buf_location >= IWL_FW_INI_LOCATION_NUM) 123 goto err; 124 125 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 126 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 127 goto err; 128 129 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 130 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 131 goto err; 132 133 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 134 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1 && 135 alloc_id != IWL_FW_INI_ALLOCATION_ID_INTERNAL) 136 goto err; 137 138 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 139 140 return 0; 141 err: 142 IWL_ERR(trans, 143 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 144 alloc_id, buf_location); 145 return -EINVAL; 146 } 147 148 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 149 const struct iwl_ucode_tlv *tlv) 150 { 151 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; 152 u32 tp = le32_to_cpu(hcmd->time_point); 153 154 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 155 return -EINVAL; 156 157 /* Host commands can not be sent in early time point since the FW 158 * is not ready 159 */ 160 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 161 tp >= IWL_FW_INI_TIME_POINT_NUM || 162 tp == IWL_FW_INI_TIME_POINT_EARLY) { 163 IWL_ERR(trans, 164 "WRT: Invalid time point %u for host command TLV\n", 165 tp); 166 return -EINVAL; 167 } 168 169 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 170 } 171 172 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 173 const struct iwl_ucode_tlv *tlv) 174 { 175 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; 176 struct iwl_ucode_tlv **active_reg; 177 u32 id = le32_to_cpu(reg->id); 178 u32 type = le32_to_cpu(reg->type); 179 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 180 181 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 182 return -EINVAL; 183 184 if (id >= IWL_FW_INI_MAX_REGION_ID) { 185 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 186 return -EINVAL; 187 } 188 189 if (type <= IWL_FW_INI_REGION_INVALID || 190 type >= IWL_FW_INI_REGION_NUM) { 191 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 192 return -EINVAL; 193 } 194 195 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 196 !trans->ops->read_config32) { 197 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 198 return -EOPNOTSUPP; 199 } 200 201 active_reg = &trans->dbg.active_regions[id]; 202 if (*active_reg) { 203 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 204 205 kfree(*active_reg); 206 } 207 208 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 209 if (!*active_reg) 210 return -ENOMEM; 211 212 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 213 214 return 0; 215 } 216 217 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 218 const struct iwl_ucode_tlv *tlv) 219 { 220 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; 221 struct iwl_fw_ini_trigger_tlv *dup_trig; 222 u32 tp = le32_to_cpu(trig->time_point); 223 struct iwl_ucode_tlv *dup = NULL; 224 int ret; 225 226 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 227 return -EINVAL; 228 229 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 230 tp >= IWL_FW_INI_TIME_POINT_NUM) { 231 IWL_ERR(trans, 232 "WRT: Invalid time point %u for trigger TLV\n", 233 tp); 234 return -EINVAL; 235 } 236 237 if (!le32_to_cpu(trig->occurrences)) { 238 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 239 GFP_KERNEL); 240 if (!dup) 241 return -ENOMEM; 242 dup_trig = (void *)dup->data; 243 dup_trig->occurrences = cpu_to_le32(-1); 244 tlv = dup; 245 } 246 247 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 248 kfree(dup); 249 250 return ret; 251 } 252 253 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 254 const struct iwl_ucode_tlv *tlv) = { 255 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 256 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 257 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 258 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 259 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 260 }; 261 262 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, 263 bool ext) 264 { 265 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 266 u32 type = le32_to_cpu(tlv->type); 267 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 268 u32 domain = le32_to_cpu(hdr->domain); 269 enum iwl_ini_cfg_state *cfg_state = ext ? 270 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 271 int ret; 272 273 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 274 !(domain & trans->dbg.domains_bitmap)) { 275 IWL_DEBUG_FW(trans, 276 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 277 domain, trans->dbg.domains_bitmap); 278 return; 279 } 280 281 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 282 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 283 goto out_err; 284 } 285 286 if (!iwl_dbg_tlv_ver_support(tlv)) { 287 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 288 le32_to_cpu(hdr->version)); 289 goto out_err; 290 } 291 292 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 293 if (ret) { 294 IWL_ERR(trans, 295 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 296 type, ret, ext); 297 goto out_err; 298 } 299 300 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 301 *cfg_state = IWL_INI_CFG_STATE_LOADED; 302 303 return; 304 305 out_err: 306 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 307 } 308 309 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 310 { 311 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 312 struct iwl_dbg_tlv_timer_node *node, *tmp; 313 314 list_for_each_entry_safe(node, tmp, timer_list, list) { 315 del_timer(&node->timer); 316 list_del(&node->list); 317 kfree(node); 318 } 319 } 320 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 321 322 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 323 enum iwl_fw_ini_allocation_id alloc_id) 324 { 325 struct iwl_fw_mon *fw_mon; 326 int i; 327 328 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 329 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 330 return; 331 332 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 333 334 for (i = 0; i < fw_mon->num_frags; i++) { 335 struct iwl_dram_data *frag = &fw_mon->frags[i]; 336 337 dma_free_coherent(trans->dev, frag->size, frag->block, 338 frag->physical); 339 340 frag->physical = 0; 341 frag->block = NULL; 342 frag->size = 0; 343 } 344 345 kfree(fw_mon->frags); 346 fw_mon->frags = NULL; 347 fw_mon->num_frags = 0; 348 } 349 350 void iwl_dbg_tlv_free(struct iwl_trans *trans) 351 { 352 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 353 int i; 354 355 iwl_dbg_tlv_del_timers(trans); 356 357 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 358 struct iwl_ucode_tlv **active_reg = 359 &trans->dbg.active_regions[i]; 360 361 kfree(*active_reg); 362 *active_reg = NULL; 363 } 364 365 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 366 &trans->dbg.debug_info_tlv_list, list) { 367 list_del(&tlv_node->list); 368 kfree(tlv_node); 369 } 370 371 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 372 struct iwl_dbg_tlv_time_point_data *tp = 373 &trans->dbg.time_point[i]; 374 375 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 376 list) { 377 list_del(&tlv_node->list); 378 kfree(tlv_node); 379 } 380 381 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 382 list) { 383 list_del(&tlv_node->list); 384 kfree(tlv_node); 385 } 386 387 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 388 &tp->active_trig_list, list) { 389 list_del(&tlv_node->list); 390 kfree(tlv_node); 391 } 392 } 393 394 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 395 iwl_dbg_tlv_fragments_free(trans, i); 396 } 397 398 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 399 size_t len) 400 { 401 const struct iwl_ucode_tlv *tlv; 402 u32 tlv_len; 403 404 while (len >= sizeof(*tlv)) { 405 len -= sizeof(*tlv); 406 tlv = (void *)data; 407 408 tlv_len = le32_to_cpu(tlv->length); 409 410 if (len < tlv_len) { 411 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 412 len, tlv_len); 413 return -EINVAL; 414 } 415 len -= ALIGN(tlv_len, 4); 416 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 417 418 iwl_dbg_tlv_alloc(trans, tlv, true); 419 } 420 421 return 0; 422 } 423 424 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 425 { 426 const struct firmware *fw; 427 int res; 428 429 if (!iwlwifi_mod_params.enable_ini) 430 return; 431 432 res = firmware_request_nowarn(&fw, "iwl-debug-yoyo.bin", dev); 433 if (res) 434 return; 435 436 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 437 438 release_firmware(fw); 439 } 440 441 void iwl_dbg_tlv_init(struct iwl_trans *trans) 442 { 443 int i; 444 445 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 446 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 447 448 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 449 struct iwl_dbg_tlv_time_point_data *tp = 450 &trans->dbg.time_point[i]; 451 452 INIT_LIST_HEAD(&tp->trig_list); 453 INIT_LIST_HEAD(&tp->hcmd_list); 454 INIT_LIST_HEAD(&tp->active_trig_list); 455 } 456 } 457 458 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 459 struct iwl_dram_data *frag, u32 pages) 460 { 461 void *block = NULL; 462 dma_addr_t physical; 463 464 if (!frag || frag->size || !pages) 465 return -EIO; 466 467 /* 468 * We try to allocate as many pages as we can, starting with 469 * the requested amount and going down until we can allocate 470 * something. Because of DIV_ROUND_UP(), pages will never go 471 * down to 0 and stop the loop, so stop when pages reaches 1, 472 * which is too small anyway. 473 */ 474 while (pages > 1) { 475 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 476 &physical, 477 GFP_KERNEL | __GFP_NOWARN); 478 if (block) 479 break; 480 481 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 482 pages * PAGE_SIZE); 483 484 pages = DIV_ROUND_UP(pages, 2); 485 } 486 487 if (!block) 488 return -ENOMEM; 489 490 frag->physical = physical; 491 frag->block = block; 492 frag->size = pages * PAGE_SIZE; 493 494 return pages; 495 } 496 497 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 498 enum iwl_fw_ini_allocation_id alloc_id) 499 { 500 struct iwl_fw_mon *fw_mon; 501 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 502 u32 num_frags, remain_pages, frag_pages; 503 int i; 504 505 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 506 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 507 return -EIO; 508 509 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 510 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 511 512 if (fw_mon->num_frags || 513 fw_mon_cfg->buf_location != 514 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 515 return 0; 516 517 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 518 if (!fw_has_capa(&fwrt->fw->ucode_capa, 519 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) { 520 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 521 return -EIO; 522 num_frags = 1; 523 } 524 525 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 526 PAGE_SIZE); 527 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 528 num_frags = min_t(u32, num_frags, remain_pages); 529 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 530 531 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 532 if (!fw_mon->frags) 533 return -ENOMEM; 534 535 for (i = 0; i < num_frags; i++) { 536 int pages = min_t(u32, frag_pages, remain_pages); 537 538 IWL_DEBUG_FW(fwrt, 539 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 540 alloc_id, i, pages * PAGE_SIZE); 541 542 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 543 pages); 544 if (pages < 0) { 545 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 546 (remain_pages * PAGE_SIZE); 547 548 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 549 iwl_dbg_tlv_fragments_free(fwrt->trans, 550 alloc_id); 551 return pages; 552 } 553 break; 554 } 555 556 remain_pages -= pages; 557 fw_mon->num_frags++; 558 } 559 560 return 0; 561 } 562 563 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 564 enum iwl_fw_ini_allocation_id alloc_id) 565 { 566 struct iwl_fw_mon *fw_mon; 567 u32 remain_frags, num_commands; 568 int i, fw_mon_idx = 0; 569 570 if (!fw_has_capa(&fwrt->fw->ucode_capa, 571 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 572 return 0; 573 574 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 575 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 576 return -EIO; 577 578 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 579 IWL_FW_INI_LOCATION_DRAM_PATH) 580 return 0; 581 582 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 583 584 /* the first fragment of DBGC1 is given to the FW via register 585 * or context info 586 */ 587 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 588 fw_mon_idx++; 589 590 remain_frags = fw_mon->num_frags - fw_mon_idx; 591 if (!remain_frags) 592 return 0; 593 594 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 595 596 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 597 alloc_id); 598 599 for (i = 0; i < num_commands; i++) { 600 u32 num_frags = min_t(u32, remain_frags, 601 BUF_ALLOC_MAX_NUM_FRAGS); 602 struct iwl_buf_alloc_cmd data = { 603 .alloc_id = cpu_to_le32(alloc_id), 604 .num_frags = cpu_to_le32(num_frags), 605 .buf_location = 606 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 607 }; 608 struct iwl_host_cmd hcmd = { 609 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 610 .data[0] = &data, 611 .len[0] = sizeof(data), 612 }; 613 int ret, j; 614 615 for (j = 0; j < num_frags; j++) { 616 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 617 struct iwl_dram_data *fw_mon_frag = 618 &fw_mon->frags[fw_mon_idx++]; 619 620 frag->addr = cpu_to_le64(fw_mon_frag->physical); 621 frag->size = cpu_to_le32(fw_mon_frag->size); 622 } 623 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 624 if (ret) 625 return ret; 626 627 remain_frags -= num_frags; 628 } 629 630 return 0; 631 } 632 633 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 634 { 635 int ret, i; 636 637 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 638 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 639 if (ret) 640 IWL_WARN(fwrt, 641 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 642 i, ret); 643 } 644 } 645 646 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 647 struct list_head *hcmd_list) 648 { 649 struct iwl_dbg_tlv_node *node; 650 651 list_for_each_entry(node, hcmd_list, list) { 652 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 653 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 654 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 655 struct iwl_host_cmd cmd = { 656 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 657 .len = { hcmd_len, }, 658 .data = { hcmd_data->data, }, 659 }; 660 661 iwl_trans_send_cmd(fwrt->trans, &cmd); 662 } 663 } 664 665 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 666 { 667 struct iwl_dbg_tlv_timer_node *timer_node = 668 from_timer(timer_node, t, timer); 669 struct iwl_fwrt_dump_data dump_data = { 670 .trig = (void *)timer_node->tlv->data, 671 }; 672 int ret; 673 674 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data); 675 if (!ret || ret == -EBUSY) { 676 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 677 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 678 679 if (!occur) 680 return; 681 682 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 683 } 684 } 685 686 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 687 { 688 struct iwl_dbg_tlv_node *node; 689 struct list_head *trig_list = 690 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 691 692 list_for_each_entry(node, trig_list, list) { 693 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 694 struct iwl_dbg_tlv_timer_node *timer_node; 695 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 696 u32 min_interval = 100; 697 698 if (!occur) 699 continue; 700 701 /* make sure there is at least one dword of data for the 702 * interval value 703 */ 704 if (le32_to_cpu(node->tlv.length) < 705 sizeof(*trig) + sizeof(__le32)) { 706 IWL_ERR(fwrt, 707 "WRT: Invalid periodic trigger data was not given\n"); 708 continue; 709 } 710 711 if (le32_to_cpu(trig->data[0]) < min_interval) { 712 IWL_WARN(fwrt, 713 "WRT: Override min interval from %u to %u msec\n", 714 le32_to_cpu(trig->data[0]), min_interval); 715 trig->data[0] = cpu_to_le32(min_interval); 716 } 717 718 collect_interval = le32_to_cpu(trig->data[0]); 719 720 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 721 if (!timer_node) { 722 IWL_ERR(fwrt, 723 "WRT: Failed to allocate periodic trigger\n"); 724 continue; 725 } 726 727 timer_node->fwrt = fwrt; 728 timer_node->tlv = &node->tlv; 729 timer_setup(&timer_node->timer, 730 iwl_dbg_tlv_periodic_trig_handler, 0); 731 732 list_add_tail(&timer_node->list, 733 &fwrt->trans->dbg.periodic_trig_list); 734 735 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 736 737 mod_timer(&timer_node->timer, 738 jiffies + msecs_to_jiffies(collect_interval)); 739 } 740 } 741 742 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, 743 const struct iwl_ucode_tlv *old) 744 { 745 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; 746 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; 747 const __le32 *new_data = new_trig->data, *old_data = old_trig->data; 748 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 749 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 750 int i, j; 751 752 for (i = 0; i < new_dwords_num; i++) { 753 bool match = false; 754 755 for (j = 0; j < old_dwords_num; j++) { 756 if (new_data[i] == old_data[j]) { 757 match = true; 758 break; 759 } 760 } 761 if (!match) 762 return false; 763 } 764 765 return true; 766 } 767 768 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 769 struct iwl_ucode_tlv *trig_tlv, 770 struct iwl_dbg_tlv_node *node) 771 { 772 struct iwl_ucode_tlv *node_tlv = &node->tlv; 773 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 774 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 775 u32 policy = le32_to_cpu(trig->apply_policy); 776 u32 size = le32_to_cpu(trig_tlv->length); 777 u32 trig_data_len = size - sizeof(*trig); 778 u32 offset = 0; 779 780 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 781 u32 data_len = le32_to_cpu(node_tlv->length) - 782 sizeof(*node_trig); 783 784 IWL_DEBUG_FW(fwrt, 785 "WRT: Appending trigger data (time point %u)\n", 786 le32_to_cpu(trig->time_point)); 787 788 offset += data_len; 789 size += data_len; 790 } else { 791 IWL_DEBUG_FW(fwrt, 792 "WRT: Overriding trigger data (time point %u)\n", 793 le32_to_cpu(trig->time_point)); 794 } 795 796 if (size != le32_to_cpu(node_tlv->length)) { 797 struct list_head *prev = node->list.prev; 798 struct iwl_dbg_tlv_node *tmp; 799 800 list_del(&node->list); 801 802 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 803 if (!tmp) { 804 IWL_WARN(fwrt, 805 "WRT: No memory to override trigger (time point %u)\n", 806 le32_to_cpu(trig->time_point)); 807 808 list_add(&node->list, prev); 809 810 return -ENOMEM; 811 } 812 813 list_add(&tmp->list, prev); 814 node_tlv = &tmp->tlv; 815 node_trig = (void *)node_tlv->data; 816 } 817 818 memcpy(node_trig->data + offset, trig->data, trig_data_len); 819 node_tlv->length = cpu_to_le32(size); 820 821 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 822 IWL_DEBUG_FW(fwrt, 823 "WRT: Overriding trigger configuration (time point %u)\n", 824 le32_to_cpu(trig->time_point)); 825 826 /* the first 11 dwords are configuration related */ 827 memcpy(node_trig, trig, sizeof(__le32) * 11); 828 } 829 830 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 831 IWL_DEBUG_FW(fwrt, 832 "WRT: Overriding trigger regions (time point %u)\n", 833 le32_to_cpu(trig->time_point)); 834 835 node_trig->regions_mask = trig->regions_mask; 836 } else { 837 IWL_DEBUG_FW(fwrt, 838 "WRT: Appending trigger regions (time point %u)\n", 839 le32_to_cpu(trig->time_point)); 840 841 node_trig->regions_mask |= trig->regions_mask; 842 } 843 844 return 0; 845 } 846 847 static int 848 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 849 struct list_head *trig_list, 850 struct iwl_ucode_tlv *trig_tlv) 851 { 852 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 853 struct iwl_dbg_tlv_node *node, *match = NULL; 854 u32 policy = le32_to_cpu(trig->apply_policy); 855 856 list_for_each_entry(node, trig_list, list) { 857 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 858 break; 859 860 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 861 is_trig_data_contained(trig_tlv, &node->tlv)) { 862 match = node; 863 break; 864 } 865 } 866 867 if (!match) { 868 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 869 le32_to_cpu(trig->time_point)); 870 return iwl_dbg_tlv_add(trig_tlv, trig_list); 871 } 872 873 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 874 } 875 876 static void 877 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 878 struct iwl_dbg_tlv_time_point_data *tp) 879 { 880 struct iwl_dbg_tlv_node *node; 881 struct list_head *trig_list = &tp->trig_list; 882 struct list_head *active_trig_list = &tp->active_trig_list; 883 884 list_for_each_entry(node, trig_list, list) { 885 struct iwl_ucode_tlv *tlv = &node->tlv; 886 887 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 888 } 889 } 890 891 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 892 struct iwl_fwrt_dump_data *dump_data, 893 union iwl_dbg_tlv_tp_data *tp_data, 894 u32 trig_data) 895 { 896 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 897 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 898 899 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 900 pkt->hdr.group_id == wanted_hdr->group_id)) { 901 struct iwl_rx_packet *fw_pkt = 902 kmemdup(pkt, 903 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 904 GFP_ATOMIC); 905 906 if (!fw_pkt) 907 return false; 908 909 dump_data->fw_pkt = fw_pkt; 910 911 return true; 912 } 913 914 return false; 915 } 916 917 static int 918 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, 919 struct list_head *active_trig_list, 920 union iwl_dbg_tlv_tp_data *tp_data, 921 bool (*data_check)(struct iwl_fw_runtime *fwrt, 922 struct iwl_fwrt_dump_data *dump_data, 923 union iwl_dbg_tlv_tp_data *tp_data, 924 u32 trig_data)) 925 { 926 struct iwl_dbg_tlv_node *node; 927 928 list_for_each_entry(node, active_trig_list, list) { 929 struct iwl_fwrt_dump_data dump_data = { 930 .trig = (void *)node->tlv.data, 931 }; 932 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 933 data); 934 int ret, i; 935 936 if (!num_data) { 937 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 938 if (ret) 939 return ret; 940 } 941 942 for (i = 0; i < num_data; i++) { 943 if (!data_check || 944 data_check(fwrt, &dump_data, tp_data, 945 le32_to_cpu(dump_data.trig->data[i]))) { 946 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 947 if (ret) 948 return ret; 949 950 break; 951 } 952 } 953 } 954 955 return 0; 956 } 957 958 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 959 { 960 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 961 int ret, i; 962 u32 failed_alloc = 0; 963 964 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) 965 return; 966 967 IWL_DEBUG_FW(fwrt, 968 "WRT: Generating active triggers list, domain 0x%x\n", 969 fwrt->trans->dbg.domains_bitmap); 970 971 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 972 struct iwl_dbg_tlv_time_point_data *tp = 973 &fwrt->trans->dbg.time_point[i]; 974 975 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 976 } 977 978 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 979 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 980 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 981 &fwrt->trans->dbg.fw_mon_cfg[i]; 982 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 983 984 if (dest == IWL_FW_INI_LOCATION_INVALID) 985 continue; 986 987 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 988 *ini_dest = dest; 989 990 if (dest != *ini_dest) 991 continue; 992 993 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 994 995 if (ret) { 996 IWL_WARN(fwrt, 997 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 998 i, ret); 999 failed_alloc |= BIT(i); 1000 } 1001 } 1002 1003 if (!failed_alloc) 1004 return; 1005 1006 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { 1007 struct iwl_fw_ini_region_tlv *reg; 1008 struct iwl_ucode_tlv **active_reg = 1009 &fwrt->trans->dbg.active_regions[i]; 1010 u32 reg_type; 1011 1012 if (!*active_reg) 1013 continue; 1014 1015 reg = (void *)(*active_reg)->data; 1016 reg_type = le32_to_cpu(reg->type); 1017 1018 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || 1019 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) 1020 continue; 1021 1022 IWL_DEBUG_FW(fwrt, 1023 "WRT: removing allocation id %d from region id %d\n", 1024 le32_to_cpu(reg->dram_alloc_id), i); 1025 1026 failed_alloc &= ~le32_to_cpu(reg->dram_alloc_id); 1027 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1028 1029 kfree(*active_reg); 1030 *active_reg = NULL; 1031 } 1032 } 1033 1034 void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1035 enum iwl_fw_ini_time_point tp_id, 1036 union iwl_dbg_tlv_tp_data *tp_data) 1037 { 1038 struct list_head *hcmd_list, *trig_list; 1039 1040 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1041 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1042 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1043 return; 1044 1045 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1046 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1047 1048 switch (tp_id) { 1049 case IWL_FW_INI_TIME_POINT_EARLY: 1050 iwl_dbg_tlv_init_cfg(fwrt); 1051 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1052 break; 1053 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1054 iwl_dbg_tlv_apply_buffers(fwrt); 1055 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1056 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1057 break; 1058 case IWL_FW_INI_TIME_POINT_PERIODIC: 1059 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1060 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1061 break; 1062 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1063 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1064 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1065 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1066 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, 1067 iwl_dbg_tlv_check_fw_pkt); 1068 break; 1069 default: 1070 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1071 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1072 break; 1073 } 1074 } 1075 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point); 1076