1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2021 Intel Corporation 4 */ 5 #include <linux/firmware.h> 6 #include "iwl-drv.h" 7 #include "iwl-trans.h" 8 #include "iwl-dbg-tlv.h" 9 #include "fw/dbg.h" 10 #include "fw/runtime.h" 11 12 /** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV 20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 21 */ 22 enum iwl_dbg_tlv_type { 23 IWL_DBG_TLV_TYPE_DEBUG_INFO = 24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 25 IWL_DBG_TLV_TYPE_BUF_ALLOC, 26 IWL_DBG_TLV_TYPE_HCMD, 27 IWL_DBG_TLV_TYPE_REGION, 28 IWL_DBG_TLV_TYPE_TRIGGER, 29 IWL_DBG_TLV_TYPE_CONF_SET, 30 IWL_DBG_TLV_TYPE_NUM, 31 }; 32 33 /** 34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 35 * @min_ver: min version supported 36 * @max_ver: max version supported 37 */ 38 struct iwl_dbg_tlv_ver_data { 39 int min_ver; 40 int max_ver; 41 }; 42 43 /** 44 * struct iwl_dbg_tlv_timer_node - timer node struct 45 * @list: list of &struct iwl_dbg_tlv_timer_node 46 * @timer: timer 47 * @fwrt: &struct iwl_fw_runtime 48 * @tlv: TLV attach to the timer node 49 */ 50 struct iwl_dbg_tlv_timer_node { 51 struct list_head list; 52 struct timer_list timer; 53 struct iwl_fw_runtime *fwrt; 54 struct iwl_ucode_tlv *tlv; 55 }; 56 57 static const struct iwl_dbg_tlv_ver_data 58 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,}, 63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,}, 65 }; 66 67 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, 68 struct list_head *list) 69 { 70 u32 len = le32_to_cpu(tlv->length); 71 struct iwl_dbg_tlv_node *node; 72 73 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 74 if (!node) 75 return -ENOMEM; 76 77 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len); 78 list_add_tail(&node->list, list); 79 80 return 0; 81 } 82 83 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) 84 { 85 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 86 u32 type = le32_to_cpu(tlv->type); 87 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 88 u32 ver = le32_to_cpu(hdr->version); 89 90 if (ver < dbg_ver_table[tlv_idx].min_ver || 91 ver > dbg_ver_table[tlv_idx].max_ver) 92 return false; 93 94 return true; 95 } 96 97 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 98 const struct iwl_ucode_tlv *tlv) 99 { 100 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; 101 102 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 103 return -EINVAL; 104 105 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 106 debug_info->debug_cfg_name); 107 108 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 109 } 110 111 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 112 const struct iwl_ucode_tlv *tlv) 113 { 114 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; 115 u32 buf_location; 116 u32 alloc_id; 117 118 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 119 return -EINVAL; 120 121 buf_location = le32_to_cpu(alloc->buf_location); 122 alloc_id = le32_to_cpu(alloc->alloc_id); 123 124 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 125 buf_location >= IWL_FW_INI_LOCATION_NUM) 126 goto err; 127 128 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 129 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 130 goto err; 131 132 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 133 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 134 goto err; 135 136 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 137 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 138 goto err; 139 140 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 141 142 return 0; 143 err: 144 IWL_ERR(trans, 145 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 146 alloc_id, buf_location); 147 return -EINVAL; 148 } 149 150 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 151 const struct iwl_ucode_tlv *tlv) 152 { 153 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; 154 u32 tp = le32_to_cpu(hcmd->time_point); 155 156 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 157 return -EINVAL; 158 159 /* Host commands can not be sent in early time point since the FW 160 * is not ready 161 */ 162 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 163 tp >= IWL_FW_INI_TIME_POINT_NUM || 164 tp == IWL_FW_INI_TIME_POINT_EARLY) { 165 IWL_ERR(trans, 166 "WRT: Invalid time point %u for host command TLV\n", 167 tp); 168 return -EINVAL; 169 } 170 171 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 172 } 173 174 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 175 const struct iwl_ucode_tlv *tlv) 176 { 177 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; 178 struct iwl_ucode_tlv **active_reg; 179 u32 id = le32_to_cpu(reg->id); 180 u8 type = reg->type; 181 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 182 183 /* 184 * The higher part of the ID in from version 2 is irrelevant for 185 * us, so mask it out. 186 */ 187 if (le32_to_cpu(reg->hdr.version) >= 2) 188 id &= IWL_FW_INI_REGION_V2_MASK; 189 190 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 191 return -EINVAL; 192 193 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */ 194 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n", 195 IWL_FW_INI_MAX_NAME, reg->name); 196 197 if (id >= IWL_FW_INI_MAX_REGION_ID) { 198 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 199 return -EINVAL; 200 } 201 202 if (type <= IWL_FW_INI_REGION_INVALID || 203 type >= IWL_FW_INI_REGION_NUM) { 204 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 205 return -EINVAL; 206 } 207 208 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 209 !trans->ops->read_config32) { 210 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 211 return -EOPNOTSUPP; 212 } 213 214 active_reg = &trans->dbg.active_regions[id]; 215 if (*active_reg) { 216 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 217 218 kfree(*active_reg); 219 } 220 221 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 222 if (!*active_reg) 223 return -ENOMEM; 224 225 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 226 227 return 0; 228 } 229 230 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 231 const struct iwl_ucode_tlv *tlv) 232 { 233 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; 234 struct iwl_fw_ini_trigger_tlv *dup_trig; 235 u32 tp = le32_to_cpu(trig->time_point); 236 u32 rf = le32_to_cpu(trig->reset_fw); 237 struct iwl_ucode_tlv *dup = NULL; 238 int ret; 239 240 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 241 return -EINVAL; 242 243 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 244 tp >= IWL_FW_INI_TIME_POINT_NUM) { 245 IWL_ERR(trans, 246 "WRT: Invalid time point %u for trigger TLV\n", 247 tp); 248 return -EINVAL; 249 } 250 251 IWL_DEBUG_FW(trans, 252 "WRT: time point %u for trigger TLV with reset_fw %u\n", 253 tp, rf); 254 trans->dbg.last_tp_resetfw = 0xFF; 255 if (!le32_to_cpu(trig->occurrences)) { 256 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 257 GFP_KERNEL); 258 if (!dup) 259 return -ENOMEM; 260 dup_trig = (void *)dup->data; 261 dup_trig->occurrences = cpu_to_le32(-1); 262 tlv = dup; 263 } 264 265 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 266 kfree(dup); 267 268 return ret; 269 } 270 271 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans, 272 const struct iwl_ucode_tlv *tlv) 273 { 274 struct iwl_fw_ini_conf_set_tlv *conf_set = (void *)tlv->data; 275 u32 tp = le32_to_cpu(conf_set->time_point); 276 u32 type = le32_to_cpu(conf_set->set_type); 277 278 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 279 tp >= IWL_FW_INI_TIME_POINT_NUM) { 280 IWL_DEBUG_FW(trans, 281 "WRT: Invalid time point %u for config set TLV\n", tp); 282 return -EINVAL; 283 } 284 285 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID || 286 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) { 287 IWL_DEBUG_FW(trans, 288 "WRT: Invalid config set type %u for config set TLV\n", type); 289 return -EINVAL; 290 } 291 292 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list); 293 } 294 295 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 296 const struct iwl_ucode_tlv *tlv) = { 297 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 298 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 299 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 300 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 301 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 302 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set, 303 }; 304 305 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, 306 bool ext) 307 { 308 enum iwl_ini_cfg_state *cfg_state = ext ? 309 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 310 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 311 u32 type; 312 u32 tlv_idx; 313 u32 domain; 314 int ret; 315 316 if (le32_to_cpu(tlv->length) < sizeof(*hdr)) 317 return; 318 319 type = le32_to_cpu(tlv->type); 320 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 321 domain = le32_to_cpu(hdr->domain); 322 323 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 324 !(domain & trans->dbg.domains_bitmap)) { 325 IWL_DEBUG_FW(trans, 326 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 327 domain, trans->dbg.domains_bitmap); 328 return; 329 } 330 331 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 332 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 333 goto out_err; 334 } 335 336 if (!iwl_dbg_tlv_ver_support(tlv)) { 337 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 338 le32_to_cpu(hdr->version)); 339 goto out_err; 340 } 341 342 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 343 if (ret) { 344 IWL_ERR(trans, 345 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 346 type, ret, ext); 347 goto out_err; 348 } 349 350 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 351 *cfg_state = IWL_INI_CFG_STATE_LOADED; 352 353 return; 354 355 out_err: 356 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 357 } 358 359 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 360 { 361 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 362 struct iwl_dbg_tlv_timer_node *node, *tmp; 363 364 list_for_each_entry_safe(node, tmp, timer_list, list) { 365 del_timer(&node->timer); 366 list_del(&node->list); 367 kfree(node); 368 } 369 } 370 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 371 372 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 373 enum iwl_fw_ini_allocation_id alloc_id) 374 { 375 struct iwl_fw_mon *fw_mon; 376 int i; 377 378 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 379 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 380 return; 381 382 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 383 384 for (i = 0; i < fw_mon->num_frags; i++) { 385 struct iwl_dram_data *frag = &fw_mon->frags[i]; 386 387 dma_free_coherent(trans->dev, frag->size, frag->block, 388 frag->physical); 389 390 frag->physical = 0; 391 frag->block = NULL; 392 frag->size = 0; 393 } 394 395 kfree(fw_mon->frags); 396 fw_mon->frags = NULL; 397 fw_mon->num_frags = 0; 398 } 399 400 void iwl_dbg_tlv_free(struct iwl_trans *trans) 401 { 402 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 403 int i; 404 405 iwl_dbg_tlv_del_timers(trans); 406 407 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 408 struct iwl_ucode_tlv **active_reg = 409 &trans->dbg.active_regions[i]; 410 411 kfree(*active_reg); 412 *active_reg = NULL; 413 } 414 415 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 416 &trans->dbg.debug_info_tlv_list, list) { 417 list_del(&tlv_node->list); 418 kfree(tlv_node); 419 } 420 421 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 422 struct iwl_dbg_tlv_time_point_data *tp = 423 &trans->dbg.time_point[i]; 424 425 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 426 list) { 427 list_del(&tlv_node->list); 428 kfree(tlv_node); 429 } 430 431 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 432 list) { 433 list_del(&tlv_node->list); 434 kfree(tlv_node); 435 } 436 437 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 438 &tp->active_trig_list, list) { 439 list_del(&tlv_node->list); 440 kfree(tlv_node); 441 } 442 443 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 444 &tp->config_list, list) { 445 list_del(&tlv_node->list); 446 kfree(tlv_node); 447 } 448 449 } 450 451 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 452 iwl_dbg_tlv_fragments_free(trans, i); 453 } 454 455 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 456 size_t len) 457 { 458 const struct iwl_ucode_tlv *tlv; 459 u32 tlv_len; 460 461 while (len >= sizeof(*tlv)) { 462 len -= sizeof(*tlv); 463 tlv = (void *)data; 464 465 tlv_len = le32_to_cpu(tlv->length); 466 467 if (len < tlv_len) { 468 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 469 len, tlv_len); 470 return -EINVAL; 471 } 472 len -= ALIGN(tlv_len, 4); 473 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 474 475 iwl_dbg_tlv_alloc(trans, tlv, true); 476 } 477 478 return 0; 479 } 480 481 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 482 { 483 const struct firmware *fw; 484 const char *yoyo_bin = "iwl-debug-yoyo.bin"; 485 int res; 486 487 if (!iwlwifi_mod_params.enable_ini || 488 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000) 489 return; 490 491 res = firmware_request_nowarn(&fw, yoyo_bin, dev); 492 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin); 493 494 if (res) 495 return; 496 497 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 498 499 release_firmware(fw); 500 } 501 502 void iwl_dbg_tlv_init(struct iwl_trans *trans) 503 { 504 int i; 505 506 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 507 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 508 509 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 510 struct iwl_dbg_tlv_time_point_data *tp = 511 &trans->dbg.time_point[i]; 512 513 INIT_LIST_HEAD(&tp->trig_list); 514 INIT_LIST_HEAD(&tp->hcmd_list); 515 INIT_LIST_HEAD(&tp->active_trig_list); 516 INIT_LIST_HEAD(&tp->config_list); 517 } 518 } 519 520 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 521 struct iwl_dram_data *frag, u32 pages) 522 { 523 void *block = NULL; 524 dma_addr_t physical; 525 526 if (!frag || frag->size || !pages) 527 return -EIO; 528 529 /* 530 * We try to allocate as many pages as we can, starting with 531 * the requested amount and going down until we can allocate 532 * something. Because of DIV_ROUND_UP(), pages will never go 533 * down to 0 and stop the loop, so stop when pages reaches 1, 534 * which is too small anyway. 535 */ 536 while (pages > 1) { 537 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 538 &physical, 539 GFP_KERNEL | __GFP_NOWARN); 540 if (block) 541 break; 542 543 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 544 pages * PAGE_SIZE); 545 546 pages = DIV_ROUND_UP(pages, 2); 547 } 548 549 if (!block) 550 return -ENOMEM; 551 552 frag->physical = physical; 553 frag->block = block; 554 frag->size = pages * PAGE_SIZE; 555 556 return pages; 557 } 558 559 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 560 enum iwl_fw_ini_allocation_id alloc_id) 561 { 562 struct iwl_fw_mon *fw_mon; 563 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 564 u32 num_frags, remain_pages, frag_pages; 565 int i; 566 567 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 568 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 569 return -EIO; 570 571 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 572 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 573 574 if (fw_mon->num_frags || 575 fw_mon_cfg->buf_location != 576 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 577 return 0; 578 579 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 580 if (!fw_has_capa(&fwrt->fw->ucode_capa, 581 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) { 582 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 583 return -EIO; 584 num_frags = 1; 585 } 586 587 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 588 PAGE_SIZE); 589 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 590 num_frags = min_t(u32, num_frags, remain_pages); 591 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 592 593 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 594 if (!fw_mon->frags) 595 return -ENOMEM; 596 597 for (i = 0; i < num_frags; i++) { 598 int pages = min_t(u32, frag_pages, remain_pages); 599 600 IWL_DEBUG_FW(fwrt, 601 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 602 alloc_id, i, pages * PAGE_SIZE); 603 604 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 605 pages); 606 if (pages < 0) { 607 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 608 (remain_pages * PAGE_SIZE); 609 610 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 611 iwl_dbg_tlv_fragments_free(fwrt->trans, 612 alloc_id); 613 return pages; 614 } 615 break; 616 } 617 618 remain_pages -= pages; 619 fw_mon->num_frags++; 620 } 621 622 return 0; 623 } 624 625 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 626 enum iwl_fw_ini_allocation_id alloc_id) 627 { 628 struct iwl_fw_mon *fw_mon; 629 u32 remain_frags, num_commands; 630 int i, fw_mon_idx = 0; 631 632 if (!fw_has_capa(&fwrt->fw->ucode_capa, 633 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 634 return 0; 635 636 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 637 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 638 return -EIO; 639 640 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 641 IWL_FW_INI_LOCATION_DRAM_PATH) 642 return 0; 643 644 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 645 646 /* the first fragment of DBGC1 is given to the FW via register 647 * or context info 648 */ 649 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 650 fw_mon_idx++; 651 652 remain_frags = fw_mon->num_frags - fw_mon_idx; 653 if (!remain_frags) 654 return 0; 655 656 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 657 658 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 659 alloc_id); 660 661 for (i = 0; i < num_commands; i++) { 662 u32 num_frags = min_t(u32, remain_frags, 663 BUF_ALLOC_MAX_NUM_FRAGS); 664 struct iwl_buf_alloc_cmd data = { 665 .alloc_id = cpu_to_le32(alloc_id), 666 .num_frags = cpu_to_le32(num_frags), 667 .buf_location = 668 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 669 }; 670 struct iwl_host_cmd hcmd = { 671 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 672 .data[0] = &data, 673 .len[0] = sizeof(data), 674 .flags = CMD_SEND_IN_RFKILL, 675 }; 676 int ret, j; 677 678 for (j = 0; j < num_frags; j++) { 679 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 680 struct iwl_dram_data *fw_mon_frag = 681 &fw_mon->frags[fw_mon_idx++]; 682 683 frag->addr = cpu_to_le64(fw_mon_frag->physical); 684 frag->size = cpu_to_le32(fw_mon_frag->size); 685 } 686 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 687 if (ret) 688 return ret; 689 690 remain_frags -= num_frags; 691 } 692 693 return 0; 694 } 695 696 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 697 { 698 int ret, i; 699 700 if (fw_has_capa(&fwrt->fw->ucode_capa, 701 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 702 return; 703 704 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 705 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 706 if (ret) 707 IWL_WARN(fwrt, 708 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 709 i, ret); 710 } 711 } 712 713 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt, 714 enum iwl_fw_ini_allocation_id alloc_id, 715 struct iwl_dram_info *dram_info) 716 { 717 struct iwl_fw_mon *fw_mon; 718 u32 remain_frags, num_frags; 719 int j, fw_mon_idx = 0; 720 struct iwl_buf_alloc_cmd *data; 721 722 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 723 IWL_FW_INI_LOCATION_DRAM_PATH) { 724 IWL_DEBUG_FW(fwrt, "DRAM_PATH is not supported alloc_id %u\n", alloc_id); 725 return -1; 726 } 727 728 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 729 730 /* the first fragment of DBGC1 is given to the FW via register 731 * or context info 732 */ 733 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 734 fw_mon_idx++; 735 736 remain_frags = fw_mon->num_frags - fw_mon_idx; 737 if (!remain_frags) 738 return -1; 739 740 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 741 data = &dram_info->dram_frags[alloc_id - 1]; 742 data->alloc_id = cpu_to_le32(alloc_id); 743 data->num_frags = cpu_to_le32(num_frags); 744 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH); 745 746 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n", 747 cpu_to_le32(alloc_id), cpu_to_le32(num_frags)); 748 749 for (j = 0; j < num_frags; j++) { 750 struct iwl_buf_alloc_frag *frag = &data->frags[j]; 751 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; 752 753 frag->addr = cpu_to_le64(fw_mon_frag->physical); 754 frag->size = cpu_to_le32(fw_mon_frag->size); 755 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n"); 756 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n", 757 j, cpu_to_le64(fw_mon_frag->physical), 758 cpu_to_le32(fw_mon_frag->size)); 759 } 760 return 0; 761 } 762 763 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt) 764 { 765 int ret, i, dram_alloc = 0; 766 struct iwl_dram_info dram_info; 767 struct iwl_dram_data *frags = 768 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0]; 769 770 if (!fw_has_capa(&fwrt->fw->ucode_capa, 771 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 772 return; 773 774 dram_info.first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); 775 dram_info.second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); 776 777 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1; 778 i <= IWL_FW_INI_ALLOCATION_ID_DBGC3; i++) { 779 ret = iwl_dbg_tlv_update_dram(fwrt, i, &dram_info); 780 if (!ret) 781 dram_alloc++; 782 else 783 IWL_WARN(fwrt, 784 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n", 785 i, ret); 786 } 787 if (dram_alloc) { 788 memcpy(frags->block, &dram_info, sizeof(dram_info)); 789 IWL_DEBUG_FW(fwrt, "block data after %016x\n", 790 *((int *)fwrt->trans->dbg.fw_mon_ini[1].frags[0].block)); 791 } 792 } 793 794 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 795 struct list_head *hcmd_list) 796 { 797 struct iwl_dbg_tlv_node *node; 798 799 list_for_each_entry(node, hcmd_list, list) { 800 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 801 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 802 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 803 struct iwl_host_cmd cmd = { 804 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 805 .len = { hcmd_len, }, 806 .data = { hcmd_data->data, }, 807 }; 808 809 iwl_trans_send_cmd(fwrt->trans, &cmd); 810 } 811 } 812 813 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt, 814 struct list_head *config_list) 815 { 816 struct iwl_dbg_tlv_node *node; 817 818 list_for_each_entry(node, config_list, list) { 819 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data; 820 u32 count, address, value; 821 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8; 822 u32 type = le32_to_cpu(config_list->set_type); 823 u32 offset = le32_to_cpu(config_list->addr_offset); 824 825 switch (type) { 826 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: { 827 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 828 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n"); 829 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n"); 830 continue; 831 } 832 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len); 833 for (count = 0; count < len; count++) { 834 address = le32_to_cpu(config_list->addr_val[count].address); 835 value = le32_to_cpu(config_list->addr_val[count].value); 836 iwl_trans_write_prph(fwrt->trans, address + offset, value); 837 } 838 iwl_trans_release_nic_access(fwrt->trans); 839 break; 840 } 841 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: { 842 for (count = 0; count < len; count++) { 843 address = le32_to_cpu(config_list->addr_val[count].address); 844 value = le32_to_cpu(config_list->addr_val[count].value); 845 iwl_trans_write_mem32(fwrt->trans, address + offset, value); 846 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n", 847 count, address, value); 848 } 849 break; 850 } 851 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: { 852 for (count = 0; count < len; count++) { 853 address = le32_to_cpu(config_list->addr_val[count].address); 854 value = le32_to_cpu(config_list->addr_val[count].value); 855 iwl_write32(fwrt->trans, address + offset, value); 856 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", 857 count, address, value); 858 } 859 break; 860 } 861 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: { 862 struct iwl_dbgc1_info dram_info = {}; 863 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0]; 864 __le64 dram_base_addr = cpu_to_le64(frags->physical); 865 __le32 dram_size = cpu_to_le32(frags->size); 866 u64 dram_addr = le64_to_cpu(dram_base_addr); 867 u32 ret; 868 869 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n", 870 dram_base_addr, dram_size); 871 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n", 872 le32_to_cpu(config_list->addr_offset)); 873 for (count = 0; count < len; count++) { 874 address = le32_to_cpu(config_list->addr_val[count].address); 875 dram_info.dbgc1_add_lsb = 876 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400); 877 dram_info.dbgc1_add_msb = 878 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32); 879 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400); 880 ret = iwl_trans_write_mem(fwrt->trans, 881 address + offset, &dram_info, 4); 882 if (ret) { 883 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n"); 884 break; 885 } 886 } 887 break; 888 } 889 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: { 890 u32 debug_token_config = 891 le32_to_cpu(config_list->addr_val[0].value); 892 893 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n", 894 debug_token_config); 895 fwrt->trans->dbg.ucode_preset = debug_token_config; 896 break; 897 } 898 default: 899 break; 900 } 901 } 902 } 903 904 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 905 { 906 struct iwl_dbg_tlv_timer_node *timer_node = 907 from_timer(timer_node, t, timer); 908 struct iwl_fwrt_dump_data dump_data = { 909 .trig = (void *)timer_node->tlv->data, 910 }; 911 int ret; 912 913 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false); 914 if (!ret || ret == -EBUSY) { 915 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 916 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 917 918 if (!occur) 919 return; 920 921 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 922 } 923 } 924 925 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 926 { 927 struct iwl_dbg_tlv_node *node; 928 struct list_head *trig_list = 929 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 930 931 list_for_each_entry(node, trig_list, list) { 932 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 933 struct iwl_dbg_tlv_timer_node *timer_node; 934 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 935 u32 min_interval = 100; 936 937 if (!occur) 938 continue; 939 940 /* make sure there is at least one dword of data for the 941 * interval value 942 */ 943 if (le32_to_cpu(node->tlv.length) < 944 sizeof(*trig) + sizeof(__le32)) { 945 IWL_ERR(fwrt, 946 "WRT: Invalid periodic trigger data was not given\n"); 947 continue; 948 } 949 950 if (le32_to_cpu(trig->data[0]) < min_interval) { 951 IWL_WARN(fwrt, 952 "WRT: Override min interval from %u to %u msec\n", 953 le32_to_cpu(trig->data[0]), min_interval); 954 trig->data[0] = cpu_to_le32(min_interval); 955 } 956 957 collect_interval = le32_to_cpu(trig->data[0]); 958 959 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 960 if (!timer_node) { 961 IWL_ERR(fwrt, 962 "WRT: Failed to allocate periodic trigger\n"); 963 continue; 964 } 965 966 timer_node->fwrt = fwrt; 967 timer_node->tlv = &node->tlv; 968 timer_setup(&timer_node->timer, 969 iwl_dbg_tlv_periodic_trig_handler, 0); 970 971 list_add_tail(&timer_node->list, 972 &fwrt->trans->dbg.periodic_trig_list); 973 974 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 975 976 mod_timer(&timer_node->timer, 977 jiffies + msecs_to_jiffies(collect_interval)); 978 } 979 } 980 981 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, 982 const struct iwl_ucode_tlv *old) 983 { 984 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; 985 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; 986 const __le32 *new_data = new_trig->data, *old_data = old_trig->data; 987 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 988 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 989 int i, j; 990 991 for (i = 0; i < new_dwords_num; i++) { 992 bool match = false; 993 994 for (j = 0; j < old_dwords_num; j++) { 995 if (new_data[i] == old_data[j]) { 996 match = true; 997 break; 998 } 999 } 1000 if (!match) 1001 return false; 1002 } 1003 1004 return true; 1005 } 1006 1007 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 1008 struct iwl_ucode_tlv *trig_tlv, 1009 struct iwl_dbg_tlv_node *node) 1010 { 1011 struct iwl_ucode_tlv *node_tlv = &node->tlv; 1012 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 1013 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1014 u32 policy = le32_to_cpu(trig->apply_policy); 1015 u32 size = le32_to_cpu(trig_tlv->length); 1016 u32 trig_data_len = size - sizeof(*trig); 1017 u32 offset = 0; 1018 1019 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 1020 u32 data_len = le32_to_cpu(node_tlv->length) - 1021 sizeof(*node_trig); 1022 1023 IWL_DEBUG_FW(fwrt, 1024 "WRT: Appending trigger data (time point %u)\n", 1025 le32_to_cpu(trig->time_point)); 1026 1027 offset += data_len; 1028 size += data_len; 1029 } else { 1030 IWL_DEBUG_FW(fwrt, 1031 "WRT: Overriding trigger data (time point %u)\n", 1032 le32_to_cpu(trig->time_point)); 1033 } 1034 1035 if (size != le32_to_cpu(node_tlv->length)) { 1036 struct list_head *prev = node->list.prev; 1037 struct iwl_dbg_tlv_node *tmp; 1038 1039 list_del(&node->list); 1040 1041 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 1042 if (!tmp) { 1043 IWL_WARN(fwrt, 1044 "WRT: No memory to override trigger (time point %u)\n", 1045 le32_to_cpu(trig->time_point)); 1046 1047 list_add(&node->list, prev); 1048 1049 return -ENOMEM; 1050 } 1051 1052 list_add(&tmp->list, prev); 1053 node_tlv = &tmp->tlv; 1054 node_trig = (void *)node_tlv->data; 1055 } 1056 1057 memcpy(node_trig->data + offset, trig->data, trig_data_len); 1058 node_tlv->length = cpu_to_le32(size); 1059 1060 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 1061 IWL_DEBUG_FW(fwrt, 1062 "WRT: Overriding trigger configuration (time point %u)\n", 1063 le32_to_cpu(trig->time_point)); 1064 1065 /* the first 11 dwords are configuration related */ 1066 memcpy(node_trig, trig, sizeof(__le32) * 11); 1067 } 1068 1069 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 1070 IWL_DEBUG_FW(fwrt, 1071 "WRT: Overriding trigger regions (time point %u)\n", 1072 le32_to_cpu(trig->time_point)); 1073 1074 node_trig->regions_mask = trig->regions_mask; 1075 } else { 1076 IWL_DEBUG_FW(fwrt, 1077 "WRT: Appending trigger regions (time point %u)\n", 1078 le32_to_cpu(trig->time_point)); 1079 1080 node_trig->regions_mask |= trig->regions_mask; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int 1087 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 1088 struct list_head *trig_list, 1089 struct iwl_ucode_tlv *trig_tlv) 1090 { 1091 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1092 struct iwl_dbg_tlv_node *node, *match = NULL; 1093 u32 policy = le32_to_cpu(trig->apply_policy); 1094 1095 list_for_each_entry(node, trig_list, list) { 1096 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 1097 break; 1098 1099 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 1100 is_trig_data_contained(trig_tlv, &node->tlv)) { 1101 match = node; 1102 break; 1103 } 1104 } 1105 1106 if (!match) { 1107 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 1108 le32_to_cpu(trig->time_point)); 1109 return iwl_dbg_tlv_add(trig_tlv, trig_list); 1110 } 1111 1112 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 1113 } 1114 1115 static void 1116 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 1117 struct iwl_dbg_tlv_time_point_data *tp) 1118 { 1119 struct iwl_dbg_tlv_node *node; 1120 struct list_head *trig_list = &tp->trig_list; 1121 struct list_head *active_trig_list = &tp->active_trig_list; 1122 1123 list_for_each_entry(node, trig_list, list) { 1124 struct iwl_ucode_tlv *tlv = &node->tlv; 1125 1126 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 1127 } 1128 } 1129 1130 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 1131 struct iwl_fwrt_dump_data *dump_data, 1132 union iwl_dbg_tlv_tp_data *tp_data, 1133 u32 trig_data) 1134 { 1135 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 1136 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 1137 1138 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 1139 pkt->hdr.group_id == wanted_hdr->group_id)) { 1140 struct iwl_rx_packet *fw_pkt = 1141 kmemdup(pkt, 1142 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 1143 GFP_ATOMIC); 1144 1145 if (!fw_pkt) 1146 return false; 1147 1148 dump_data->fw_pkt = fw_pkt; 1149 1150 return true; 1151 } 1152 1153 return false; 1154 } 1155 1156 static int 1157 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync, 1158 struct list_head *active_trig_list, 1159 union iwl_dbg_tlv_tp_data *tp_data, 1160 bool (*data_check)(struct iwl_fw_runtime *fwrt, 1161 struct iwl_fwrt_dump_data *dump_data, 1162 union iwl_dbg_tlv_tp_data *tp_data, 1163 u32 trig_data)) 1164 { 1165 struct iwl_dbg_tlv_node *node; 1166 1167 list_for_each_entry(node, active_trig_list, list) { 1168 struct iwl_fwrt_dump_data dump_data = { 1169 .trig = (void *)node->tlv.data, 1170 }; 1171 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 1172 data); 1173 int ret, i; 1174 u32 tp = le32_to_cpu(dump_data.trig->time_point); 1175 1176 1177 if (!num_data) { 1178 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1179 if (ret) 1180 return ret; 1181 } 1182 1183 for (i = 0; i < num_data; i++) { 1184 if (!data_check || 1185 data_check(fwrt, &dump_data, tp_data, 1186 le32_to_cpu(dump_data.trig->data[i]))) { 1187 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1188 if (ret) 1189 return ret; 1190 1191 break; 1192 } 1193 } 1194 1195 fwrt->trans->dbg.restart_required = FALSE; 1196 IWL_DEBUG_INFO(fwrt, "WRT: tp %d, reset_fw %d\n", 1197 tp, dump_data.trig->reset_fw); 1198 IWL_DEBUG_INFO(fwrt, "WRT: restart_required %d, last_tp_resetfw %d\n", 1199 fwrt->trans->dbg.restart_required, 1200 fwrt->trans->dbg.last_tp_resetfw); 1201 1202 if (fwrt->trans->trans_cfg->device_family == 1203 IWL_DEVICE_FAMILY_9000) { 1204 fwrt->trans->dbg.restart_required = TRUE; 1205 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT && 1206 fwrt->trans->dbg.last_tp_resetfw == 1207 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1208 fwrt->trans->dbg.restart_required = FALSE; 1209 fwrt->trans->dbg.last_tp_resetfw = 0xFF; 1210 IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n"); 1211 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1212 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) { 1213 IWL_DEBUG_INFO(fwrt, "WRT: stop and reload firmware\n"); 1214 fwrt->trans->dbg.restart_required = TRUE; 1215 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1216 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1217 IWL_DEBUG_INFO(fwrt, "WRT: stop only and no reload firmware\n"); 1218 fwrt->trans->dbg.restart_required = FALSE; 1219 fwrt->trans->dbg.last_tp_resetfw = 1220 le32_to_cpu(dump_data.trig->reset_fw); 1221 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1222 IWL_FW_INI_RESET_FW_MODE_NOTHING) { 1223 IWL_DEBUG_INFO(fwrt, 1224 "WRT: nothing need to be done after debug collection\n"); 1225 } else { 1226 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n", 1227 le32_to_cpu(dump_data.trig->reset_fw)); 1228 } 1229 } 1230 return 0; 1231 } 1232 1233 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1234 { 1235 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1236 int ret, i; 1237 u32 failed_alloc = 0; 1238 1239 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) 1240 return; 1241 1242 IWL_DEBUG_FW(fwrt, 1243 "WRT: Generating active triggers list, domain 0x%x\n", 1244 fwrt->trans->dbg.domains_bitmap); 1245 1246 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1247 struct iwl_dbg_tlv_time_point_data *tp = 1248 &fwrt->trans->dbg.time_point[i]; 1249 1250 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1251 } 1252 1253 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1254 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1255 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1256 &fwrt->trans->dbg.fw_mon_cfg[i]; 1257 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1258 1259 if (dest == IWL_FW_INI_LOCATION_INVALID) { 1260 failed_alloc |= BIT(i); 1261 continue; 1262 } 1263 1264 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1265 *ini_dest = dest; 1266 1267 if (dest != *ini_dest) 1268 continue; 1269 1270 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1271 1272 if (ret) { 1273 IWL_WARN(fwrt, 1274 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1275 i, ret); 1276 failed_alloc |= BIT(i); 1277 } 1278 } 1279 1280 if (!failed_alloc) 1281 return; 1282 1283 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { 1284 struct iwl_fw_ini_region_tlv *reg; 1285 struct iwl_ucode_tlv **active_reg = 1286 &fwrt->trans->dbg.active_regions[i]; 1287 u32 reg_type; 1288 1289 if (!*active_reg) { 1290 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1291 continue; 1292 } 1293 1294 reg = (void *)(*active_reg)->data; 1295 reg_type = reg->type; 1296 1297 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || 1298 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) 1299 continue; 1300 1301 IWL_DEBUG_FW(fwrt, 1302 "WRT: removing allocation id %d from region id %d\n", 1303 le32_to_cpu(reg->dram_alloc_id), i); 1304 1305 failed_alloc &= ~le32_to_cpu(reg->dram_alloc_id); 1306 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1307 1308 kfree(*active_reg); 1309 *active_reg = NULL; 1310 } 1311 } 1312 1313 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1314 enum iwl_fw_ini_time_point tp_id, 1315 union iwl_dbg_tlv_tp_data *tp_data, 1316 bool sync) 1317 { 1318 struct list_head *hcmd_list, *trig_list, *conf_list; 1319 1320 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1321 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1322 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1323 return; 1324 1325 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1326 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1327 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list; 1328 1329 switch (tp_id) { 1330 case IWL_FW_INI_TIME_POINT_EARLY: 1331 iwl_dbg_tlv_init_cfg(fwrt); 1332 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1333 iwl_dbg_tlv_update_drams(fwrt); 1334 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1335 break; 1336 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1337 iwl_dbg_tlv_apply_buffers(fwrt); 1338 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1339 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1340 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1341 break; 1342 case IWL_FW_INI_TIME_POINT_PERIODIC: 1343 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1344 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1345 break; 1346 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1347 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1348 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1349 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1350 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1351 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, 1352 iwl_dbg_tlv_check_fw_pkt); 1353 break; 1354 default: 1355 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1356 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1357 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1358 break; 1359 } 1360 } 1361 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point); 1362