1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2022 Intel Corporation 4 */ 5 #include <linux/firmware.h> 6 #include "iwl-drv.h" 7 #include "iwl-trans.h" 8 #include "iwl-dbg-tlv.h" 9 #include "fw/dbg.h" 10 #include "fw/runtime.h" 11 12 /** 13 * enum iwl_dbg_tlv_type - debug TLV types 14 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 15 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 16 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 17 * @IWL_DBG_TLV_TYPE_REGION: region TLV 18 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 19 * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV 20 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 21 */ 22 enum iwl_dbg_tlv_type { 23 IWL_DBG_TLV_TYPE_DEBUG_INFO = 24 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 25 IWL_DBG_TLV_TYPE_BUF_ALLOC, 26 IWL_DBG_TLV_TYPE_HCMD, 27 IWL_DBG_TLV_TYPE_REGION, 28 IWL_DBG_TLV_TYPE_TRIGGER, 29 IWL_DBG_TLV_TYPE_CONF_SET, 30 IWL_DBG_TLV_TYPE_NUM, 31 }; 32 33 /** 34 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 35 * @min_ver: min version supported 36 * @max_ver: max version supported 37 */ 38 struct iwl_dbg_tlv_ver_data { 39 int min_ver; 40 int max_ver; 41 }; 42 43 /** 44 * struct iwl_dbg_tlv_timer_node - timer node struct 45 * @list: list of &struct iwl_dbg_tlv_timer_node 46 * @timer: timer 47 * @fwrt: &struct iwl_fw_runtime 48 * @tlv: TLV attach to the timer node 49 */ 50 struct iwl_dbg_tlv_timer_node { 51 struct list_head list; 52 struct timer_list timer; 53 struct iwl_fw_runtime *fwrt; 54 struct iwl_ucode_tlv *tlv; 55 }; 56 57 static const struct iwl_dbg_tlv_ver_data 58 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 59 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 60 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 61 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 62 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 3,}, 63 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 64 [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,}, 65 }; 66 67 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv, 68 struct list_head *list) 69 { 70 u32 len = le32_to_cpu(tlv->length); 71 struct iwl_dbg_tlv_node *node; 72 73 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 74 if (!node) 75 return -ENOMEM; 76 77 memcpy(&node->tlv, tlv, sizeof(node->tlv)); 78 memcpy(node->tlv.data, tlv->data, len); 79 list_add_tail(&node->list, list); 80 81 return 0; 82 } 83 84 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv) 85 { 86 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 87 u32 type = le32_to_cpu(tlv->type); 88 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 89 u32 ver = le32_to_cpu(hdr->version); 90 91 if (ver < dbg_ver_table[tlv_idx].min_ver || 92 ver > dbg_ver_table[tlv_idx].max_ver) 93 return false; 94 95 return true; 96 } 97 98 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 99 const struct iwl_ucode_tlv *tlv) 100 { 101 const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data; 102 103 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 104 return -EINVAL; 105 106 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 107 debug_info->debug_cfg_name); 108 109 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 110 } 111 112 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 113 const struct iwl_ucode_tlv *tlv) 114 { 115 const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data; 116 u32 buf_location; 117 u32 alloc_id; 118 119 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 120 return -EINVAL; 121 122 buf_location = le32_to_cpu(alloc->buf_location); 123 alloc_id = le32_to_cpu(alloc->alloc_id); 124 125 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 126 buf_location >= IWL_FW_INI_LOCATION_NUM) 127 goto err; 128 129 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 130 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 131 goto err; 132 133 if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH && 134 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 135 goto err; 136 137 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH && 138 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 139 goto err; 140 141 if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH && 142 alloc->req_size == 0) { 143 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n"); 144 return -EINVAL; 145 } 146 147 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 148 149 return 0; 150 err: 151 IWL_ERR(trans, 152 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 153 alloc_id, buf_location); 154 return -EINVAL; 155 } 156 157 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 158 const struct iwl_ucode_tlv *tlv) 159 { 160 const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data; 161 u32 tp = le32_to_cpu(hcmd->time_point); 162 163 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 164 return -EINVAL; 165 166 /* Host commands can not be sent in early time point since the FW 167 * is not ready 168 */ 169 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 170 tp >= IWL_FW_INI_TIME_POINT_NUM || 171 tp == IWL_FW_INI_TIME_POINT_EARLY) { 172 IWL_ERR(trans, 173 "WRT: Invalid time point %u for host command TLV\n", 174 tp); 175 return -EINVAL; 176 } 177 178 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 179 } 180 181 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 182 const struct iwl_ucode_tlv *tlv) 183 { 184 const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data; 185 struct iwl_ucode_tlv **active_reg; 186 u32 id = le32_to_cpu(reg->id); 187 u8 type = reg->type; 188 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 189 190 /* 191 * The higher part of the ID from version 2 is debug policy. 192 * The id will be only lsb 16 bits, so mask it out. 193 */ 194 if (le32_to_cpu(reg->hdr.version) >= 2) 195 id &= IWL_FW_INI_REGION_ID_MASK; 196 197 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 198 return -EINVAL; 199 200 /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */ 201 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n", 202 IWL_FW_INI_MAX_NAME, reg->name); 203 204 if (id >= IWL_FW_INI_MAX_REGION_ID) { 205 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 206 return -EINVAL; 207 } 208 209 if (type <= IWL_FW_INI_REGION_INVALID || 210 type >= IWL_FW_INI_REGION_NUM) { 211 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 212 return -EINVAL; 213 } 214 215 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 216 !trans->ops->read_config32) { 217 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 218 return -EOPNOTSUPP; 219 } 220 221 if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) { 222 trans->dbg.imr_data.sram_addr = 223 le32_to_cpu(reg->internal_buffer.base_addr); 224 trans->dbg.imr_data.sram_size = 225 le32_to_cpu(reg->internal_buffer.size); 226 } 227 228 229 active_reg = &trans->dbg.active_regions[id]; 230 if (*active_reg) { 231 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 232 233 kfree(*active_reg); 234 } 235 236 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 237 if (!*active_reg) 238 return -ENOMEM; 239 240 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 241 242 return 0; 243 } 244 245 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 246 const struct iwl_ucode_tlv *tlv) 247 { 248 const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data; 249 struct iwl_fw_ini_trigger_tlv *dup_trig; 250 u32 tp = le32_to_cpu(trig->time_point); 251 u32 rf = le32_to_cpu(trig->reset_fw); 252 struct iwl_ucode_tlv *dup = NULL; 253 int ret; 254 255 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 256 return -EINVAL; 257 258 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 259 tp >= IWL_FW_INI_TIME_POINT_NUM) { 260 IWL_ERR(trans, 261 "WRT: Invalid time point %u for trigger TLV\n", 262 tp); 263 return -EINVAL; 264 } 265 266 IWL_DEBUG_FW(trans, 267 "WRT: time point %u for trigger TLV with reset_fw %u\n", 268 tp, rf); 269 trans->dbg.last_tp_resetfw = 0xFF; 270 if (!le32_to_cpu(trig->occurrences)) { 271 dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length), 272 GFP_KERNEL); 273 if (!dup) 274 return -ENOMEM; 275 dup_trig = (void *)dup->data; 276 dup_trig->occurrences = cpu_to_le32(-1); 277 tlv = dup; 278 } 279 280 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 281 kfree(dup); 282 283 return ret; 284 } 285 286 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans, 287 const struct iwl_ucode_tlv *tlv) 288 { 289 const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data; 290 u32 tp = le32_to_cpu(conf_set->time_point); 291 u32 type = le32_to_cpu(conf_set->set_type); 292 293 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 294 tp >= IWL_FW_INI_TIME_POINT_NUM) { 295 IWL_DEBUG_FW(trans, 296 "WRT: Invalid time point %u for config set TLV\n", tp); 297 return -EINVAL; 298 } 299 300 if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID || 301 type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) { 302 IWL_DEBUG_FW(trans, 303 "WRT: Invalid config set type %u for config set TLV\n", type); 304 return -EINVAL; 305 } 306 307 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list); 308 } 309 310 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 311 const struct iwl_ucode_tlv *tlv) = { 312 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 313 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 314 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 315 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 316 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 317 [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set, 318 }; 319 320 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv, 321 bool ext) 322 { 323 enum iwl_ini_cfg_state *cfg_state = ext ? 324 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 325 const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0]; 326 u32 type; 327 u32 tlv_idx; 328 u32 domain; 329 int ret; 330 331 if (le32_to_cpu(tlv->length) < sizeof(*hdr)) 332 return; 333 334 type = le32_to_cpu(tlv->type); 335 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 336 domain = le32_to_cpu(hdr->domain); 337 338 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 339 !(domain & trans->dbg.domains_bitmap)) { 340 IWL_DEBUG_FW(trans, 341 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 342 domain, trans->dbg.domains_bitmap); 343 return; 344 } 345 346 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 347 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 348 goto out_err; 349 } 350 351 if (!iwl_dbg_tlv_ver_support(tlv)) { 352 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 353 le32_to_cpu(hdr->version)); 354 goto out_err; 355 } 356 357 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 358 if (ret) { 359 IWL_WARN(trans, 360 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 361 type, ret, ext); 362 goto out_err; 363 } 364 365 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 366 *cfg_state = IWL_INI_CFG_STATE_LOADED; 367 368 return; 369 370 out_err: 371 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 372 } 373 374 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 375 { 376 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 377 struct iwl_dbg_tlv_timer_node *node, *tmp; 378 379 list_for_each_entry_safe(node, tmp, timer_list, list) { 380 timer_shutdown_sync(&node->timer); 381 list_del(&node->list); 382 kfree(node); 383 } 384 } 385 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 386 387 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 388 enum iwl_fw_ini_allocation_id alloc_id) 389 { 390 struct iwl_fw_mon *fw_mon; 391 int i; 392 393 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 394 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 395 return; 396 397 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 398 399 for (i = 0; i < fw_mon->num_frags; i++) { 400 struct iwl_dram_data *frag = &fw_mon->frags[i]; 401 402 dma_free_coherent(trans->dev, frag->size, frag->block, 403 frag->physical); 404 405 frag->physical = 0; 406 frag->block = NULL; 407 frag->size = 0; 408 } 409 410 kfree(fw_mon->frags); 411 fw_mon->frags = NULL; 412 fw_mon->num_frags = 0; 413 } 414 415 void iwl_dbg_tlv_free(struct iwl_trans *trans) 416 { 417 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 418 int i; 419 420 iwl_dbg_tlv_del_timers(trans); 421 422 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 423 struct iwl_ucode_tlv **active_reg = 424 &trans->dbg.active_regions[i]; 425 426 kfree(*active_reg); 427 *active_reg = NULL; 428 } 429 430 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 431 &trans->dbg.debug_info_tlv_list, list) { 432 list_del(&tlv_node->list); 433 kfree(tlv_node); 434 } 435 436 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 437 struct iwl_dbg_tlv_time_point_data *tp = 438 &trans->dbg.time_point[i]; 439 440 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 441 list) { 442 list_del(&tlv_node->list); 443 kfree(tlv_node); 444 } 445 446 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 447 list) { 448 list_del(&tlv_node->list); 449 kfree(tlv_node); 450 } 451 452 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 453 &tp->active_trig_list, list) { 454 list_del(&tlv_node->list); 455 kfree(tlv_node); 456 } 457 458 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 459 &tp->config_list, list) { 460 list_del(&tlv_node->list); 461 kfree(tlv_node); 462 } 463 464 } 465 466 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 467 iwl_dbg_tlv_fragments_free(trans, i); 468 } 469 470 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 471 size_t len) 472 { 473 const struct iwl_ucode_tlv *tlv; 474 u32 tlv_len; 475 476 while (len >= sizeof(*tlv)) { 477 len -= sizeof(*tlv); 478 tlv = (const void *)data; 479 480 tlv_len = le32_to_cpu(tlv->length); 481 482 if (len < tlv_len) { 483 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 484 len, tlv_len); 485 return -EINVAL; 486 } 487 len -= ALIGN(tlv_len, 4); 488 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 489 490 iwl_dbg_tlv_alloc(trans, tlv, true); 491 } 492 493 return 0; 494 } 495 496 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 497 { 498 const struct firmware *fw; 499 const char *yoyo_bin = "iwl-debug-yoyo.bin"; 500 int res; 501 502 if (!iwlwifi_mod_params.enable_ini || 503 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000) 504 return; 505 506 res = firmware_request_nowarn(&fw, yoyo_bin, dev); 507 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin); 508 509 if (res) 510 return; 511 512 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 513 514 release_firmware(fw); 515 } 516 517 void iwl_dbg_tlv_init(struct iwl_trans *trans) 518 { 519 int i; 520 521 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 522 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 523 524 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 525 struct iwl_dbg_tlv_time_point_data *tp = 526 &trans->dbg.time_point[i]; 527 528 INIT_LIST_HEAD(&tp->trig_list); 529 INIT_LIST_HEAD(&tp->hcmd_list); 530 INIT_LIST_HEAD(&tp->active_trig_list); 531 INIT_LIST_HEAD(&tp->config_list); 532 } 533 } 534 535 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 536 struct iwl_dram_data *frag, u32 pages) 537 { 538 void *block = NULL; 539 dma_addr_t physical; 540 541 if (!frag || frag->size || !pages) 542 return -EIO; 543 544 /* 545 * We try to allocate as many pages as we can, starting with 546 * the requested amount and going down until we can allocate 547 * something. Because of DIV_ROUND_UP(), pages will never go 548 * down to 0 and stop the loop, so stop when pages reaches 1, 549 * which is too small anyway. 550 */ 551 while (pages > 1) { 552 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 553 &physical, 554 GFP_KERNEL | __GFP_NOWARN); 555 if (block) 556 break; 557 558 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 559 pages * PAGE_SIZE); 560 561 pages = DIV_ROUND_UP(pages, 2); 562 } 563 564 if (!block) 565 return -ENOMEM; 566 567 frag->physical = physical; 568 frag->block = block; 569 frag->size = pages * PAGE_SIZE; 570 571 return pages; 572 } 573 574 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 575 enum iwl_fw_ini_allocation_id alloc_id) 576 { 577 struct iwl_fw_mon *fw_mon; 578 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 579 u32 num_frags, remain_pages, frag_pages; 580 int i; 581 582 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 583 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 584 return -EIO; 585 586 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 587 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 588 589 if (fw_mon->num_frags || 590 fw_mon_cfg->buf_location != 591 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 592 return 0; 593 594 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 595 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 596 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 597 return -EIO; 598 num_frags = 1; 599 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ && 600 alloc_id > IWL_FW_INI_ALLOCATION_ID_DBGC3) { 601 return -EIO; 602 } 603 604 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 605 PAGE_SIZE); 606 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 607 num_frags = min_t(u32, num_frags, remain_pages); 608 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 609 610 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 611 if (!fw_mon->frags) 612 return -ENOMEM; 613 614 for (i = 0; i < num_frags; i++) { 615 int pages = min_t(u32, frag_pages, remain_pages); 616 617 IWL_DEBUG_FW(fwrt, 618 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 619 alloc_id, i, pages * PAGE_SIZE); 620 621 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 622 pages); 623 if (pages < 0) { 624 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 625 (remain_pages * PAGE_SIZE); 626 627 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 628 iwl_dbg_tlv_fragments_free(fwrt->trans, 629 alloc_id); 630 return pages; 631 } 632 break; 633 } 634 635 remain_pages -= pages; 636 fw_mon->num_frags++; 637 } 638 639 return 0; 640 } 641 642 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 643 enum iwl_fw_ini_allocation_id alloc_id) 644 { 645 struct iwl_fw_mon *fw_mon; 646 u32 remain_frags, num_commands; 647 int i, fw_mon_idx = 0; 648 649 if (!fw_has_capa(&fwrt->fw->ucode_capa, 650 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 651 return 0; 652 653 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 654 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 655 return -EIO; 656 657 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 658 IWL_FW_INI_LOCATION_DRAM_PATH) 659 return 0; 660 661 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 662 663 /* the first fragment of DBGC1 is given to the FW via register 664 * or context info 665 */ 666 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 667 fw_mon_idx++; 668 669 remain_frags = fw_mon->num_frags - fw_mon_idx; 670 if (!remain_frags) 671 return 0; 672 673 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 674 675 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 676 alloc_id); 677 678 for (i = 0; i < num_commands; i++) { 679 u32 num_frags = min_t(u32, remain_frags, 680 BUF_ALLOC_MAX_NUM_FRAGS); 681 struct iwl_buf_alloc_cmd data = { 682 .alloc_id = cpu_to_le32(alloc_id), 683 .num_frags = cpu_to_le32(num_frags), 684 .buf_location = 685 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 686 }; 687 struct iwl_host_cmd hcmd = { 688 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 689 .data[0] = &data, 690 .len[0] = sizeof(data), 691 .flags = CMD_SEND_IN_RFKILL, 692 }; 693 int ret, j; 694 695 for (j = 0; j < num_frags; j++) { 696 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 697 struct iwl_dram_data *fw_mon_frag = 698 &fw_mon->frags[fw_mon_idx++]; 699 700 frag->addr = cpu_to_le64(fw_mon_frag->physical); 701 frag->size = cpu_to_le32(fw_mon_frag->size); 702 } 703 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 704 if (ret) 705 return ret; 706 707 remain_frags -= num_frags; 708 } 709 710 return 0; 711 } 712 713 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 714 { 715 int ret, i; 716 717 if (fw_has_capa(&fwrt->fw->ucode_capa, 718 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 719 return; 720 721 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 722 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 723 if (ret) 724 IWL_WARN(fwrt, 725 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 726 i, ret); 727 } 728 } 729 730 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt, 731 enum iwl_fw_ini_allocation_id alloc_id, 732 struct iwl_dram_info *dram_info) 733 { 734 struct iwl_fw_mon *fw_mon; 735 u32 remain_frags, num_frags; 736 int j, fw_mon_idx = 0; 737 struct iwl_buf_alloc_cmd *data; 738 739 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 740 IWL_FW_INI_LOCATION_DRAM_PATH) { 741 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n", 742 alloc_id); 743 return -1; 744 } 745 746 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 747 748 /* the first fragment of DBGC1 is given to the FW via register 749 * or context info 750 */ 751 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 752 fw_mon_idx++; 753 754 remain_frags = fw_mon->num_frags - fw_mon_idx; 755 if (!remain_frags) 756 return -1; 757 758 num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 759 data = &dram_info->dram_frags[alloc_id - 1]; 760 data->alloc_id = cpu_to_le32(alloc_id); 761 data->num_frags = cpu_to_le32(num_frags); 762 data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH); 763 764 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n", 765 cpu_to_le32(alloc_id), cpu_to_le32(num_frags)); 766 767 for (j = 0; j < num_frags; j++) { 768 struct iwl_buf_alloc_frag *frag = &data->frags[j]; 769 struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++]; 770 771 frag->addr = cpu_to_le64(fw_mon_frag->physical); 772 frag->size = cpu_to_le32(fw_mon_frag->size); 773 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n"); 774 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n", 775 j, cpu_to_le64(fw_mon_frag->physical), 776 cpu_to_le32(fw_mon_frag->size)); 777 } 778 return 0; 779 } 780 781 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt) 782 { 783 int ret, i; 784 bool dram_alloc = false; 785 struct iwl_dram_data *frags = 786 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0]; 787 struct iwl_dram_info *dram_info; 788 789 if (!frags || !frags->block) 790 return; 791 792 dram_info = frags->block; 793 794 if (!fw_has_capa(&fwrt->fw->ucode_capa, 795 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT)) 796 return; 797 798 dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD); 799 dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD); 800 801 for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1; 802 i < IWL_FW_INI_ALLOCATION_NUM; i++) { 803 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location == 804 IWL_FW_INI_LOCATION_INVALID) 805 continue; 806 807 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info); 808 if (!ret) 809 dram_alloc = true; 810 else 811 IWL_INFO(fwrt, 812 "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n", 813 i, ret); 814 } 815 816 if (dram_alloc) 817 IWL_DEBUG_FW(fwrt, "block data after %08x\n", 818 dram_info->first_word); 819 else 820 memset(frags->block, 0, sizeof(*dram_info)); 821 } 822 823 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 824 struct list_head *hcmd_list) 825 { 826 struct iwl_dbg_tlv_node *node; 827 828 list_for_each_entry(node, hcmd_list, list) { 829 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 830 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 831 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 832 struct iwl_host_cmd cmd = { 833 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 834 .len = { hcmd_len, }, 835 .data = { hcmd_data->data, }, 836 }; 837 838 iwl_trans_send_cmd(fwrt->trans, &cmd); 839 } 840 } 841 842 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt, 843 struct list_head *conf_list) 844 { 845 struct iwl_dbg_tlv_node *node; 846 847 list_for_each_entry(node, conf_list, list) { 848 struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data; 849 u32 count, address, value; 850 u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8; 851 u32 type = le32_to_cpu(config_list->set_type); 852 u32 offset = le32_to_cpu(config_list->addr_offset); 853 854 switch (type) { 855 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: { 856 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 857 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n"); 858 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n"); 859 continue; 860 } 861 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len); 862 for (count = 0; count < len; count++) { 863 address = le32_to_cpu(config_list->addr_val[count].address); 864 value = le32_to_cpu(config_list->addr_val[count].value); 865 iwl_trans_write_prph(fwrt->trans, address + offset, value); 866 } 867 iwl_trans_release_nic_access(fwrt->trans); 868 break; 869 } 870 case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: { 871 for (count = 0; count < len; count++) { 872 address = le32_to_cpu(config_list->addr_val[count].address); 873 value = le32_to_cpu(config_list->addr_val[count].value); 874 iwl_trans_write_mem32(fwrt->trans, address + offset, value); 875 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n", 876 count, address, value); 877 } 878 break; 879 } 880 case IWL_FW_INI_CONFIG_SET_TYPE_CSR: { 881 for (count = 0; count < len; count++) { 882 address = le32_to_cpu(config_list->addr_val[count].address); 883 value = le32_to_cpu(config_list->addr_val[count].value); 884 iwl_write32(fwrt->trans, address + offset, value); 885 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n", 886 count, address, value); 887 } 888 break; 889 } 890 case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: { 891 struct iwl_dbgc1_info dram_info = {}; 892 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0]; 893 __le64 dram_base_addr; 894 __le32 dram_size; 895 u64 dram_addr; 896 u32 ret; 897 898 if (!frags) 899 break; 900 901 dram_base_addr = cpu_to_le64(frags->physical); 902 dram_size = cpu_to_le32(frags->size); 903 dram_addr = le64_to_cpu(dram_base_addr); 904 905 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n", 906 dram_base_addr, dram_size); 907 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n", 908 le32_to_cpu(config_list->addr_offset)); 909 for (count = 0; count < len; count++) { 910 address = le32_to_cpu(config_list->addr_val[count].address); 911 dram_info.dbgc1_add_lsb = 912 cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400); 913 dram_info.dbgc1_add_msb = 914 cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32); 915 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400); 916 ret = iwl_trans_write_mem(fwrt->trans, 917 address + offset, &dram_info, 4); 918 if (ret) { 919 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n"); 920 break; 921 } 922 } 923 break; 924 } 925 case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: { 926 u32 debug_token_config = 927 le32_to_cpu(config_list->addr_val[0].value); 928 929 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n", 930 debug_token_config); 931 fwrt->trans->dbg.ucode_preset = debug_token_config; 932 break; 933 } 934 default: 935 break; 936 } 937 } 938 } 939 940 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 941 { 942 struct iwl_dbg_tlv_timer_node *timer_node = 943 from_timer(timer_node, t, timer); 944 struct iwl_fwrt_dump_data dump_data = { 945 .trig = (void *)timer_node->tlv->data, 946 }; 947 int ret; 948 949 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false); 950 if (!ret || ret == -EBUSY) { 951 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 952 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 953 954 if (!occur) 955 return; 956 957 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 958 } 959 } 960 961 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 962 { 963 struct iwl_dbg_tlv_node *node; 964 struct list_head *trig_list = 965 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 966 967 list_for_each_entry(node, trig_list, list) { 968 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 969 struct iwl_dbg_tlv_timer_node *timer_node; 970 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 971 u32 min_interval = 100; 972 973 if (!occur) 974 continue; 975 976 /* make sure there is at least one dword of data for the 977 * interval value 978 */ 979 if (le32_to_cpu(node->tlv.length) < 980 sizeof(*trig) + sizeof(__le32)) { 981 IWL_ERR(fwrt, 982 "WRT: Invalid periodic trigger data was not given\n"); 983 continue; 984 } 985 986 if (le32_to_cpu(trig->data[0]) < min_interval) { 987 IWL_WARN(fwrt, 988 "WRT: Override min interval from %u to %u msec\n", 989 le32_to_cpu(trig->data[0]), min_interval); 990 trig->data[0] = cpu_to_le32(min_interval); 991 } 992 993 collect_interval = le32_to_cpu(trig->data[0]); 994 995 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 996 if (!timer_node) { 997 IWL_ERR(fwrt, 998 "WRT: Failed to allocate periodic trigger\n"); 999 continue; 1000 } 1001 1002 timer_node->fwrt = fwrt; 1003 timer_node->tlv = &node->tlv; 1004 timer_setup(&timer_node->timer, 1005 iwl_dbg_tlv_periodic_trig_handler, 0); 1006 1007 list_add_tail(&timer_node->list, 1008 &fwrt->trans->dbg.periodic_trig_list); 1009 1010 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 1011 1012 mod_timer(&timer_node->timer, 1013 jiffies + msecs_to_jiffies(collect_interval)); 1014 } 1015 } 1016 1017 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new, 1018 const struct iwl_ucode_tlv *old) 1019 { 1020 const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data; 1021 const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data; 1022 const __le32 *new_data = new_trig->data, *old_data = old_trig->data; 1023 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 1024 u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data); 1025 int i, j; 1026 1027 for (i = 0; i < new_dwords_num; i++) { 1028 bool match = false; 1029 1030 for (j = 0; j < old_dwords_num; j++) { 1031 if (new_data[i] == old_data[j]) { 1032 match = true; 1033 break; 1034 } 1035 } 1036 if (!match) 1037 return false; 1038 } 1039 1040 return true; 1041 } 1042 1043 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 1044 struct iwl_ucode_tlv *trig_tlv, 1045 struct iwl_dbg_tlv_node *node) 1046 { 1047 struct iwl_ucode_tlv *node_tlv = &node->tlv; 1048 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 1049 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1050 u32 policy = le32_to_cpu(trig->apply_policy); 1051 u32 size = le32_to_cpu(trig_tlv->length); 1052 u32 trig_data_len = size - sizeof(*trig); 1053 u32 offset = 0; 1054 1055 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 1056 u32 data_len = le32_to_cpu(node_tlv->length) - 1057 sizeof(*node_trig); 1058 1059 IWL_DEBUG_FW(fwrt, 1060 "WRT: Appending trigger data (time point %u)\n", 1061 le32_to_cpu(trig->time_point)); 1062 1063 offset += data_len; 1064 size += data_len; 1065 } else { 1066 IWL_DEBUG_FW(fwrt, 1067 "WRT: Overriding trigger data (time point %u)\n", 1068 le32_to_cpu(trig->time_point)); 1069 } 1070 1071 if (size != le32_to_cpu(node_tlv->length)) { 1072 struct list_head *prev = node->list.prev; 1073 struct iwl_dbg_tlv_node *tmp; 1074 1075 list_del(&node->list); 1076 1077 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 1078 if (!tmp) { 1079 IWL_WARN(fwrt, 1080 "WRT: No memory to override trigger (time point %u)\n", 1081 le32_to_cpu(trig->time_point)); 1082 1083 list_add(&node->list, prev); 1084 1085 return -ENOMEM; 1086 } 1087 1088 list_add(&tmp->list, prev); 1089 node_tlv = &tmp->tlv; 1090 node_trig = (void *)node_tlv->data; 1091 } 1092 1093 memcpy(node_trig->data + offset, trig->data, trig_data_len); 1094 node_tlv->length = cpu_to_le32(size); 1095 1096 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 1097 IWL_DEBUG_FW(fwrt, 1098 "WRT: Overriding trigger configuration (time point %u)\n", 1099 le32_to_cpu(trig->time_point)); 1100 1101 /* the first 11 dwords are configuration related */ 1102 memcpy(node_trig, trig, sizeof(__le32) * 11); 1103 } 1104 1105 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 1106 IWL_DEBUG_FW(fwrt, 1107 "WRT: Overriding trigger regions (time point %u)\n", 1108 le32_to_cpu(trig->time_point)); 1109 1110 node_trig->regions_mask = trig->regions_mask; 1111 } else { 1112 IWL_DEBUG_FW(fwrt, 1113 "WRT: Appending trigger regions (time point %u)\n", 1114 le32_to_cpu(trig->time_point)); 1115 1116 node_trig->regions_mask |= trig->regions_mask; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static int 1123 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 1124 struct list_head *trig_list, 1125 struct iwl_ucode_tlv *trig_tlv) 1126 { 1127 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 1128 struct iwl_dbg_tlv_node *node, *match = NULL; 1129 u32 policy = le32_to_cpu(trig->apply_policy); 1130 1131 list_for_each_entry(node, trig_list, list) { 1132 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 1133 break; 1134 1135 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 1136 is_trig_data_contained(trig_tlv, &node->tlv)) { 1137 match = node; 1138 break; 1139 } 1140 } 1141 1142 if (!match) { 1143 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 1144 le32_to_cpu(trig->time_point)); 1145 return iwl_dbg_tlv_add(trig_tlv, trig_list); 1146 } 1147 1148 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 1149 } 1150 1151 static void 1152 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 1153 struct iwl_dbg_tlv_time_point_data *tp) 1154 { 1155 struct iwl_dbg_tlv_node *node; 1156 struct list_head *trig_list = &tp->trig_list; 1157 struct list_head *active_trig_list = &tp->active_trig_list; 1158 1159 list_for_each_entry(node, trig_list, list) { 1160 struct iwl_ucode_tlv *tlv = &node->tlv; 1161 1162 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 1163 } 1164 } 1165 1166 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 1167 struct iwl_fwrt_dump_data *dump_data, 1168 union iwl_dbg_tlv_tp_data *tp_data, 1169 u32 trig_data) 1170 { 1171 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 1172 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 1173 1174 if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd && 1175 pkt->hdr.group_id == wanted_hdr->group_id)) { 1176 struct iwl_rx_packet *fw_pkt = 1177 kmemdup(pkt, 1178 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 1179 GFP_ATOMIC); 1180 1181 if (!fw_pkt) 1182 return false; 1183 1184 dump_data->fw_pkt = fw_pkt; 1185 1186 return true; 1187 } 1188 1189 return false; 1190 } 1191 1192 static int 1193 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync, 1194 struct list_head *active_trig_list, 1195 union iwl_dbg_tlv_tp_data *tp_data, 1196 bool (*data_check)(struct iwl_fw_runtime *fwrt, 1197 struct iwl_fwrt_dump_data *dump_data, 1198 union iwl_dbg_tlv_tp_data *tp_data, 1199 u32 trig_data)) 1200 { 1201 struct iwl_dbg_tlv_node *node; 1202 1203 list_for_each_entry(node, active_trig_list, list) { 1204 struct iwl_fwrt_dump_data dump_data = { 1205 .trig = (void *)node->tlv.data, 1206 }; 1207 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 1208 data); 1209 int ret, i; 1210 u32 tp = le32_to_cpu(dump_data.trig->time_point); 1211 1212 1213 if (!num_data) { 1214 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1215 if (ret) 1216 return ret; 1217 } 1218 1219 for (i = 0; i < num_data; i++) { 1220 if (!data_check || 1221 data_check(fwrt, &dump_data, tp_data, 1222 le32_to_cpu(dump_data.trig->data[i]))) { 1223 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync); 1224 if (ret) 1225 return ret; 1226 1227 break; 1228 } 1229 } 1230 1231 fwrt->trans->dbg.restart_required = FALSE; 1232 IWL_DEBUG_FW(fwrt, "WRT: tp %d, reset_fw %d\n", 1233 tp, dump_data.trig->reset_fw); 1234 IWL_DEBUG_FW(fwrt, 1235 "WRT: restart_required %d, last_tp_resetfw %d\n", 1236 fwrt->trans->dbg.restart_required, 1237 fwrt->trans->dbg.last_tp_resetfw); 1238 1239 if (fwrt->trans->trans_cfg->device_family == 1240 IWL_DEVICE_FAMILY_9000) { 1241 fwrt->trans->dbg.restart_required = TRUE; 1242 } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT && 1243 fwrt->trans->dbg.last_tp_resetfw == 1244 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1245 fwrt->trans->dbg.restart_required = FALSE; 1246 fwrt->trans->dbg.last_tp_resetfw = 0xFF; 1247 IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n"); 1248 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1249 IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) { 1250 IWL_DEBUG_FW(fwrt, "WRT: stop and reload firmware\n"); 1251 fwrt->trans->dbg.restart_required = TRUE; 1252 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1253 IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) { 1254 IWL_DEBUG_FW(fwrt, 1255 "WRT: stop only and no reload firmware\n"); 1256 fwrt->trans->dbg.restart_required = FALSE; 1257 fwrt->trans->dbg.last_tp_resetfw = 1258 le32_to_cpu(dump_data.trig->reset_fw); 1259 } else if (le32_to_cpu(dump_data.trig->reset_fw) == 1260 IWL_FW_INI_RESET_FW_MODE_NOTHING) { 1261 IWL_DEBUG_FW(fwrt, 1262 "WRT: nothing need to be done after debug collection\n"); 1263 } else { 1264 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n", 1265 le32_to_cpu(dump_data.trig->reset_fw)); 1266 } 1267 } 1268 return 0; 1269 } 1270 1271 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 1272 { 1273 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1274 int ret, i; 1275 u32 failed_alloc = 0; 1276 1277 if (*ini_dest != IWL_FW_INI_LOCATION_INVALID) 1278 return; 1279 1280 IWL_DEBUG_FW(fwrt, 1281 "WRT: Generating active triggers list, domain 0x%x\n", 1282 fwrt->trans->dbg.domains_bitmap); 1283 1284 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1285 struct iwl_dbg_tlv_time_point_data *tp = 1286 &fwrt->trans->dbg.time_point[i]; 1287 1288 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1289 } 1290 1291 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1292 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1293 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1294 &fwrt->trans->dbg.fw_mon_cfg[i]; 1295 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1296 1297 if (dest == IWL_FW_INI_LOCATION_INVALID) { 1298 failed_alloc |= BIT(i); 1299 continue; 1300 } 1301 1302 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1303 *ini_dest = dest; 1304 1305 if (dest != *ini_dest) 1306 continue; 1307 1308 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1309 1310 if (ret) { 1311 IWL_WARN(fwrt, 1312 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1313 i, ret); 1314 failed_alloc |= BIT(i); 1315 } 1316 } 1317 1318 if (!failed_alloc) 1319 return; 1320 1321 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) { 1322 struct iwl_fw_ini_region_tlv *reg; 1323 struct iwl_ucode_tlv **active_reg = 1324 &fwrt->trans->dbg.active_regions[i]; 1325 u32 reg_type; 1326 1327 if (!*active_reg) { 1328 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1329 continue; 1330 } 1331 1332 reg = (void *)(*active_reg)->data; 1333 reg_type = reg->type; 1334 1335 if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER || 1336 !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc)) 1337 continue; 1338 1339 IWL_DEBUG_FW(fwrt, 1340 "WRT: removing allocation id %d from region id %d\n", 1341 le32_to_cpu(reg->dram_alloc_id), i); 1342 1343 failed_alloc &= ~BIT(le32_to_cpu(reg->dram_alloc_id)); 1344 fwrt->trans->dbg.unsupported_region_msk |= BIT(i); 1345 1346 kfree(*active_reg); 1347 *active_reg = NULL; 1348 } 1349 } 1350 1351 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1352 enum iwl_fw_ini_time_point tp_id, 1353 union iwl_dbg_tlv_tp_data *tp_data, 1354 bool sync) 1355 { 1356 struct list_head *hcmd_list, *trig_list, *conf_list; 1357 1358 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1359 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1360 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1361 return; 1362 1363 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1364 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1365 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list; 1366 1367 switch (tp_id) { 1368 case IWL_FW_INI_TIME_POINT_EARLY: 1369 iwl_dbg_tlv_init_cfg(fwrt); 1370 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1371 iwl_dbg_tlv_update_drams(fwrt); 1372 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1373 break; 1374 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1375 iwl_dbg_tlv_apply_buffers(fwrt); 1376 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1377 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1378 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1379 break; 1380 case IWL_FW_INI_TIME_POINT_PERIODIC: 1381 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1382 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1383 break; 1384 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1385 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1386 case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION: 1387 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1388 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1389 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, 1390 iwl_dbg_tlv_check_fw_pkt); 1391 break; 1392 default: 1393 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1394 iwl_dbg_tlv_apply_config(fwrt, conf_list); 1395 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL); 1396 break; 1397 } 1398 } 1399 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point); 1400