1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3  * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4  * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5  * Copyright (C) 2016 Intel Deutschland GmbH
6  */
7 #ifndef __iwl_csr_h__
8 #define __iwl_csr_h__
9 /*
10  * CSR (control and status registers)
11  *
12  * CSR registers are mapped directly into PCI bus space, and are accessible
13  * whenever platform supplies power to device, even when device is in
14  * low power states due to driver-invoked device resets
15  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
16  *
17  * Use iwl_write32() and iwl_read32() family to access these registers;
18  * these provide simple PCI bus access, without waking up the MAC.
19  * Do not use iwl_write_direct32() family for these registers;
20  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
21  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
22  * the CSR registers.
23  *
24  * NOTE:  Device does need to be awake in order to read this memory
25  *        via CSR_EEPROM and CSR_OTP registers
26  */
27 #define CSR_BASE    (0x000)
28 
29 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
30 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
31 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
32 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
33 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
34 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
35 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
36 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
37 #define CSR_FUNC_SCRATCH        (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
38 
39 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
40 #define CSR_INT_PERIODIC_REG	(CSR_BASE+0x005)
41 
42 /*
43  * Hardware revision info
44  * Bit fields:
45  * 31-16:  Reserved
46  *  15-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
47  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
48  *  1-0:  "Dash" (-) value, as in A-1, etc.
49  */
50 #define CSR_HW_REV              (CSR_BASE+0x028)
51 
52 /*
53  * RF ID revision info
54  * Bit fields:
55  * 31:24: Reserved (set to 0x0)
56  * 23:12: Type
57  * 11:8:  Step (A - 0x0, B - 0x1, etc)
58  * 7:4:   Dash
59  * 3:0:   Flavor
60  */
61 #define CSR_HW_RF_ID		(CSR_BASE+0x09c)
62 
63 /*
64  * EEPROM and OTP (one-time-programmable) memory reads
65  *
66  * NOTE:  Device must be awake, initialized via apm_ops.init(),
67  *        in order to read.
68  */
69 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
70 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
71 #define CSR_OTP_GP_REG   	(CSR_BASE+0x034)
72 
73 #define CSR_GIO_REG		(CSR_BASE+0x03C)
74 #define CSR_GP_UCODE_REG	(CSR_BASE+0x048)
75 #define CSR_GP_DRIVER_REG	(CSR_BASE+0x050)
76 
77 /*
78  * UCODE-DRIVER GP (general purpose) mailbox registers.
79  * SET/CLR registers set/clear bit(s) if "1" is written.
80  */
81 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
82 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
83 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
84 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
85 
86 #define CSR_MBOX_SET_REG	(CSR_BASE + 0x88)
87 
88 #define CSR_LED_REG             (CSR_BASE+0x094)
89 #define CSR_DRAM_INT_TBL_REG	(CSR_BASE+0x0A0)
90 #define CSR_MAC_SHADOW_REG_CTRL		(CSR_BASE + 0x0A8) /* 6000 and up */
91 #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE	BIT(20)
92 #define CSR_MAC_SHADOW_REG_CTL2		(CSR_BASE + 0x0AC)
93 #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE	0xFFFF
94 
95 /* LTR control (since IWL_DEVICE_FAMILY_22000) */
96 #define CSR_LTR_LONG_VAL_AD			(CSR_BASE + 0x0D4)
97 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ	0x80000000
98 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE	0x1c000000
99 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL	0x03ff0000
100 #define CSR_LTR_LONG_VAL_AD_SNOOP_REQ		0x00008000
101 #define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE		0x00001c00
102 #define CSR_LTR_LONG_VAL_AD_SNOOP_VAL		0x000003ff
103 #define CSR_LTR_LONG_VAL_AD_SCALE_USEC		2
104 
105 /* GIO Chicken Bits (PCI Express bus link power management) */
106 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
107 
108 /* Doorbell NMI (since Bz) */
109 #define CSR_DOORBELL_VECTOR	(CSR_BASE + 0x130)
110 #define CSR_DOORBELL_VECTOR_NMI	BIT(1)
111 
112 /* host chicken bits */
113 #define CSR_HOST_CHICKEN	(CSR_BASE + 0x204)
114 #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME	BIT(19)
115 
116 /* Analog phase-lock-loop configuration  */
117 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
118 
119 /*
120  * CSR HW resources monitor registers
121  */
122 #define CSR_MONITOR_CFG_REG		(CSR_BASE+0x214)
123 #define CSR_MONITOR_STATUS_REG		(CSR_BASE+0x228)
124 #define CSR_MONITOR_XTAL_RESOURCES	(0x00000010)
125 
126 /*
127  * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
128  * "step" determines CCK backoff for txpower calculation.
129  * See also CSR_HW_REV register.
130  * Bit fields:
131  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
132  *  1-0:  "Dash" (-) value, as in C-1, etc.
133  */
134 #define CSR_HW_REV_WA_REG		(CSR_BASE+0x22C)
135 
136 #define CSR_DBG_HPET_MEM_REG		(CSR_BASE+0x240)
137 #define CSR_DBG_LINK_PWR_MGMT_REG	(CSR_BASE+0x250)
138 
139 /*
140  * Scratch register initial configuration - this is set on init, and read
141  * during a error FW error.
142  */
143 #define CSR_FUNC_SCRATCH_INIT_VALUE		(0x01010101)
144 
145 /* Bits for CSR_HW_IF_CONFIG_REG */
146 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH	(0x00000003)
147 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP	(0x0000000C)
148 #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM	(0x00000080)
149 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER	(0x000000C0)
150 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI		(0x00000100)
151 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI	(0x00000200)
152 #define CSR_HW_IF_CONFIG_REG_D3_DEBUG		(0x00000200)
153 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE	(0x00000C00)
154 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH	(0x00003000)
155 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP	(0x0000C000)
156 
157 #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH	(0)
158 #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP	(2)
159 #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER	(6)
160 #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE	(10)
161 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH	(12)
162 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP	(14)
163 
164 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A	(0x00080000)
165 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM	(0x00200000)
166 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY	(0x00400000) /* PCI_OWN_SEM */
167 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
168 #define CSR_HW_IF_CONFIG_REG_PREPARE		  (0x08000000) /* WAKE_ME */
169 #define CSR_HW_IF_CONFIG_REG_ENABLE_PME		  (0x10000000)
170 #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE	  (0x40000000) /* PERSISTENCE */
171 
172 #define CSR_MBOX_SET_REG_OS_ALIVE		BIT(5)
173 
174 #define CSR_INT_PERIODIC_DIS			(0x00) /* disable periodic int*/
175 #define CSR_INT_PERIODIC_ENA			(0xFF) /* 255*32 usec ~ 8 msec*/
176 
177 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
178  * acknowledged (reset) by host writing "1" to flagged bits. */
179 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
180 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
181 #define CSR_INT_BIT_RX_PERIODIC	 (1 << 28) /* Rx periodic */
182 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
183 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
184 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
185 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
186 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
187 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses */
188 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
189 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
190 
191 #define CSR_INI_SET_MASK	(CSR_INT_BIT_FH_RX   | \
192 				 CSR_INT_BIT_HW_ERR  | \
193 				 CSR_INT_BIT_FH_TX   | \
194 				 CSR_INT_BIT_SW_ERR  | \
195 				 CSR_INT_BIT_RF_KILL | \
196 				 CSR_INT_BIT_SW_RX   | \
197 				 CSR_INT_BIT_WAKEUP  | \
198 				 CSR_INT_BIT_ALIVE   | \
199 				 CSR_INT_BIT_RX_PERIODIC)
200 
201 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
202 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
203 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
204 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
205 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
206 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
207 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
208 
209 #define CSR_FH_INT_RX_MASK	(CSR_FH_INT_BIT_HI_PRIOR | \
210 				CSR_FH_INT_BIT_RX_CHNL1 | \
211 				CSR_FH_INT_BIT_RX_CHNL0)
212 
213 #define CSR_FH_INT_TX_MASK	(CSR_FH_INT_BIT_TX_CHNL1 | \
214 				CSR_FH_INT_BIT_TX_CHNL0)
215 
216 /* GPIO */
217 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
218 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
219 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
220 
221 /* RESET */
222 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
223 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
224 #define CSR_RESET_REG_FLAG_SW_RESET		     (0x00000080)
225 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
226 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
227 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
228 
229 /*
230  * GP (general purpose) CONTROL REGISTER
231  * Bit fields:
232  *    27:  HW_RF_KILL_SW
233  *         Indicates state of (platform's) hardware RF-Kill switch
234  * 26-24:  POWER_SAVE_TYPE
235  *         Indicates current power-saving mode:
236  *         000 -- No power saving
237  *         001 -- MAC power-down
238  *         010 -- PHY (radio) power-down
239  *         011 -- Error
240  *    10:  XTAL ON request
241  *   9-6:  SYS_CONFIG
242  *         Indicates current system configuration, reflecting pins on chip
243  *         as forced high/low by device circuit board.
244  *     4:  GOING_TO_SLEEP
245  *         Indicates MAC is entering a power-saving sleep power-down.
246  *         Not a good time to access device-internal resources.
247  *     3:  MAC_ACCESS_REQ
248  *         Host sets this to request and maintain MAC wakeup, to allow host
249  *         access to device-internal resources.  Host must wait for
250  *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
251  *         device registers.
252  *     2:  INIT_DONE
253  *         Host sets this to put device into fully operational D0 power mode.
254  *         Host resets this after SW_RESET to put device into low power mode.
255  *     0:  MAC_CLOCK_READY
256  *         Indicates MAC (ucode processor, etc.) is powered up and can run.
257  *         Internal resources are accessible.
258  *         NOTE:  This does not indicate that the processor is actually running.
259  *         NOTE:  This does not indicate that device has completed
260  *                init or post-power-down restore of internal SRAM memory.
261  *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
262  *                SRAM is restored and uCode is in normal operation mode.
263  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
264  *                do not need to save/restore it.
265  *         NOTE:  After device reset, this bit remains "0" until host sets
266  *                INIT_DONE
267  */
268 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY	     (0x00000001)
269 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE		     (0x00000004)
270 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ	     (0x00000008)
271 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP	     (0x00000010)
272 #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON		     (0x00000400)
273 
274 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN	     (0x00000001)
275 
276 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
277 #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN     (0x04000000)
278 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
279 
280 /* From Bz we use these instead during init/reset flow */
281 #define CSR_GP_CNTRL_REG_FLAG_MAC_INIT			BIT(6)
282 #define CSR_GP_CNTRL_REG_FLAG_ROM_START			BIT(7)
283 #define CSR_GP_CNTRL_REG_FLAG_MAC_STATUS		BIT(20)
284 #define CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ		BIT(21)
285 #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS	BIT(28)
286 #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ	BIT(29)
287 #define CSR_GP_CNTRL_REG_FLAG_SW_RESET			BIT(31)
288 
289 /* HW REV */
290 #define CSR_HW_REV_DASH(_val)          (((_val) & 0x0000003) >> 0)
291 #define CSR_HW_REV_STEP(_val)          (((_val) & 0x000000C) >> 2)
292 #define CSR_HW_REV_TYPE(_val)          (((_val) & 0x000FFF0) >> 4)
293 
294 /* HW RFID */
295 #define CSR_HW_RFID_FLAVOR(_val)       (((_val) & 0x000000F) >> 0)
296 #define CSR_HW_RFID_DASH(_val)         (((_val) & 0x00000F0) >> 4)
297 #define CSR_HW_RFID_STEP(_val)         (((_val) & 0x0000F00) >> 8)
298 #define CSR_HW_RFID_TYPE(_val)         (((_val) & 0x0FFF000) >> 12)
299 #define CSR_HW_RFID_IS_CDB(_val)       (((_val) & 0x10000000) >> 28)
300 #define CSR_HW_RFID_IS_JACKET(_val)    (((_val) & 0x20000000) >> 29)
301 
302 /**
303  *  hw_rev values
304  */
305 enum {
306 	SILICON_A_STEP = 0,
307 	SILICON_B_STEP,
308 	SILICON_C_STEP,
309 };
310 
311 
312 #define CSR_HW_REV_TYPE_MSK		(0x000FFF0)
313 #define CSR_HW_REV_TYPE_5300		(0x0000020)
314 #define CSR_HW_REV_TYPE_5350		(0x0000030)
315 #define CSR_HW_REV_TYPE_5100		(0x0000050)
316 #define CSR_HW_REV_TYPE_5150		(0x0000040)
317 #define CSR_HW_REV_TYPE_1000		(0x0000060)
318 #define CSR_HW_REV_TYPE_6x00		(0x0000070)
319 #define CSR_HW_REV_TYPE_6x50		(0x0000080)
320 #define CSR_HW_REV_TYPE_6150		(0x0000084)
321 #define CSR_HW_REV_TYPE_6x05		(0x00000B0)
322 #define CSR_HW_REV_TYPE_6x30		CSR_HW_REV_TYPE_6x05
323 #define CSR_HW_REV_TYPE_6x35		CSR_HW_REV_TYPE_6x05
324 #define CSR_HW_REV_TYPE_2x30		(0x00000C0)
325 #define CSR_HW_REV_TYPE_2x00		(0x0000100)
326 #define CSR_HW_REV_TYPE_105		(0x0000110)
327 #define CSR_HW_REV_TYPE_135		(0x0000120)
328 #define CSR_HW_REV_TYPE_7265D		(0x0000210)
329 #define CSR_HW_REV_TYPE_NONE		(0x00001F0)
330 #define CSR_HW_REV_TYPE_QNJ		(0x0000360)
331 #define CSR_HW_REV_TYPE_QNJ_B0		(0x0000364)
332 #define CSR_HW_REV_TYPE_QU_B0		(0x0000334)
333 #define CSR_HW_REV_TYPE_QU_C0		(0x0000338)
334 #define CSR_HW_REV_TYPE_QUZ		(0x0000354)
335 #define CSR_HW_REV_TYPE_HR_CDB		(0x0000340)
336 #define CSR_HW_REV_TYPE_SO		(0x0000370)
337 #define CSR_HW_REV_TYPE_TY		(0x0000420)
338 
339 /* RF_ID value */
340 #define CSR_HW_RF_ID_TYPE_JF		(0x00105100)
341 #define CSR_HW_RF_ID_TYPE_HR		(0x0010A000)
342 #define CSR_HW_RF_ID_TYPE_HR1		(0x0010c100)
343 #define CSR_HW_RF_ID_TYPE_HRCDB		(0x00109F00)
344 #define CSR_HW_RF_ID_TYPE_GF		(0x0010D000)
345 #define CSR_HW_RF_ID_TYPE_GF4		(0x0010E000)
346 
347 /* HW_RF CHIP STEP  */
348 #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
349 
350 /* EEPROM REG */
351 #define CSR_EEPROM_REG_READ_VALID_MSK	(0x00000001)
352 #define CSR_EEPROM_REG_BIT_CMD		(0x00000002)
353 #define CSR_EEPROM_REG_MSK_ADDR		(0x0000FFFC)
354 #define CSR_EEPROM_REG_MSK_DATA		(0xFFFF0000)
355 
356 /* EEPROM GP */
357 #define CSR_EEPROM_GP_VALID_MSK		(0x00000007) /* signature */
358 #define CSR_EEPROM_GP_IF_OWNER_MSK	(0x00000180)
359 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP	(0x00000000)
360 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP		(0x00000001)
361 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K		(0x00000002)
362 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K		(0x00000004)
363 
364 /* One-time-programmable memory general purpose reg */
365 #define CSR_OTP_GP_REG_DEVICE_SELECT	(0x00010000) /* 0 - EEPROM, 1 - OTP */
366 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE	(0x00020000) /* 0 - absolute, 1 - relative */
367 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
368 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
369 
370 /* GP REG */
371 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
372 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
373 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
374 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
375 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
376 
377 
378 /* CSR GIO */
379 #define CSR_GIO_REG_VAL_L0S_DISABLED	(0x00000002)
380 
381 /*
382  * UCODE-DRIVER GP (general purpose) mailbox register 1
383  * Host driver and uCode write and/or read this register to communicate with
384  * each other.
385  * Bit fields:
386  *     4:  UCODE_DISABLE
387  *         Host sets this to request permanent halt of uCode, same as
388  *         sending CARD_STATE command with "halt" bit set.
389  *     3:  CT_KILL_EXIT
390  *         Host sets this to request exit from CT_KILL state, i.e. host thinks
391  *         device temperature is low enough to continue normal operation.
392  *     2:  CMD_BLOCKED
393  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
394  *         to release uCode to clear all Tx and command queues, enter
395  *         unassociated mode, and power down.
396  *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
397  *     1:  SW_BIT_RFKILL
398  *         Host sets this when issuing CARD_STATE command to request
399  *         device sleep.
400  *     0:  MAC_SLEEP
401  *         uCode sets this when preparing a power-saving power-down.
402  *         uCode resets this when power-up is complete and SRAM is sane.
403  *         NOTE:  device saves internal SRAM data to host when powering down,
404  *                and must restore this data after powering back up.
405  *                MAC_SLEEP is the best indication that restore is complete.
406  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
407  *                do not need to save/restore it.
408  */
409 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
410 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
411 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
412 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
413 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE       (0x00000020)
414 
415 /* GP Driver */
416 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK	    (0x00000003)
417 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB	    (0x00000000)
418 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB	    (0x00000001)
419 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA	    (0x00000002)
420 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6	    (0x00000004)
421 #define CSR_GP_DRIVER_REG_BIT_6050_1x2		    (0x00000008)
422 
423 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER	    (0x00000080)
424 
425 /* GIO Chicken Bits (PCI Express bus link power management) */
426 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
427 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
428 
429 /* LED */
430 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
431 #define CSR_LED_REG_TURN_ON (0x60)
432 #define CSR_LED_REG_TURN_OFF (0x20)
433 
434 /* ANA_PLL */
435 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
436 
437 /* HPET MEM debug */
438 #define CSR_DBG_HPET_MEM_REG_VAL	(0xFFFF0000)
439 
440 /* DRAM INT TABLE */
441 #define CSR_DRAM_INT_TBL_ENABLE		(1 << 31)
442 #define CSR_DRAM_INIT_TBL_WRITE_POINTER	(1 << 28)
443 #define CSR_DRAM_INIT_TBL_WRAP_CHECK	(1 << 27)
444 
445 /*
446  * SHR target access (Shared block memory space)
447  *
448  * Shared internal registers can be accessed directly from PCI bus through SHR
449  * arbiter without need for the MAC HW to be powered up. This is possible due to
450  * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
451  * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
452  *
453  * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
454  * need not be powered up so no "grab inc access" is required.
455  */
456 
457 /*
458  * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
459  * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
460  * first, write to the control register:
461  * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
462  * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
463  * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
464  *
465  * To write the register, first, write to the data register
466  * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
467  * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
468  * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
469  */
470 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG	(CSR_BASE+0x0ec)
471 #define HEEP_CTRL_WRD_PCIEX_DATA_REG	(CSR_BASE+0x0f4)
472 
473 /*
474  * HBUS (Host-side Bus)
475  *
476  * HBUS registers are mapped directly into PCI bus space, but are used
477  * to indirectly access device's internal memory or registers that
478  * may be powered-down.
479  *
480  * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
481  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
482  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
483  * internal resources.
484  *
485  * Do not use iwl_write32()/iwl_read32() family to access these registers;
486  * these provide only simple PCI bus access, without waking up the MAC.
487  */
488 #define HBUS_BASE	(0x400)
489 
490 /*
491  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
492  * structures, error log, event log, verifying uCode load).
493  * First write to address register, then read from or write to data register
494  * to complete the job.  Once the address register is set up, accesses to
495  * data registers auto-increment the address by one dword.
496  * Bit usage for address registers (read or write):
497  *  0-31:  memory address within device
498  */
499 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
500 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
501 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
502 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
503 
504 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
505 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
506 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
507 
508 /*
509  * Registers for accessing device's internal peripheral registers
510  * (e.g. SCD, BSM, etc.).  First write to address register,
511  * then read from or write to data register to complete the job.
512  * Bit usage for address registers (read or write):
513  *  0-15:  register address (offset) within device
514  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
515  */
516 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
517 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
518 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
519 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
520 
521 /* Used to enable DBGM */
522 #define HBUS_TARG_TEST_REG	(HBUS_BASE+0x05c)
523 
524 /*
525  * Per-Tx-queue write pointer (index, really!)
526  * Indicates index to next TFD that driver will fill (1 past latest filled).
527  * Bit usage:
528  *  0-7:  queue write index
529  * 11-8:  queue selector
530  */
531 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
532 
533 /**********************************************************
534  * CSR values
535  **********************************************************/
536  /*
537  * host interrupt timeout value
538  * used with setting interrupt coalescing timer
539  * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
540  *
541  * default interrupt coalescing timer is 64 x 32 = 2048 usecs
542  */
543 #define IWL_HOST_INT_TIMEOUT_MAX	(0xFF)
544 #define IWL_HOST_INT_TIMEOUT_DEF	(0x40)
545 #define IWL_HOST_INT_TIMEOUT_MIN	(0x0)
546 #define IWL_HOST_INT_OPER_MODE		BIT(31)
547 
548 /*****************************************************************************
549  *                        7000/3000 series SHR DTS addresses                 *
550  *****************************************************************************/
551 
552 /* Diode Results Register Structure: */
553 enum dtd_diode_reg {
554 	DTS_DIODE_REG_DIG_VAL			= 0x000000FF, /* bits [7:0] */
555 	DTS_DIODE_REG_VREF_LOW			= 0x0000FF00, /* bits [15:8] */
556 	DTS_DIODE_REG_VREF_HIGH			= 0x00FF0000, /* bits [23:16] */
557 	DTS_DIODE_REG_VREF_ID			= 0x03000000, /* bits [25:24] */
558 	DTS_DIODE_REG_PASS_ONCE			= 0x80000000, /* bits [31:31] */
559 	DTS_DIODE_REG_FLAGS_MSK			= 0xFF000000, /* bits [31:24] */
560 /* Those are the masks INSIDE the flags bit-field: */
561 	DTS_DIODE_REG_FLAGS_VREFS_ID_POS	= 0,
562 	DTS_DIODE_REG_FLAGS_VREFS_ID		= 0x00000003, /* bits [1:0] */
563 	DTS_DIODE_REG_FLAGS_PASS_ONCE_POS	= 7,
564 	DTS_DIODE_REG_FLAGS_PASS_ONCE		= 0x00000080, /* bits [7:7] */
565 };
566 
567 /*****************************************************************************
568  *                        MSIX related registers                             *
569  *****************************************************************************/
570 
571 #define CSR_MSIX_BASE			(0x2000)
572 #define CSR_MSIX_FH_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x800)
573 #define CSR_MSIX_FH_INT_MASK_AD		(CSR_MSIX_BASE + 0x804)
574 #define CSR_MSIX_HW_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x808)
575 #define CSR_MSIX_HW_INT_MASK_AD		(CSR_MSIX_BASE + 0x80C)
576 #define CSR_MSIX_AUTOMASK_ST_AD		(CSR_MSIX_BASE + 0x810)
577 #define CSR_MSIX_RX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x880)
578 #define CSR_MSIX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x890)
579 #define CSR_MSIX_PENDING_PBA_AD		(CSR_MSIX_BASE + 0x1000)
580 #define CSR_MSIX_RX_IVAR(cause)		(CSR_MSIX_RX_IVAR_AD_REG + (cause))
581 #define CSR_MSIX_IVAR(cause)		(CSR_MSIX_IVAR_AD_REG + (cause))
582 
583 #define MSIX_FH_INT_CAUSES_Q(q)		(q)
584 
585 /*
586  * Causes for the FH register interrupts
587  */
588 enum msix_fh_int_causes {
589 	MSIX_FH_INT_CAUSES_Q0			= BIT(0),
590 	MSIX_FH_INT_CAUSES_Q1			= BIT(1),
591 	MSIX_FH_INT_CAUSES_D2S_CH0_NUM		= BIT(16),
592 	MSIX_FH_INT_CAUSES_D2S_CH1_NUM		= BIT(17),
593 	MSIX_FH_INT_CAUSES_S2D			= BIT(19),
594 	MSIX_FH_INT_CAUSES_FH_ERR		= BIT(21),
595 };
596 
597 /* The low 16 bits are for rx data queue indication */
598 #define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff
599 
600 /*
601  * Causes for the HW register interrupts
602  */
603 enum msix_hw_int_causes {
604 	MSIX_HW_INT_CAUSES_REG_ALIVE		= BIT(0),
605 	MSIX_HW_INT_CAUSES_REG_WAKEUP		= BIT(1),
606 	MSIX_HW_INT_CAUSES_REG_IML              = BIT(1),
607 	MSIX_HW_INT_CAUSES_REG_RESET_DONE	= BIT(2),
608 	MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ	= BIT(5),
609 	MSIX_HW_INT_CAUSES_REG_CT_KILL		= BIT(6),
610 	MSIX_HW_INT_CAUSES_REG_RF_KILL		= BIT(7),
611 	MSIX_HW_INT_CAUSES_REG_PERIODIC		= BIT(8),
612 	MSIX_HW_INT_CAUSES_REG_SW_ERR		= BIT(25),
613 	MSIX_HW_INT_CAUSES_REG_SCD		= BIT(26),
614 	MSIX_HW_INT_CAUSES_REG_FH_TX		= BIT(27),
615 	MSIX_HW_INT_CAUSES_REG_HW_ERR		= BIT(29),
616 	MSIX_HW_INT_CAUSES_REG_HAP		= BIT(30),
617 };
618 
619 #define MSIX_MIN_INTERRUPT_VECTORS		2
620 #define MSIX_AUTO_CLEAR_CAUSE			0
621 #define MSIX_NON_AUTO_CLEAR_CAUSE		BIT(7)
622 
623 /*****************************************************************************
624  *                     HW address related registers                          *
625  *****************************************************************************/
626 
627 #define CSR_ADDR_BASE(trans)			((trans)->cfg->mac_addr_from_csr)
628 #define CSR_MAC_ADDR0_OTP(trans)		(CSR_ADDR_BASE(trans) + 0x00)
629 #define CSR_MAC_ADDR1_OTP(trans)		(CSR_ADDR_BASE(trans) + 0x04)
630 #define CSR_MAC_ADDR0_STRAP(trans)		(CSR_ADDR_BASE(trans) + 0x08)
631 #define CSR_MAC_ADDR1_STRAP(trans)		(CSR_ADDR_BASE(trans) + 0x0c)
632 
633 #endif /* !__iwl_csr_h__ */
634