1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2005-2014, 2018-2020 Intel Corporation 4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH 5 * Copyright (C) 2016 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_csr_h__ 8 #define __iwl_csr_h__ 9 /* 10 * CSR (control and status registers) 11 * 12 * CSR registers are mapped directly into PCI bus space, and are accessible 13 * whenever platform supplies power to device, even when device is in 14 * low power states due to driver-invoked device resets 15 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 16 * 17 * Use iwl_write32() and iwl_read32() family to access these registers; 18 * these provide simple PCI bus access, without waking up the MAC. 19 * Do not use iwl_write_direct32() family for these registers; 20 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 21 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 22 * the CSR registers. 23 * 24 * NOTE: Device does need to be awake in order to read this memory 25 * via CSR_EEPROM and CSR_OTP registers 26 */ 27 #define CSR_BASE (0x000) 28 29 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 31 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 32 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 33 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 34 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 35 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 36 #define CSR_GP_CNTRL (CSR_BASE+0x024) 37 38 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ 39 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) 40 41 /* 42 * Hardware revision info 43 * Bit fields: 44 * 31-16: Reserved 45 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions 46 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 47 * 1-0: "Dash" (-) value, as in A-1, etc. 48 */ 49 #define CSR_HW_REV (CSR_BASE+0x028) 50 51 /* 52 * RF ID revision info 53 * Bit fields: 54 * 31:24: Reserved (set to 0x0) 55 * 23:12: Type 56 * 11:8: Step (A - 0x0, B - 0x1, etc) 57 * 7:4: Dash 58 * 3:0: Flavor 59 */ 60 #define CSR_HW_RF_ID (CSR_BASE+0x09c) 61 62 /* 63 * EEPROM and OTP (one-time-programmable) memory reads 64 * 65 * NOTE: Device must be awake, initialized via apm_ops.init(), 66 * in order to read. 67 */ 68 #define CSR_EEPROM_REG (CSR_BASE+0x02c) 69 #define CSR_EEPROM_GP (CSR_BASE+0x030) 70 #define CSR_OTP_GP_REG (CSR_BASE+0x034) 71 72 #define CSR_GIO_REG (CSR_BASE+0x03C) 73 #define CSR_GP_UCODE_REG (CSR_BASE+0x048) 74 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) 75 76 /* 77 * UCODE-DRIVER GP (general purpose) mailbox registers. 78 * SET/CLR registers set/clear bit(s) if "1" is written. 79 */ 80 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 81 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 82 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 83 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 84 85 #define CSR_MBOX_SET_REG (CSR_BASE + 0x88) 86 87 #define CSR_LED_REG (CSR_BASE+0x094) 88 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) 89 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */ 90 #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20) 91 #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC) 92 #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF 93 94 /* LTR control (since IWL_DEVICE_FAMILY_22000) */ 95 #define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4) 96 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000 97 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE 0x1c000000 98 #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL 0x03ff0000 99 #define CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000 100 #define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE 0x00001c00 101 #define CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff 102 #define CSR_LTR_LONG_VAL_AD_SCALE_USEC 2 103 104 /* GIO Chicken Bits (PCI Express bus link power management) */ 105 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 106 107 /* host chicken bits */ 108 #define CSR_HOST_CHICKEN (CSR_BASE + 0x204) 109 #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19) 110 111 /* Analog phase-lock-loop configuration */ 112 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 113 114 /* 115 * CSR HW resources monitor registers 116 */ 117 #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) 118 #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) 119 #define CSR_MONITOR_XTAL_RESOURCES (0x00000010) 120 121 /* 122 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 123 * "step" determines CCK backoff for txpower calculation. 124 * See also CSR_HW_REV register. 125 * Bit fields: 126 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 127 * 1-0: "Dash" (-) value, as in C-1, etc. 128 */ 129 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 130 131 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 132 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) 133 134 /* Bits for CSR_HW_IF_CONFIG_REG */ 135 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 136 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 137 #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080) 138 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 139 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 140 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 141 #define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200) 142 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 143 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 144 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 145 146 #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 147 #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 148 #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 149 #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 150 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 151 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 152 153 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 154 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 155 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 156 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 157 #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 158 #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 159 #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 160 161 #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) 162 163 #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 164 #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 165 166 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 167 * acknowledged (reset) by host writing "1" to flagged bits. */ 168 #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 169 #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 170 #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 171 #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 172 #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 173 #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 174 #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 175 #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 176 #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 177 #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 178 #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 179 180 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 181 CSR_INT_BIT_HW_ERR | \ 182 CSR_INT_BIT_FH_TX | \ 183 CSR_INT_BIT_SW_ERR | \ 184 CSR_INT_BIT_RF_KILL | \ 185 CSR_INT_BIT_SW_RX | \ 186 CSR_INT_BIT_WAKEUP | \ 187 CSR_INT_BIT_ALIVE | \ 188 CSR_INT_BIT_RX_PERIODIC) 189 190 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 191 #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 192 #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 193 #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 194 #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 195 #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 196 #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 197 198 #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 199 CSR_FH_INT_BIT_RX_CHNL1 | \ 200 CSR_FH_INT_BIT_RX_CHNL0) 201 202 #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 203 CSR_FH_INT_BIT_TX_CHNL0) 204 205 /* GPIO */ 206 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 207 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 208 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 209 210 /* RESET */ 211 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 212 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 213 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 214 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 215 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 216 #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 217 218 /* 219 * GP (general purpose) CONTROL REGISTER 220 * Bit fields: 221 * 27: HW_RF_KILL_SW 222 * Indicates state of (platform's) hardware RF-Kill switch 223 * 26-24: POWER_SAVE_TYPE 224 * Indicates current power-saving mode: 225 * 000 -- No power saving 226 * 001 -- MAC power-down 227 * 010 -- PHY (radio) power-down 228 * 011 -- Error 229 * 10: XTAL ON request 230 * 9-6: SYS_CONFIG 231 * Indicates current system configuration, reflecting pins on chip 232 * as forced high/low by device circuit board. 233 * 4: GOING_TO_SLEEP 234 * Indicates MAC is entering a power-saving sleep power-down. 235 * Not a good time to access device-internal resources. 236 * 3: MAC_ACCESS_REQ 237 * Host sets this to request and maintain MAC wakeup, to allow host 238 * access to device-internal resources. Host must wait for 239 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 240 * device registers. 241 * 2: INIT_DONE 242 * Host sets this to put device into fully operational D0 power mode. 243 * Host resets this after SW_RESET to put device into low power mode. 244 * 0: MAC_CLOCK_READY 245 * Indicates MAC (ucode processor, etc.) is powered up and can run. 246 * Internal resources are accessible. 247 * NOTE: This does not indicate that the processor is actually running. 248 * NOTE: This does not indicate that device has completed 249 * init or post-power-down restore of internal SRAM memory. 250 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 251 * SRAM is restored and uCode is in normal operation mode. 252 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 253 * do not need to save/restore it. 254 * NOTE: After device reset, this bit remains "0" until host sets 255 * INIT_DONE 256 */ 257 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 258 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 259 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 260 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 261 #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) 262 263 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 264 265 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 266 #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 267 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 268 269 270 /* HW REV */ 271 #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 272 #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 273 #define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) 274 275 /* HW RFID */ 276 #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) 277 #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) 278 #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) 279 #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) 280 #define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) 281 #define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) 282 283 /** 284 * hw_rev values 285 */ 286 enum { 287 SILICON_A_STEP = 0, 288 SILICON_B_STEP, 289 SILICON_C_STEP, 290 }; 291 292 293 #define CSR_HW_REV_TYPE_MSK (0x000FFF0) 294 #define CSR_HW_REV_TYPE_5300 (0x0000020) 295 #define CSR_HW_REV_TYPE_5350 (0x0000030) 296 #define CSR_HW_REV_TYPE_5100 (0x0000050) 297 #define CSR_HW_REV_TYPE_5150 (0x0000040) 298 #define CSR_HW_REV_TYPE_1000 (0x0000060) 299 #define CSR_HW_REV_TYPE_6x00 (0x0000070) 300 #define CSR_HW_REV_TYPE_6x50 (0x0000080) 301 #define CSR_HW_REV_TYPE_6150 (0x0000084) 302 #define CSR_HW_REV_TYPE_6x05 (0x00000B0) 303 #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 304 #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 305 #define CSR_HW_REV_TYPE_2x30 (0x00000C0) 306 #define CSR_HW_REV_TYPE_2x00 (0x0000100) 307 #define CSR_HW_REV_TYPE_105 (0x0000110) 308 #define CSR_HW_REV_TYPE_135 (0x0000120) 309 #define CSR_HW_REV_TYPE_7265D (0x0000210) 310 #define CSR_HW_REV_TYPE_NONE (0x00001F0) 311 #define CSR_HW_REV_TYPE_QNJ (0x0000360) 312 #define CSR_HW_REV_TYPE_QNJ_B0 (0x0000364) 313 #define CSR_HW_REV_TYPE_QU_B0 (0x0000334) 314 #define CSR_HW_REV_TYPE_QU_C0 (0x0000338) 315 #define CSR_HW_REV_TYPE_QUZ (0x0000354) 316 #define CSR_HW_REV_TYPE_HR_CDB (0x0000340) 317 #define CSR_HW_REV_TYPE_SO (0x0000370) 318 #define CSR_HW_REV_TYPE_TY (0x0000420) 319 320 /* RF_ID value */ 321 #define CSR_HW_RF_ID_TYPE_JF (0x00105100) 322 #define CSR_HW_RF_ID_TYPE_HR (0x0010A000) 323 #define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100) 324 #define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00) 325 #define CSR_HW_RF_ID_TYPE_GF (0x0010D000) 326 #define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000) 327 328 /* HW_RF CHIP ID */ 329 #define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF) 330 331 /* HW_RF CHIP STEP */ 332 #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF) 333 334 /* EEPROM REG */ 335 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 336 #define CSR_EEPROM_REG_BIT_CMD (0x00000002) 337 #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 338 #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 339 340 /* EEPROM GP */ 341 #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 342 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 343 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 344 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 345 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 346 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 347 348 /* One-time-programmable memory general purpose reg */ 349 #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 350 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 351 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 352 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 353 354 /* GP REG */ 355 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 356 #define CSR_GP_REG_NO_POWER_SAVE (0x00000000) 357 #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 358 #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 359 #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 360 361 362 /* CSR GIO */ 363 #define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) 364 365 /* 366 * UCODE-DRIVER GP (general purpose) mailbox register 1 367 * Host driver and uCode write and/or read this register to communicate with 368 * each other. 369 * Bit fields: 370 * 4: UCODE_DISABLE 371 * Host sets this to request permanent halt of uCode, same as 372 * sending CARD_STATE command with "halt" bit set. 373 * 3: CT_KILL_EXIT 374 * Host sets this to request exit from CT_KILL state, i.e. host thinks 375 * device temperature is low enough to continue normal operation. 376 * 2: CMD_BLOCKED 377 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 378 * to release uCode to clear all Tx and command queues, enter 379 * unassociated mode, and power down. 380 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 381 * 1: SW_BIT_RFKILL 382 * Host sets this when issuing CARD_STATE command to request 383 * device sleep. 384 * 0: MAC_SLEEP 385 * uCode sets this when preparing a power-saving power-down. 386 * uCode resets this when power-up is complete and SRAM is sane. 387 * NOTE: device saves internal SRAM data to host when powering down, 388 * and must restore this data after powering back up. 389 * MAC_SLEEP is the best indication that restore is complete. 390 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 391 * do not need to save/restore it. 392 */ 393 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 394 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 395 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 396 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 397 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 398 399 /* GP Driver */ 400 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 401 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 402 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 403 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 404 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 405 #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 406 407 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 408 409 /* GIO Chicken Bits (PCI Express bus link power management) */ 410 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 411 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 412 413 /* LED */ 414 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 415 #define CSR_LED_REG_TURN_ON (0x60) 416 #define CSR_LED_REG_TURN_OFF (0x20) 417 418 /* ANA_PLL */ 419 #define CSR50_ANA_PLL_CFG_VAL (0x00880300) 420 421 /* HPET MEM debug */ 422 #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 423 424 /* DRAM INT TABLE */ 425 #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) 426 #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 427 #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 428 429 /* 430 * SHR target access (Shared block memory space) 431 * 432 * Shared internal registers can be accessed directly from PCI bus through SHR 433 * arbiter without need for the MAC HW to be powered up. This is possible due to 434 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and 435 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. 436 * 437 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW 438 * need not be powered up so no "grab inc access" is required. 439 */ 440 441 /* 442 * Registers for accessing shared registers (e.g. SHR_APMG_GP1, 443 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), 444 * first, write to the control register: 445 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 446 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) 447 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. 448 * 449 * To write the register, first, write to the data register 450 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: 451 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 452 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) 453 */ 454 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) 455 #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) 456 457 /* 458 * HBUS (Host-side Bus) 459 * 460 * HBUS registers are mapped directly into PCI bus space, but are used 461 * to indirectly access device's internal memory or registers that 462 * may be powered-down. 463 * 464 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 465 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 466 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 467 * internal resources. 468 * 469 * Do not use iwl_write32()/iwl_read32() family to access these registers; 470 * these provide only simple PCI bus access, without waking up the MAC. 471 */ 472 #define HBUS_BASE (0x400) 473 474 /* 475 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 476 * structures, error log, event log, verifying uCode load). 477 * First write to address register, then read from or write to data register 478 * to complete the job. Once the address register is set up, accesses to 479 * data registers auto-increment the address by one dword. 480 * Bit usage for address registers (read or write): 481 * 0-31: memory address within device 482 */ 483 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 484 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 485 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 486 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 487 488 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 489 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 490 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 491 492 /* 493 * Registers for accessing device's internal peripheral registers 494 * (e.g. SCD, BSM, etc.). First write to address register, 495 * then read from or write to data register to complete the job. 496 * Bit usage for address registers (read or write): 497 * 0-15: register address (offset) within device 498 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 499 */ 500 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 501 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 502 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 503 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 504 505 /* Used to enable DBGM */ 506 #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) 507 508 /* 509 * Per-Tx-queue write pointer (index, really!) 510 * Indicates index to next TFD that driver will fill (1 past latest filled). 511 * Bit usage: 512 * 0-7: queue write index 513 * 11-8: queue selector 514 */ 515 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 516 517 /********************************************************** 518 * CSR values 519 **********************************************************/ 520 /* 521 * host interrupt timeout value 522 * used with setting interrupt coalescing timer 523 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 524 * 525 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 526 */ 527 #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) 528 #define IWL_HOST_INT_TIMEOUT_DEF (0x40) 529 #define IWL_HOST_INT_TIMEOUT_MIN (0x0) 530 #define IWL_HOST_INT_OPER_MODE BIT(31) 531 532 /***************************************************************************** 533 * 7000/3000 series SHR DTS addresses * 534 *****************************************************************************/ 535 536 /* Diode Results Register Structure: */ 537 enum dtd_diode_reg { 538 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 539 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 540 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 541 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 542 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 543 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 544 /* Those are the masks INSIDE the flags bit-field: */ 545 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 546 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 547 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 548 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 549 }; 550 551 /***************************************************************************** 552 * MSIX related registers * 553 *****************************************************************************/ 554 555 #define CSR_MSIX_BASE (0x2000) 556 #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800) 557 #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804) 558 #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808) 559 #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C) 560 #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810) 561 #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880) 562 #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890) 563 #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000) 564 #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause)) 565 #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause)) 566 567 #define MSIX_FH_INT_CAUSES_Q(q) (q) 568 569 /* 570 * Causes for the FH register interrupts 571 */ 572 enum msix_fh_int_causes { 573 MSIX_FH_INT_CAUSES_Q0 = BIT(0), 574 MSIX_FH_INT_CAUSES_Q1 = BIT(1), 575 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16), 576 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17), 577 MSIX_FH_INT_CAUSES_S2D = BIT(19), 578 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21), 579 }; 580 581 /* The low 16 bits are for rx data queue indication */ 582 #define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff 583 584 /* 585 * Causes for the HW register interrupts 586 */ 587 enum msix_hw_int_causes { 588 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0), 589 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1), 590 MSIX_HW_INT_CAUSES_REG_IML = BIT(1), 591 MSIX_HW_INT_CAUSES_REG_RESET_DONE = BIT(2), 592 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6), 593 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7), 594 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8), 595 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25), 596 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26), 597 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27), 598 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29), 599 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30), 600 }; 601 602 #define MSIX_MIN_INTERRUPT_VECTORS 2 603 #define MSIX_AUTO_CLEAR_CAUSE 0 604 #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 605 606 /***************************************************************************** 607 * HW address related registers * 608 *****************************************************************************/ 609 610 #define CSR_ADDR_BASE (0x380) 611 #define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE) 612 #define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4) 613 #define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8) 614 #define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC) 615 616 #endif /* !__iwl_csr_h__ */ 617