1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
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6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10  * Copyright(c) 2016        Intel Deutschland GmbH
11  * Copyright(c) 2018 - 2019 Intel Corporation
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63 #ifndef __iwl_csr_h__
64 #define __iwl_csr_h__
65 /*
66  * CSR (control and status registers)
67  *
68  * CSR registers are mapped directly into PCI bus space, and are accessible
69  * whenever platform supplies power to device, even when device is in
70  * low power states due to driver-invoked device resets
71  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
72  *
73  * Use iwl_write32() and iwl_read32() family to access these registers;
74  * these provide simple PCI bus access, without waking up the MAC.
75  * Do not use iwl_write_direct32() family for these registers;
76  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
77  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
78  * the CSR registers.
79  *
80  * NOTE:  Device does need to be awake in order to read this memory
81  *        via CSR_EEPROM and CSR_OTP registers
82  */
83 #define CSR_BASE    (0x000)
84 
85 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
86 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
87 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
88 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
89 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
90 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
91 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
92 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
93 
94 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
95 #define CSR_INT_PERIODIC_REG	(CSR_BASE+0x005)
96 
97 /*
98  * Hardware revision info
99  * Bit fields:
100  * 31-16:  Reserved
101  *  15-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
102  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
103  *  1-0:  "Dash" (-) value, as in A-1, etc.
104  */
105 #define CSR_HW_REV              (CSR_BASE+0x028)
106 
107 /*
108  * RF ID revision info
109  * Bit fields:
110  * 31:24: Reserved (set to 0x0)
111  * 23:12: Type
112  * 11:8:  Step (A - 0x0, B - 0x1, etc)
113  * 7:4:   Dash
114  * 3:0:   Flavor
115  */
116 #define CSR_HW_RF_ID		(CSR_BASE+0x09c)
117 
118 /*
119  * EEPROM and OTP (one-time-programmable) memory reads
120  *
121  * NOTE:  Device must be awake, initialized via apm_ops.init(),
122  *        in order to read.
123  */
124 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
125 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
126 #define CSR_OTP_GP_REG   	(CSR_BASE+0x034)
127 
128 #define CSR_GIO_REG		(CSR_BASE+0x03C)
129 #define CSR_GP_UCODE_REG	(CSR_BASE+0x048)
130 #define CSR_GP_DRIVER_REG	(CSR_BASE+0x050)
131 
132 /*
133  * UCODE-DRIVER GP (general purpose) mailbox registers.
134  * SET/CLR registers set/clear bit(s) if "1" is written.
135  */
136 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
137 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
138 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
139 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
140 
141 #define CSR_MBOX_SET_REG	(CSR_BASE + 0x88)
142 
143 #define CSR_LED_REG             (CSR_BASE+0x094)
144 #define CSR_DRAM_INT_TBL_REG	(CSR_BASE+0x0A0)
145 #define CSR_MAC_SHADOW_REG_CTRL		(CSR_BASE + 0x0A8) /* 6000 and up */
146 #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE	BIT(20)
147 #define CSR_MAC_SHADOW_REG_CTL2		(CSR_BASE + 0x0AC)
148 #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE	0xFFFF
149 
150 /* GIO Chicken Bits (PCI Express bus link power management) */
151 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
152 
153 /* host chicken bits */
154 #define CSR_HOST_CHICKEN	(CSR_BASE + 0x204)
155 #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME	BIT(19)
156 
157 /* Analog phase-lock-loop configuration  */
158 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
159 
160 /*
161  * CSR HW resources monitor registers
162  */
163 #define CSR_MONITOR_CFG_REG		(CSR_BASE+0x214)
164 #define CSR_MONITOR_STATUS_REG		(CSR_BASE+0x228)
165 #define CSR_MONITOR_XTAL_RESOURCES	(0x00000010)
166 
167 /*
168  * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
169  * "step" determines CCK backoff for txpower calculation.
170  * See also CSR_HW_REV register.
171  * Bit fields:
172  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
173  *  1-0:  "Dash" (-) value, as in C-1, etc.
174  */
175 #define CSR_HW_REV_WA_REG		(CSR_BASE+0x22C)
176 
177 #define CSR_DBG_HPET_MEM_REG		(CSR_BASE+0x240)
178 #define CSR_DBG_LINK_PWR_MGMT_REG	(CSR_BASE+0x250)
179 
180 /* Bits for CSR_HW_IF_CONFIG_REG */
181 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH	(0x00000003)
182 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP	(0x0000000C)
183 #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM	(0x00000080)
184 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER	(0x000000C0)
185 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI		(0x00000100)
186 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI	(0x00000200)
187 #define CSR_HW_IF_CONFIG_REG_D3_DEBUG		(0x00000200)
188 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE	(0x00000C00)
189 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH	(0x00003000)
190 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP	(0x0000C000)
191 
192 #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH	(0)
193 #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP	(2)
194 #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER	(6)
195 #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE	(10)
196 #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH	(12)
197 #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP	(14)
198 
199 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A	(0x00080000)
200 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM	(0x00200000)
201 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY	(0x00400000) /* PCI_OWN_SEM */
202 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
203 #define CSR_HW_IF_CONFIG_REG_PREPARE		  (0x08000000) /* WAKE_ME */
204 #define CSR_HW_IF_CONFIG_REG_ENABLE_PME		  (0x10000000)
205 #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE	  (0x40000000) /* PERSISTENCE */
206 
207 #define CSR_MBOX_SET_REG_OS_ALIVE		BIT(5)
208 
209 #define CSR_INT_PERIODIC_DIS			(0x00) /* disable periodic int*/
210 #define CSR_INT_PERIODIC_ENA			(0xFF) /* 255*32 usec ~ 8 msec*/
211 
212 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
213  * acknowledged (reset) by host writing "1" to flagged bits. */
214 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
215 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
216 #define CSR_INT_BIT_RX_PERIODIC	 (1 << 28) /* Rx periodic */
217 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
218 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
219 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
220 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
221 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
222 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses */
223 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
224 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
225 
226 #define CSR_INI_SET_MASK	(CSR_INT_BIT_FH_RX   | \
227 				 CSR_INT_BIT_HW_ERR  | \
228 				 CSR_INT_BIT_FH_TX   | \
229 				 CSR_INT_BIT_SW_ERR  | \
230 				 CSR_INT_BIT_RF_KILL | \
231 				 CSR_INT_BIT_SW_RX   | \
232 				 CSR_INT_BIT_WAKEUP  | \
233 				 CSR_INT_BIT_ALIVE   | \
234 				 CSR_INT_BIT_RX_PERIODIC)
235 
236 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
237 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
238 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
239 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
240 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
241 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
242 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
243 
244 #define CSR_FH_INT_RX_MASK	(CSR_FH_INT_BIT_HI_PRIOR | \
245 				CSR_FH_INT_BIT_RX_CHNL1 | \
246 				CSR_FH_INT_BIT_RX_CHNL0)
247 
248 #define CSR_FH_INT_TX_MASK	(CSR_FH_INT_BIT_TX_CHNL1 | \
249 				CSR_FH_INT_BIT_TX_CHNL0)
250 
251 /* GPIO */
252 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
253 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
254 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
255 
256 /* RESET */
257 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
258 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
259 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
260 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
261 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
262 
263 /*
264  * GP (general purpose) CONTROL REGISTER
265  * Bit fields:
266  *    27:  HW_RF_KILL_SW
267  *         Indicates state of (platform's) hardware RF-Kill switch
268  * 26-24:  POWER_SAVE_TYPE
269  *         Indicates current power-saving mode:
270  *         000 -- No power saving
271  *         001 -- MAC power-down
272  *         010 -- PHY (radio) power-down
273  *         011 -- Error
274  *    10:  XTAL ON request
275  *   9-6:  SYS_CONFIG
276  *         Indicates current system configuration, reflecting pins on chip
277  *         as forced high/low by device circuit board.
278  *     4:  GOING_TO_SLEEP
279  *         Indicates MAC is entering a power-saving sleep power-down.
280  *         Not a good time to access device-internal resources.
281  */
282 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
283 #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON		     (0x00000400)
284 
285 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
286 #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN     (0x04000000)
287 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
288 
289 
290 /* HW REV */
291 #define CSR_HW_REV_DASH(_val)          (((_val) & 0x0000003) >> 0)
292 #define CSR_HW_REV_STEP(_val)          (((_val) & 0x000000C) >> 2)
293 #define CSR_HW_REV_TYPE(_val)          (((_val) & 0x000FFF0) >> 4)
294 
295 /* HW RFID */
296 #define CSR_HW_RFID_FLAVOR(_val)       (((_val) & 0x000000F) >> 0)
297 #define CSR_HW_RFID_DASH(_val)         (((_val) & 0x00000F0) >> 4)
298 #define CSR_HW_RFID_STEP(_val)         (((_val) & 0x0000F00) >> 8)
299 #define CSR_HW_RFID_TYPE(_val)         (((_val) & 0x0FFF000) >> 12)
300 
301 /**
302  *  hw_rev values
303  */
304 enum {
305 	SILICON_A_STEP = 0,
306 	SILICON_B_STEP,
307 	SILICON_C_STEP,
308 };
309 
310 
311 #define CSR_HW_REV_TYPE_MSK		(0x000FFF0)
312 #define CSR_HW_REV_TYPE_5300		(0x0000020)
313 #define CSR_HW_REV_TYPE_5350		(0x0000030)
314 #define CSR_HW_REV_TYPE_5100		(0x0000050)
315 #define CSR_HW_REV_TYPE_5150		(0x0000040)
316 #define CSR_HW_REV_TYPE_1000		(0x0000060)
317 #define CSR_HW_REV_TYPE_6x00		(0x0000070)
318 #define CSR_HW_REV_TYPE_6x50		(0x0000080)
319 #define CSR_HW_REV_TYPE_6150		(0x0000084)
320 #define CSR_HW_REV_TYPE_6x05		(0x00000B0)
321 #define CSR_HW_REV_TYPE_6x30		CSR_HW_REV_TYPE_6x05
322 #define CSR_HW_REV_TYPE_6x35		CSR_HW_REV_TYPE_6x05
323 #define CSR_HW_REV_TYPE_2x30		(0x00000C0)
324 #define CSR_HW_REV_TYPE_2x00		(0x0000100)
325 #define CSR_HW_REV_TYPE_105		(0x0000110)
326 #define CSR_HW_REV_TYPE_135		(0x0000120)
327 #define CSR_HW_REV_TYPE_7265D		(0x0000210)
328 #define CSR_HW_REV_TYPE_NONE		(0x00001F0)
329 #define CSR_HW_REV_TYPE_QNJ		(0x0000360)
330 #define CSR_HW_REV_TYPE_QNJ_B0		(0x0000364)
331 #define CSR_HW_REV_TYPE_QUZ		(0x0000354)
332 #define CSR_HW_REV_TYPE_HR_CDB		(0x0000340)
333 #define CSR_HW_REV_TYPE_SO		(0x0000370)
334 #define CSR_HW_REV_TYPE_TY		(0x0000420)
335 
336 /* RF_ID value */
337 #define CSR_HW_RF_ID_TYPE_JF		(0x00105100)
338 #define CSR_HW_RF_ID_TYPE_HR		(0x0010A000)
339 #define CSR_HW_RF_ID_TYPE_HRCDB		(0x00109F00)
340 #define CSR_HW_RF_ID_TYPE_GF		(0x0010D000)
341 #define CSR_HW_RF_ID_TYPE_GF4		(0x0010E000)
342 
343 /* HW_RF CHIP ID  */
344 #define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF)
345 
346 /* HW_RF CHIP STEP  */
347 #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
348 
349 /* EEPROM REG */
350 #define CSR_EEPROM_REG_READ_VALID_MSK	(0x00000001)
351 #define CSR_EEPROM_REG_BIT_CMD		(0x00000002)
352 #define CSR_EEPROM_REG_MSK_ADDR		(0x0000FFFC)
353 #define CSR_EEPROM_REG_MSK_DATA		(0xFFFF0000)
354 
355 /* EEPROM GP */
356 #define CSR_EEPROM_GP_VALID_MSK		(0x00000007) /* signature */
357 #define CSR_EEPROM_GP_IF_OWNER_MSK	(0x00000180)
358 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP	(0x00000000)
359 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP		(0x00000001)
360 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K		(0x00000002)
361 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K		(0x00000004)
362 
363 /* One-time-programmable memory general purpose reg */
364 #define CSR_OTP_GP_REG_DEVICE_SELECT	(0x00010000) /* 0 - EEPROM, 1 - OTP */
365 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE	(0x00020000) /* 0 - absolute, 1 - relative */
366 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
367 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
368 
369 /* GP REG */
370 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
371 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
372 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
373 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
374 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
375 
376 
377 /* CSR GIO */
378 #define CSR_GIO_REG_VAL_L0S_ENABLED	(0x00000002)
379 
380 /*
381  * UCODE-DRIVER GP (general purpose) mailbox register 1
382  * Host driver and uCode write and/or read this register to communicate with
383  * each other.
384  * Bit fields:
385  *     4:  UCODE_DISABLE
386  *         Host sets this to request permanent halt of uCode, same as
387  *         sending CARD_STATE command with "halt" bit set.
388  *     3:  CT_KILL_EXIT
389  *         Host sets this to request exit from CT_KILL state, i.e. host thinks
390  *         device temperature is low enough to continue normal operation.
391  *     2:  CMD_BLOCKED
392  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
393  *         to release uCode to clear all Tx and command queues, enter
394  *         unassociated mode, and power down.
395  *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
396  *     1:  SW_BIT_RFKILL
397  *         Host sets this when issuing CARD_STATE command to request
398  *         device sleep.
399  *     0:  MAC_SLEEP
400  *         uCode sets this when preparing a power-saving power-down.
401  *         uCode resets this when power-up is complete and SRAM is sane.
402  *         NOTE:  device saves internal SRAM data to host when powering down,
403  *                and must restore this data after powering back up.
404  *                MAC_SLEEP is the best indication that restore is complete.
405  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
406  *                do not need to save/restore it.
407  */
408 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
409 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
410 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
411 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
412 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE       (0x00000020)
413 
414 /* GP Driver */
415 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK	    (0x00000003)
416 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB	    (0x00000000)
417 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB	    (0x00000001)
418 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA	    (0x00000002)
419 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6	    (0x00000004)
420 #define CSR_GP_DRIVER_REG_BIT_6050_1x2		    (0x00000008)
421 
422 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER	    (0x00000080)
423 
424 /* GIO Chicken Bits (PCI Express bus link power management) */
425 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
426 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
427 
428 /* LED */
429 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
430 #define CSR_LED_REG_TURN_ON (0x60)
431 #define CSR_LED_REG_TURN_OFF (0x20)
432 
433 /* ANA_PLL */
434 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
435 
436 /* HPET MEM debug */
437 #define CSR_DBG_HPET_MEM_REG_VAL	(0xFFFF0000)
438 
439 /* DRAM INT TABLE */
440 #define CSR_DRAM_INT_TBL_ENABLE		(1 << 31)
441 #define CSR_DRAM_INIT_TBL_WRITE_POINTER	(1 << 28)
442 #define CSR_DRAM_INIT_TBL_WRAP_CHECK	(1 << 27)
443 
444 /*
445  * SHR target access (Shared block memory space)
446  *
447  * Shared internal registers can be accessed directly from PCI bus through SHR
448  * arbiter without need for the MAC HW to be powered up. This is possible due to
449  * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
450  * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
451  *
452  * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
453  * need not be powered up so no "grab inc access" is required.
454  */
455 
456 /*
457  * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
458  * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
459  * first, write to the control register:
460  * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
461  * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
462  * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
463  *
464  * To write the register, first, write to the data register
465  * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
466  * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
467  * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
468  */
469 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG	(CSR_BASE+0x0ec)
470 #define HEEP_CTRL_WRD_PCIEX_DATA_REG	(CSR_BASE+0x0f4)
471 
472 /*
473  * HBUS (Host-side Bus)
474  *
475  * HBUS registers are mapped directly into PCI bus space, but are used
476  * to indirectly access device's internal memory or registers that
477  * may be powered-down.
478  *
479  * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
480  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
481  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
482  * internal resources.
483  *
484  * Do not use iwl_write32()/iwl_read32() family to access these registers;
485  * these provide only simple PCI bus access, without waking up the MAC.
486  */
487 #define HBUS_BASE	(0x400)
488 
489 /*
490  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
491  * structures, error log, event log, verifying uCode load).
492  * First write to address register, then read from or write to data register
493  * to complete the job.  Once the address register is set up, accesses to
494  * data registers auto-increment the address by one dword.
495  * Bit usage for address registers (read or write):
496  *  0-31:  memory address within device
497  */
498 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
499 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
500 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
501 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
502 
503 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
504 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
505 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
506 
507 /*
508  * Registers for accessing device's internal peripheral registers
509  * (e.g. SCD, BSM, etc.).  First write to address register,
510  * then read from or write to data register to complete the job.
511  * Bit usage for address registers (read or write):
512  *  0-15:  register address (offset) within device
513  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
514  */
515 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
516 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
517 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
518 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
519 
520 /* Used to enable DBGM */
521 #define HBUS_TARG_TEST_REG	(HBUS_BASE+0x05c)
522 
523 /*
524  * Per-Tx-queue write pointer (index, really!)
525  * Indicates index to next TFD that driver will fill (1 past latest filled).
526  * Bit usage:
527  *  0-7:  queue write index
528  * 11-8:  queue selector
529  */
530 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
531 
532 /**********************************************************
533  * CSR values
534  **********************************************************/
535  /*
536  * host interrupt timeout value
537  * used with setting interrupt coalescing timer
538  * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
539  *
540  * default interrupt coalescing timer is 64 x 32 = 2048 usecs
541  */
542 #define IWL_HOST_INT_TIMEOUT_MAX	(0xFF)
543 #define IWL_HOST_INT_TIMEOUT_DEF	(0x40)
544 #define IWL_HOST_INT_TIMEOUT_MIN	(0x0)
545 #define IWL_HOST_INT_OPER_MODE		BIT(31)
546 
547 /*****************************************************************************
548  *                        7000/3000 series SHR DTS addresses                 *
549  *****************************************************************************/
550 
551 /* Diode Results Register Structure: */
552 enum dtd_diode_reg {
553 	DTS_DIODE_REG_DIG_VAL			= 0x000000FF, /* bits [7:0] */
554 	DTS_DIODE_REG_VREF_LOW			= 0x0000FF00, /* bits [15:8] */
555 	DTS_DIODE_REG_VREF_HIGH			= 0x00FF0000, /* bits [23:16] */
556 	DTS_DIODE_REG_VREF_ID			= 0x03000000, /* bits [25:24] */
557 	DTS_DIODE_REG_PASS_ONCE			= 0x80000000, /* bits [31:31] */
558 	DTS_DIODE_REG_FLAGS_MSK			= 0xFF000000, /* bits [31:24] */
559 /* Those are the masks INSIDE the flags bit-field: */
560 	DTS_DIODE_REG_FLAGS_VREFS_ID_POS	= 0,
561 	DTS_DIODE_REG_FLAGS_VREFS_ID		= 0x00000003, /* bits [1:0] */
562 	DTS_DIODE_REG_FLAGS_PASS_ONCE_POS	= 7,
563 	DTS_DIODE_REG_FLAGS_PASS_ONCE		= 0x00000080, /* bits [7:7] */
564 };
565 
566 /*****************************************************************************
567  *                        MSIX related registers                             *
568  *****************************************************************************/
569 
570 #define CSR_MSIX_BASE			(0x2000)
571 #define CSR_MSIX_FH_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x800)
572 #define CSR_MSIX_FH_INT_MASK_AD		(CSR_MSIX_BASE + 0x804)
573 #define CSR_MSIX_HW_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x808)
574 #define CSR_MSIX_HW_INT_MASK_AD		(CSR_MSIX_BASE + 0x80C)
575 #define CSR_MSIX_AUTOMASK_ST_AD		(CSR_MSIX_BASE + 0x810)
576 #define CSR_MSIX_RX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x880)
577 #define CSR_MSIX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x890)
578 #define CSR_MSIX_PENDING_PBA_AD		(CSR_MSIX_BASE + 0x1000)
579 #define CSR_MSIX_RX_IVAR(cause)		(CSR_MSIX_RX_IVAR_AD_REG + (cause))
580 #define CSR_MSIX_IVAR(cause)		(CSR_MSIX_IVAR_AD_REG + (cause))
581 
582 #define MSIX_FH_INT_CAUSES_Q(q)		(q)
583 
584 /*
585  * Causes for the FH register interrupts
586  */
587 enum msix_fh_int_causes {
588 	MSIX_FH_INT_CAUSES_Q0			= BIT(0),
589 	MSIX_FH_INT_CAUSES_Q1			= BIT(1),
590 	MSIX_FH_INT_CAUSES_D2S_CH0_NUM		= BIT(16),
591 	MSIX_FH_INT_CAUSES_D2S_CH1_NUM		= BIT(17),
592 	MSIX_FH_INT_CAUSES_S2D			= BIT(19),
593 	MSIX_FH_INT_CAUSES_FH_ERR		= BIT(21),
594 };
595 
596 /*
597  * Causes for the HW register interrupts
598  */
599 enum msix_hw_int_causes {
600 	MSIX_HW_INT_CAUSES_REG_ALIVE		= BIT(0),
601 	MSIX_HW_INT_CAUSES_REG_WAKEUP		= BIT(1),
602 	MSIX_HW_INT_CAUSES_REG_IPC		= BIT(1),
603 	MSIX_HW_INT_CAUSES_REG_IML              = BIT(2),
604 	MSIX_HW_INT_CAUSES_REG_SW_ERR_V2	= BIT(5),
605 	MSIX_HW_INT_CAUSES_REG_CT_KILL		= BIT(6),
606 	MSIX_HW_INT_CAUSES_REG_RF_KILL		= BIT(7),
607 	MSIX_HW_INT_CAUSES_REG_PERIODIC		= BIT(8),
608 	MSIX_HW_INT_CAUSES_REG_SW_ERR		= BIT(25),
609 	MSIX_HW_INT_CAUSES_REG_SCD		= BIT(26),
610 	MSIX_HW_INT_CAUSES_REG_FH_TX		= BIT(27),
611 	MSIX_HW_INT_CAUSES_REG_HW_ERR		= BIT(29),
612 	MSIX_HW_INT_CAUSES_REG_HAP		= BIT(30),
613 };
614 
615 #define MSIX_MIN_INTERRUPT_VECTORS		2
616 #define MSIX_AUTO_CLEAR_CAUSE			0
617 #define MSIX_NON_AUTO_CLEAR_CAUSE		BIT(7)
618 
619 /*****************************************************************************
620  *                     HW address related registers                          *
621  *****************************************************************************/
622 
623 #define CSR_ADDR_BASE			(0x380)
624 #define CSR_MAC_ADDR0_OTP		(CSR_ADDR_BASE)
625 #define CSR_MAC_ADDR1_OTP		(CSR_ADDR_BASE + 4)
626 #define CSR_MAC_ADDR0_STRAP		(CSR_ADDR_BASE + 8)
627 #define CSR_MAC_ADDR1_STRAP		(CSR_ADDR_BASE + 0xC)
628 
629 #endif /* !__iwl_csr_h__ */
630