18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 28e99ea8dSJohannes Berg /* 3*5f06f6bfSLuca Coelho * Copyright (C) 2005-2014, 2018-2022 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2014 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #ifndef __iwl_csr_h__ 8e705c121SKalle Valo #define __iwl_csr_h__ 9e705c121SKalle Valo /* 10e705c121SKalle Valo * CSR (control and status registers) 11e705c121SKalle Valo * 12e705c121SKalle Valo * CSR registers are mapped directly into PCI bus space, and are accessible 13e705c121SKalle Valo * whenever platform supplies power to device, even when device is in 14e705c121SKalle Valo * low power states due to driver-invoked device resets 15e705c121SKalle Valo * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 16e705c121SKalle Valo * 17e705c121SKalle Valo * Use iwl_write32() and iwl_read32() family to access these registers; 18e705c121SKalle Valo * these provide simple PCI bus access, without waking up the MAC. 19e705c121SKalle Valo * Do not use iwl_write_direct32() family for these registers; 20e705c121SKalle Valo * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 21e705c121SKalle Valo * The MAC (uCode processor, etc.) does not need to be powered up for accessing 22e705c121SKalle Valo * the CSR registers. 23e705c121SKalle Valo * 24e705c121SKalle Valo * NOTE: Device does need to be awake in order to read this memory 25e705c121SKalle Valo * via CSR_EEPROM and CSR_OTP registers 26e705c121SKalle Valo */ 27e705c121SKalle Valo #define CSR_BASE (0x000) 28e705c121SKalle Valo 29e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 30e705c121SKalle Valo #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 31e705c121SKalle Valo #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 32e705c121SKalle Valo #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 33e705c121SKalle Valo #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 34e705c121SKalle Valo #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 35e705c121SKalle Valo #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 36e705c121SKalle Valo #define CSR_GP_CNTRL (CSR_BASE+0x024) 37595c230bSMatti Gottlieb #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */ 38e705c121SKalle Valo 39e705c121SKalle Valo /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ 40e705c121SKalle Valo #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) 41e705c121SKalle Valo 42e705c121SKalle Valo /* 43e705c121SKalle Valo * Hardware revision info 44e705c121SKalle Valo * Bit fields: 45e705c121SKalle Valo * 31-16: Reserved 46e705c121SKalle Valo * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions 47e705c121SKalle Valo * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 48e705c121SKalle Valo * 1-0: "Dash" (-) value, as in A-1, etc. 49e705c121SKalle Valo */ 50e705c121SKalle Valo #define CSR_HW_REV (CSR_BASE+0x028) 51e705c121SKalle Valo 52e705c121SKalle Valo /* 531afb0ae4SHaim Dreyfuss * RF ID revision info 541afb0ae4SHaim Dreyfuss * Bit fields: 551afb0ae4SHaim Dreyfuss * 31:24: Reserved (set to 0x0) 561afb0ae4SHaim Dreyfuss * 23:12: Type 571afb0ae4SHaim Dreyfuss * 11:8: Step (A - 0x0, B - 0x1, etc) 581afb0ae4SHaim Dreyfuss * 7:4: Dash 591afb0ae4SHaim Dreyfuss * 3:0: Flavor 601afb0ae4SHaim Dreyfuss */ 611afb0ae4SHaim Dreyfuss #define CSR_HW_RF_ID (CSR_BASE+0x09c) 621afb0ae4SHaim Dreyfuss 631afb0ae4SHaim Dreyfuss /* 64e705c121SKalle Valo * EEPROM and OTP (one-time-programmable) memory reads 65e705c121SKalle Valo * 66e705c121SKalle Valo * NOTE: Device must be awake, initialized via apm_ops.init(), 67e705c121SKalle Valo * in order to read. 68e705c121SKalle Valo */ 69e705c121SKalle Valo #define CSR_EEPROM_REG (CSR_BASE+0x02c) 70e705c121SKalle Valo #define CSR_EEPROM_GP (CSR_BASE+0x030) 71e705c121SKalle Valo #define CSR_OTP_GP_REG (CSR_BASE+0x034) 72e705c121SKalle Valo 73e705c121SKalle Valo #define CSR_GIO_REG (CSR_BASE+0x03C) 74e705c121SKalle Valo #define CSR_GP_UCODE_REG (CSR_BASE+0x048) 75e705c121SKalle Valo #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) 76e705c121SKalle Valo 77e705c121SKalle Valo /* 78e705c121SKalle Valo * UCODE-DRIVER GP (general purpose) mailbox registers. 79e705c121SKalle Valo * SET/CLR registers set/clear bit(s) if "1" is written. 80e705c121SKalle Valo */ 81e705c121SKalle Valo #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 82e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 83e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 84e705c121SKalle Valo #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 85e705c121SKalle Valo 86e705c121SKalle Valo #define CSR_MBOX_SET_REG (CSR_BASE + 0x88) 87e705c121SKalle Valo 88e705c121SKalle Valo #define CSR_LED_REG (CSR_BASE+0x094) 89e705c121SKalle Valo #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) 90e705c121SKalle Valo #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */ 911316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20) 921316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC) 931316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF 94e705c121SKalle Valo 95edb62520SJohannes Berg /* LTR control (since IWL_DEVICE_FAMILY_22000) */ 96edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4) 97edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000 98edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE 0x1c000000 99edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL 0x03ff0000 100edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000 101edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE 0x00001c00 102edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff 103edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SCALE_USEC 2 104edb62520SJohannes Berg 105e705c121SKalle Valo /* GIO Chicken Bits (PCI Express bus link power management) */ 106e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 107e705c121SKalle Valo 108af08571dSHaim Dreyfuss #define CSR_IPC_SLEEP_CONTROL (CSR_BASE + 0x114) 109af08571dSHaim Dreyfuss #define CSR_IPC_SLEEP_CONTROL_SUSPEND 0x3 110af08571dSHaim Dreyfuss #define CSR_IPC_SLEEP_CONTROL_RESUME 0 111af08571dSHaim Dreyfuss 112fdfde0cbSJohannes Berg /* Doorbell - since Bz 113fdfde0cbSJohannes Berg * connected to UREG_DOORBELL_TO_ISR6 (lower 16 bits only) 114fdfde0cbSJohannes Berg */ 1156c0795f1SJohannes Berg #define CSR_DOORBELL_VECTOR (CSR_BASE + 0x130) 1166c0795f1SJohannes Berg 117c00ee467SJohannes Berg /* host chicken bits */ 118c00ee467SJohannes Berg #define CSR_HOST_CHICKEN (CSR_BASE + 0x204) 119c00ee467SJohannes Berg #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19) 120c00ee467SJohannes Berg 121e705c121SKalle Valo /* Analog phase-lock-loop configuration */ 122e705c121SKalle Valo #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 123e705c121SKalle Valo 124e705c121SKalle Valo /* 125e705c121SKalle Valo * CSR HW resources monitor registers 126e705c121SKalle Valo */ 127e705c121SKalle Valo #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) 128e705c121SKalle Valo #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) 129e705c121SKalle Valo #define CSR_MONITOR_XTAL_RESOURCES (0x00000010) 130e705c121SKalle Valo 131e705c121SKalle Valo /* 132e705c121SKalle Valo * CSR Hardware Revision Workaround Register. Indicates hardware rev; 133fb70d49fSLuca Coelho * "step" determines CCK backoff for txpower calculation. 134e705c121SKalle Valo * See also CSR_HW_REV register. 135e705c121SKalle Valo * Bit fields: 136e705c121SKalle Valo * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 137e705c121SKalle Valo * 1-0: "Dash" (-) value, as in C-1, etc. 138e705c121SKalle Valo */ 139e705c121SKalle Valo #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 140e705c121SKalle Valo 141e705c121SKalle Valo #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 142e705c121SKalle Valo #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) 143e705c121SKalle Valo 144595c230bSMatti Gottlieb /* 145595c230bSMatti Gottlieb * Scratch register initial configuration - this is set on init, and read 146595c230bSMatti Gottlieb * during a error FW error. 147595c230bSMatti Gottlieb */ 148595c230bSMatti Gottlieb #define CSR_FUNC_SCRATCH_INIT_VALUE (0x01010101) 149595c230bSMatti Gottlieb 150e705c121SKalle Valo /* Bits for CSR_HW_IF_CONFIG_REG */ 15155c6d8f8SMike Golant #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH (0x0000000F) 152e41e2c26SShahar S Matityahu #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080) 153e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 154e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 155e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 1562d8c2615SShahar S Matityahu #define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200) 157e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 158e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 159e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 160e705c121SKalle Valo 161e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 162e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 163e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 164e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 165e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 166e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 167e705c121SKalle Valo 168e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 169e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 170e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 171e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 172e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 173e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 174e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 175e705c121SKalle Valo 176e705c121SKalle Valo #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) 177e705c121SKalle Valo 178e705c121SKalle Valo #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 179e705c121SKalle Valo #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 180e705c121SKalle Valo 181e705c121SKalle Valo /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 182e705c121SKalle Valo * acknowledged (reset) by host writing "1" to flagged bits. */ 183e705c121SKalle Valo #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 184e705c121SKalle Valo #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 185e705c121SKalle Valo #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 186e705c121SKalle Valo #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 187e705c121SKalle Valo #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 188e705c121SKalle Valo #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 189e705c121SKalle Valo #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 190e705c121SKalle Valo #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 191e705c121SKalle Valo #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 192e705c121SKalle Valo #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 193e705c121SKalle Valo #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 194e705c121SKalle Valo 195e705c121SKalle Valo #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 196e705c121SKalle Valo CSR_INT_BIT_HW_ERR | \ 197e705c121SKalle Valo CSR_INT_BIT_FH_TX | \ 198e705c121SKalle Valo CSR_INT_BIT_SW_ERR | \ 199e705c121SKalle Valo CSR_INT_BIT_RF_KILL | \ 200e705c121SKalle Valo CSR_INT_BIT_SW_RX | \ 201e705c121SKalle Valo CSR_INT_BIT_WAKEUP | \ 202e705c121SKalle Valo CSR_INT_BIT_ALIVE | \ 203e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC) 204e705c121SKalle Valo 205e705c121SKalle Valo /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 206e705c121SKalle Valo #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 207e705c121SKalle Valo #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 208e705c121SKalle Valo #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 209e705c121SKalle Valo #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 210e705c121SKalle Valo #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 211e705c121SKalle Valo #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 212e705c121SKalle Valo 213e705c121SKalle Valo #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 214e705c121SKalle Valo CSR_FH_INT_BIT_RX_CHNL1 | \ 215e705c121SKalle Valo CSR_FH_INT_BIT_RX_CHNL0) 216e705c121SKalle Valo 217e705c121SKalle Valo #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 218e705c121SKalle Valo CSR_FH_INT_BIT_TX_CHNL0) 219e705c121SKalle Valo 220e705c121SKalle Valo /* GPIO */ 221e705c121SKalle Valo #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 222e705c121SKalle Valo #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 223e705c121SKalle Valo #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 224e705c121SKalle Valo 225e705c121SKalle Valo /* RESET */ 226e705c121SKalle Valo #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 227e705c121SKalle Valo #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 2286dece0e9SLuca Coelho #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 229e705c121SKalle Valo #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 230e705c121SKalle Valo #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 231e705c121SKalle Valo #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 232e705c121SKalle Valo 233e705c121SKalle Valo /* 234e705c121SKalle Valo * GP (general purpose) CONTROL REGISTER 235e705c121SKalle Valo * Bit fields: 236e705c121SKalle Valo * 27: HW_RF_KILL_SW 237e705c121SKalle Valo * Indicates state of (platform's) hardware RF-Kill switch 238e705c121SKalle Valo * 26-24: POWER_SAVE_TYPE 239e705c121SKalle Valo * Indicates current power-saving mode: 240e705c121SKalle Valo * 000 -- No power saving 241e705c121SKalle Valo * 001 -- MAC power-down 242e705c121SKalle Valo * 010 -- PHY (radio) power-down 243e705c121SKalle Valo * 011 -- Error 244e705c121SKalle Valo * 10: XTAL ON request 245e705c121SKalle Valo * 9-6: SYS_CONFIG 246e705c121SKalle Valo * Indicates current system configuration, reflecting pins on chip 247e705c121SKalle Valo * as forced high/low by device circuit board. 248e705c121SKalle Valo * 4: GOING_TO_SLEEP 249e705c121SKalle Valo * Indicates MAC is entering a power-saving sleep power-down. 250e705c121SKalle Valo * Not a good time to access device-internal resources. 2516dece0e9SLuca Coelho * 3: MAC_ACCESS_REQ 2526dece0e9SLuca Coelho * Host sets this to request and maintain MAC wakeup, to allow host 2536dece0e9SLuca Coelho * access to device-internal resources. Host must wait for 2546dece0e9SLuca Coelho * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 2556dece0e9SLuca Coelho * device registers. 2566dece0e9SLuca Coelho * 2: INIT_DONE 2576dece0e9SLuca Coelho * Host sets this to put device into fully operational D0 power mode. 2586dece0e9SLuca Coelho * Host resets this after SW_RESET to put device into low power mode. 2596dece0e9SLuca Coelho * 0: MAC_CLOCK_READY 2606dece0e9SLuca Coelho * Indicates MAC (ucode processor, etc.) is powered up and can run. 2616dece0e9SLuca Coelho * Internal resources are accessible. 2626dece0e9SLuca Coelho * NOTE: This does not indicate that the processor is actually running. 2636dece0e9SLuca Coelho * NOTE: This does not indicate that device has completed 2646dece0e9SLuca Coelho * init or post-power-down restore of internal SRAM memory. 2656dece0e9SLuca Coelho * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 2666dece0e9SLuca Coelho * SRAM is restored and uCode is in normal operation mode. 2676dece0e9SLuca Coelho * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 2686dece0e9SLuca Coelho * do not need to save/restore it. 2696dece0e9SLuca Coelho * NOTE: After device reset, this bit remains "0" until host sets 2706dece0e9SLuca Coelho * INIT_DONE 271e705c121SKalle Valo */ 2726dece0e9SLuca Coelho #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 2739a47cb98SLuca Coelho #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 2746dece0e9SLuca Coelho #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 275e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 276e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) 277e705c121SKalle Valo 2786dece0e9SLuca Coelho #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 2796dece0e9SLuca Coelho 280e705c121SKalle Valo #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 281ae5bb2a6SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 282e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 283e705c121SKalle Valo 2849ce041f5SJohannes Berg /* From Bz we use these instead during init/reset flow */ 2859ce041f5SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_MAC_INIT BIT(6) 2869ce041f5SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_ROM_START BIT(7) 2879ce041f5SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_MAC_STATUS BIT(20) 2889ce041f5SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ BIT(21) 2899ce041f5SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS BIT(28) 2909ce041f5SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ BIT(29) 2919ce041f5SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_SW_RESET BIT(31) 292e705c121SKalle Valo 293e705c121SKalle Valo /* HW REV */ 29455c6d8f8SMike Golant #define CSR_HW_REV_STEP_DASH(_val) ((_val) & CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH) 295391481adSShahar S Matityahu #define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) 296e705c121SKalle Valo 2970705b953SHaim Dreyfuss /* HW RFID */ 2980705b953SHaim Dreyfuss #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) 2990705b953SHaim Dreyfuss #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) 3000705b953SHaim Dreyfuss #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) 3010705b953SHaim Dreyfuss #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) 302b964bfd0SMatti Gottlieb #define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) 303b964bfd0SMatti Gottlieb #define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) 304e705c121SKalle Valo 305e705c121SKalle Valo /** 306e705c121SKalle Valo * hw_rev values 307e705c121SKalle Valo */ 308e705c121SKalle Valo enum { 309e705c121SKalle Valo SILICON_A_STEP = 0, 310e705c121SKalle Valo SILICON_B_STEP, 311e705c121SKalle Valo SILICON_C_STEP, 312f738e705SMike Golant SILICON_Z_STEP = 0xf, 313e705c121SKalle Valo }; 314e705c121SKalle Valo 315e705c121SKalle Valo 316e705c121SKalle Valo #define CSR_HW_REV_TYPE_MSK (0x000FFF0) 317e705c121SKalle Valo #define CSR_HW_REV_TYPE_5300 (0x0000020) 318e705c121SKalle Valo #define CSR_HW_REV_TYPE_5350 (0x0000030) 319e705c121SKalle Valo #define CSR_HW_REV_TYPE_5100 (0x0000050) 320e705c121SKalle Valo #define CSR_HW_REV_TYPE_5150 (0x0000040) 321e705c121SKalle Valo #define CSR_HW_REV_TYPE_1000 (0x0000060) 322e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x00 (0x0000070) 323e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x50 (0x0000080) 324e705c121SKalle Valo #define CSR_HW_REV_TYPE_6150 (0x0000084) 325e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x05 (0x00000B0) 326e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 327e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 328e705c121SKalle Valo #define CSR_HW_REV_TYPE_2x30 (0x00000C0) 329e705c121SKalle Valo #define CSR_HW_REV_TYPE_2x00 (0x0000100) 330e705c121SKalle Valo #define CSR_HW_REV_TYPE_105 (0x0000110) 331e705c121SKalle Valo #define CSR_HW_REV_TYPE_135 (0x0000120) 332*5f06f6bfSLuca Coelho #define CSR_HW_REV_TYPE_3160 (0x0000164) 333e705c121SKalle Valo #define CSR_HW_REV_TYPE_7265D (0x0000210) 334e705c121SKalle Valo #define CSR_HW_REV_TYPE_NONE (0x00001F0) 3355f19d6ddSTzipi Peres #define CSR_HW_REV_TYPE_QNJ (0x0000360) 33655c6d8f8SMike Golant #define CSR_HW_REV_TYPE_QNJ_B0 (0x0000361) 33755c6d8f8SMike Golant #define CSR_HW_REV_TYPE_QU_B0 (0x0000331) 33855c6d8f8SMike Golant #define CSR_HW_REV_TYPE_QU_C0 (0x0000332) 33955c6d8f8SMike Golant #define CSR_HW_REV_TYPE_QUZ (0x0000351) 3405f19d6ddSTzipi Peres #define CSR_HW_REV_TYPE_HR_CDB (0x0000340) 341ff911dcaSShaul Triebitz #define CSR_HW_REV_TYPE_SO (0x0000370) 342ff911dcaSShaul Triebitz #define CSR_HW_REV_TYPE_TY (0x0000420) 343e705c121SKalle Valo 3441afb0ae4SHaim Dreyfuss /* RF_ID value */ 34536ae4f3aSLiad Kaufman #define CSR_HW_RF_ID_TYPE_JF (0x00105100) 346a85281ebSSara Sharon #define CSR_HW_RF_ID_TYPE_HR (0x0010A000) 347498d3eb5SOren Givon #define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100) 3485f19d6ddSTzipi Peres #define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00) 349ff911dcaSShaul Triebitz #define CSR_HW_RF_ID_TYPE_GF (0x0010D000) 3505bd757a6SShaul Triebitz #define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000) 3515f19d6ddSTzipi Peres 35233708052SLuca Coelho /* HW_RF CHIP STEP */ 35333708052SLuca Coelho #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF) 35433708052SLuca Coelho 355e705c121SKalle Valo /* EEPROM REG */ 356e705c121SKalle Valo #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 357e705c121SKalle Valo #define CSR_EEPROM_REG_BIT_CMD (0x00000002) 358e705c121SKalle Valo #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 359e705c121SKalle Valo #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 360e705c121SKalle Valo 361e705c121SKalle Valo /* EEPROM GP */ 362e705c121SKalle Valo #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 363e705c121SKalle Valo #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 364e705c121SKalle Valo #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 365e705c121SKalle Valo #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 366e705c121SKalle Valo #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 367e705c121SKalle Valo #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 368e705c121SKalle Valo 369e705c121SKalle Valo /* One-time-programmable memory general purpose reg */ 370e705c121SKalle Valo #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 371e705c121SKalle Valo #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 372e705c121SKalle Valo #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 373e705c121SKalle Valo #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 374e705c121SKalle Valo 375e705c121SKalle Valo /* GP REG */ 376e705c121SKalle Valo #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 377e705c121SKalle Valo #define CSR_GP_REG_NO_POWER_SAVE (0x00000000) 378e705c121SKalle Valo #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 379e705c121SKalle Valo #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 380e705c121SKalle Valo #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 381e705c121SKalle Valo 382e705c121SKalle Valo 383e705c121SKalle Valo /* CSR GIO */ 3843d1b28fdSLuca Coelho #define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) 385e705c121SKalle Valo 386e705c121SKalle Valo /* 387e705c121SKalle Valo * UCODE-DRIVER GP (general purpose) mailbox register 1 388e705c121SKalle Valo * Host driver and uCode write and/or read this register to communicate with 389e705c121SKalle Valo * each other. 390e705c121SKalle Valo * Bit fields: 391e705c121SKalle Valo * 4: UCODE_DISABLE 392e705c121SKalle Valo * Host sets this to request permanent halt of uCode, same as 393e705c121SKalle Valo * sending CARD_STATE command with "halt" bit set. 394e705c121SKalle Valo * 3: CT_KILL_EXIT 395e705c121SKalle Valo * Host sets this to request exit from CT_KILL state, i.e. host thinks 396e705c121SKalle Valo * device temperature is low enough to continue normal operation. 397e705c121SKalle Valo * 2: CMD_BLOCKED 398e705c121SKalle Valo * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 399e705c121SKalle Valo * to release uCode to clear all Tx and command queues, enter 400e705c121SKalle Valo * unassociated mode, and power down. 401e705c121SKalle Valo * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 402e705c121SKalle Valo * 1: SW_BIT_RFKILL 403e705c121SKalle Valo * Host sets this when issuing CARD_STATE command to request 404e705c121SKalle Valo * device sleep. 405e705c121SKalle Valo * 0: MAC_SLEEP 406e705c121SKalle Valo * uCode sets this when preparing a power-saving power-down. 407e705c121SKalle Valo * uCode resets this when power-up is complete and SRAM is sane. 408e705c121SKalle Valo * NOTE: device saves internal SRAM data to host when powering down, 409e705c121SKalle Valo * and must restore this data after powering back up. 410e705c121SKalle Valo * MAC_SLEEP is the best indication that restore is complete. 411e705c121SKalle Valo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 412e705c121SKalle Valo * do not need to save/restore it. 413e705c121SKalle Valo */ 414e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 415e705c121SKalle Valo #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 416e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 417e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 418e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 419e705c121SKalle Valo 420e705c121SKalle Valo /* GP Driver */ 421e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 422e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 423e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 424e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 425e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 426e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 427e705c121SKalle Valo 428e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 429e705c121SKalle Valo 430e705c121SKalle Valo /* GIO Chicken Bits (PCI Express bus link power management) */ 431e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 432e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 433e705c121SKalle Valo 434e705c121SKalle Valo /* LED */ 435e705c121SKalle Valo #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 436e705c121SKalle Valo #define CSR_LED_REG_TURN_ON (0x60) 437e705c121SKalle Valo #define CSR_LED_REG_TURN_OFF (0x20) 438e705c121SKalle Valo 439e705c121SKalle Valo /* ANA_PLL */ 440e705c121SKalle Valo #define CSR50_ANA_PLL_CFG_VAL (0x00880300) 441e705c121SKalle Valo 442e705c121SKalle Valo /* HPET MEM debug */ 443e705c121SKalle Valo #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 444e705c121SKalle Valo 445e705c121SKalle Valo /* DRAM INT TABLE */ 446e705c121SKalle Valo #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) 447e705c121SKalle Valo #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 448e705c121SKalle Valo #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 449e705c121SKalle Valo 450e705c121SKalle Valo /* 451e705c121SKalle Valo * SHR target access (Shared block memory space) 452e705c121SKalle Valo * 453e705c121SKalle Valo * Shared internal registers can be accessed directly from PCI bus through SHR 454e705c121SKalle Valo * arbiter without need for the MAC HW to be powered up. This is possible due to 455e705c121SKalle Valo * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and 456e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. 457e705c121SKalle Valo * 458e705c121SKalle Valo * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW 459e705c121SKalle Valo * need not be powered up so no "grab inc access" is required. 460e705c121SKalle Valo */ 461e705c121SKalle Valo 462e705c121SKalle Valo /* 463e705c121SKalle Valo * Registers for accessing shared registers (e.g. SHR_APMG_GP1, 464e705c121SKalle Valo * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), 465e705c121SKalle Valo * first, write to the control register: 466e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 467e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) 468e705c121SKalle Valo * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. 469e705c121SKalle Valo * 470e705c121SKalle Valo * To write the register, first, write to the data register 471e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: 472e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 473e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) 474e705c121SKalle Valo */ 475e705c121SKalle Valo #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) 476e705c121SKalle Valo #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) 477e705c121SKalle Valo 478e705c121SKalle Valo /* 479e705c121SKalle Valo * HBUS (Host-side Bus) 480e705c121SKalle Valo * 481e705c121SKalle Valo * HBUS registers are mapped directly into PCI bus space, but are used 482e705c121SKalle Valo * to indirectly access device's internal memory or registers that 483e705c121SKalle Valo * may be powered-down. 484e705c121SKalle Valo * 485e705c121SKalle Valo * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 486e705c121SKalle Valo * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 487e705c121SKalle Valo * to make sure the MAC (uCode processor, etc.) is powered up for accessing 488e705c121SKalle Valo * internal resources. 489e705c121SKalle Valo * 490e705c121SKalle Valo * Do not use iwl_write32()/iwl_read32() family to access these registers; 491e705c121SKalle Valo * these provide only simple PCI bus access, without waking up the MAC. 492e705c121SKalle Valo */ 493e705c121SKalle Valo #define HBUS_BASE (0x400) 494e705c121SKalle Valo 495e705c121SKalle Valo /* 496e705c121SKalle Valo * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 497e705c121SKalle Valo * structures, error log, event log, verifying uCode load). 498e705c121SKalle Valo * First write to address register, then read from or write to data register 499e705c121SKalle Valo * to complete the job. Once the address register is set up, accesses to 500e705c121SKalle Valo * data registers auto-increment the address by one dword. 501e705c121SKalle Valo * Bit usage for address registers (read or write): 502e705c121SKalle Valo * 0-31: memory address within device 503e705c121SKalle Valo */ 504e705c121SKalle Valo #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 505e705c121SKalle Valo #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 506e705c121SKalle Valo #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 507e705c121SKalle Valo #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 508e705c121SKalle Valo 509e705c121SKalle Valo /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 510e705c121SKalle Valo #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 511e705c121SKalle Valo #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 512e705c121SKalle Valo 513e705c121SKalle Valo /* 514e705c121SKalle Valo * Registers for accessing device's internal peripheral registers 515e705c121SKalle Valo * (e.g. SCD, BSM, etc.). First write to address register, 516e705c121SKalle Valo * then read from or write to data register to complete the job. 517e705c121SKalle Valo * Bit usage for address registers (read or write): 518e705c121SKalle Valo * 0-15: register address (offset) within device 519e705c121SKalle Valo * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 520e705c121SKalle Valo */ 521e705c121SKalle Valo #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 522e705c121SKalle Valo #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 523e705c121SKalle Valo #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 524e705c121SKalle Valo #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 525e705c121SKalle Valo 526e705c121SKalle Valo /* Used to enable DBGM */ 527e705c121SKalle Valo #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) 528e705c121SKalle Valo 529e705c121SKalle Valo /* 530e705c121SKalle Valo * Per-Tx-queue write pointer (index, really!) 531e705c121SKalle Valo * Indicates index to next TFD that driver will fill (1 past latest filled). 532e705c121SKalle Valo * Bit usage: 533e705c121SKalle Valo * 0-7: queue write index 534e705c121SKalle Valo * 11-8: queue selector 535e705c121SKalle Valo */ 536e705c121SKalle Valo #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 537e705c121SKalle Valo 538e705c121SKalle Valo /********************************************************** 539e705c121SKalle Valo * CSR values 540e705c121SKalle Valo **********************************************************/ 541e705c121SKalle Valo /* 542e705c121SKalle Valo * host interrupt timeout value 543e705c121SKalle Valo * used with setting interrupt coalescing timer 544e705c121SKalle Valo * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 545e705c121SKalle Valo * 546e705c121SKalle Valo * default interrupt coalescing timer is 64 x 32 = 2048 usecs 547e705c121SKalle Valo */ 548e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) 549e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_DEF (0x40) 550e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_MIN (0x0) 551e705c121SKalle Valo #define IWL_HOST_INT_OPER_MODE BIT(31) 552e705c121SKalle Valo 553e705c121SKalle Valo /***************************************************************************** 554e705c121SKalle Valo * 7000/3000 series SHR DTS addresses * 555e705c121SKalle Valo *****************************************************************************/ 556e705c121SKalle Valo 557e705c121SKalle Valo /* Diode Results Register Structure: */ 558e705c121SKalle Valo enum dtd_diode_reg { 559e705c121SKalle Valo DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 560e705c121SKalle Valo DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 561e705c121SKalle Valo DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 562e705c121SKalle Valo DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 563e705c121SKalle Valo DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 564e705c121SKalle Valo DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 565e705c121SKalle Valo /* Those are the masks INSIDE the flags bit-field: */ 566e705c121SKalle Valo DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 567e705c121SKalle Valo DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 568e705c121SKalle Valo DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 569e705c121SKalle Valo DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 570e705c121SKalle Valo }; 571e705c121SKalle Valo 5722e5d4a8fSHaim Dreyfuss /***************************************************************************** 5732e5d4a8fSHaim Dreyfuss * MSIX related registers * 5742e5d4a8fSHaim Dreyfuss *****************************************************************************/ 5752e5d4a8fSHaim Dreyfuss 5762e5d4a8fSHaim Dreyfuss #define CSR_MSIX_BASE (0x2000) 5772e5d4a8fSHaim Dreyfuss #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800) 5782e5d4a8fSHaim Dreyfuss #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804) 5792e5d4a8fSHaim Dreyfuss #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808) 5802e5d4a8fSHaim Dreyfuss #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C) 5812e5d4a8fSHaim Dreyfuss #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810) 5822e5d4a8fSHaim Dreyfuss #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880) 5832e5d4a8fSHaim Dreyfuss #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890) 5842e5d4a8fSHaim Dreyfuss #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000) 5852e5d4a8fSHaim Dreyfuss #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause)) 5862e5d4a8fSHaim Dreyfuss #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause)) 5872e5d4a8fSHaim Dreyfuss 5882e5d4a8fSHaim Dreyfuss #define MSIX_FH_INT_CAUSES_Q(q) (q) 5892e5d4a8fSHaim Dreyfuss 5902e5d4a8fSHaim Dreyfuss /* 5912e5d4a8fSHaim Dreyfuss * Causes for the FH register interrupts 5922e5d4a8fSHaim Dreyfuss */ 5932e5d4a8fSHaim Dreyfuss enum msix_fh_int_causes { 594496d83caSHaim Dreyfuss MSIX_FH_INT_CAUSES_Q0 = BIT(0), 595496d83caSHaim Dreyfuss MSIX_FH_INT_CAUSES_Q1 = BIT(1), 5962e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16), 5972e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17), 5982e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_S2D = BIT(19), 5992e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_FH_ERR = BIT(21), 6002e5d4a8fSHaim Dreyfuss }; 6012e5d4a8fSHaim Dreyfuss 602d4626f91SMordechay Goodstein /* The low 16 bits are for rx data queue indication */ 603d4626f91SMordechay Goodstein #define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff 604d4626f91SMordechay Goodstein 6052e5d4a8fSHaim Dreyfuss /* 6062e5d4a8fSHaim Dreyfuss * Causes for the HW register interrupts 6072e5d4a8fSHaim Dreyfuss */ 6082e5d4a8fSHaim Dreyfuss enum msix_hw_int_causes { 6092e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0), 6102e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1), 611aa7fd946SJohannes Berg MSIX_HW_INT_CAUSES_REG_IML = BIT(1), 612906d4eb8SJohannes Berg MSIX_HW_INT_CAUSES_REG_RESET_DONE = BIT(2), 613571836a0SMike Golant MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ = BIT(5), 6142e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6), 6152e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7), 6162e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8), 6172e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25), 6182e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_SCD = BIT(26), 6192e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27), 6202e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29), 6212e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_HAP = BIT(30), 6222e5d4a8fSHaim Dreyfuss }; 6232e5d4a8fSHaim Dreyfuss 6242e5d4a8fSHaim Dreyfuss #define MSIX_MIN_INTERRUPT_VECTORS 2 6252e5d4a8fSHaim Dreyfuss #define MSIX_AUTO_CLEAR_CAUSE 0 6262e5d4a8fSHaim Dreyfuss #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 6272e5d4a8fSHaim Dreyfuss 62817c867bfSSara Sharon /***************************************************************************** 62917c867bfSSara Sharon * HW address related registers * 63017c867bfSSara Sharon *****************************************************************************/ 63117c867bfSSara Sharon 6327e6dffdaSJohannes Berg #define CSR_ADDR_BASE(trans) ((trans)->cfg->mac_addr_from_csr) 6337e6dffdaSJohannes Berg #define CSR_MAC_ADDR0_OTP(trans) (CSR_ADDR_BASE(trans) + 0x00) 6347e6dffdaSJohannes Berg #define CSR_MAC_ADDR1_OTP(trans) (CSR_ADDR_BASE(trans) + 0x04) 6357e6dffdaSJohannes Berg #define CSR_MAC_ADDR0_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x08) 6367e6dffdaSJohannes Berg #define CSR_MAC_ADDR1_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x0c) 63717c867bfSSara Sharon 638e705c121SKalle Valo #endif /* !__iwl_csr_h__ */ 639