1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 102e5d4a8fSHaim Dreyfuss * Copyright(c) 2016 Intel Deutschland GmbH 11a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * You should have received a copy of the GNU General Public License 23e705c121SKalle Valo * along with this program; if not, write to the Free Software 24e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25e705c121SKalle Valo * USA 26e705c121SKalle Valo * 27e705c121SKalle Valo * The full GNU General Public License is included in this distribution 28e705c121SKalle Valo * in the file called COPYING. 29e705c121SKalle Valo * 30e705c121SKalle Valo * Contact Information: 31cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 32e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33e705c121SKalle Valo * 34e705c121SKalle Valo * BSD LICENSE 35e705c121SKalle Valo * 36e705c121SKalle Valo * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37e705c121SKalle Valo * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 38a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 39e705c121SKalle Valo * All rights reserved. 40e705c121SKalle Valo * 41e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 42e705c121SKalle Valo * modification, are permitted provided that the following conditions 43e705c121SKalle Valo * are met: 44e705c121SKalle Valo * 45e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 46e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 47e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 48e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 49e705c121SKalle Valo * the documentation and/or other materials provided with the 50e705c121SKalle Valo * distribution. 51e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 52e705c121SKalle Valo * contributors may be used to endorse or promote products derived 53e705c121SKalle Valo * from this software without specific prior written permission. 54e705c121SKalle Valo * 55e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 56e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 58e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 59e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 60e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 61e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 65e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66e705c121SKalle Valo * 67e705c121SKalle Valo *****************************************************************************/ 68e705c121SKalle Valo #ifndef __iwl_csr_h__ 69e705c121SKalle Valo #define __iwl_csr_h__ 70e705c121SKalle Valo /* 71e705c121SKalle Valo * CSR (control and status registers) 72e705c121SKalle Valo * 73e705c121SKalle Valo * CSR registers are mapped directly into PCI bus space, and are accessible 74e705c121SKalle Valo * whenever platform supplies power to device, even when device is in 75e705c121SKalle Valo * low power states due to driver-invoked device resets 76e705c121SKalle Valo * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 77e705c121SKalle Valo * 78e705c121SKalle Valo * Use iwl_write32() and iwl_read32() family to access these registers; 79e705c121SKalle Valo * these provide simple PCI bus access, without waking up the MAC. 80e705c121SKalle Valo * Do not use iwl_write_direct32() family for these registers; 81e705c121SKalle Valo * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 82e705c121SKalle Valo * The MAC (uCode processor, etc.) does not need to be powered up for accessing 83e705c121SKalle Valo * the CSR registers. 84e705c121SKalle Valo * 85e705c121SKalle Valo * NOTE: Device does need to be awake in order to read this memory 86e705c121SKalle Valo * via CSR_EEPROM and CSR_OTP registers 87e705c121SKalle Valo */ 88e705c121SKalle Valo #define CSR_BASE (0x000) 89e705c121SKalle Valo 90e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 91e705c121SKalle Valo #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 92e705c121SKalle Valo #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 93e705c121SKalle Valo #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 94e705c121SKalle Valo #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 95e705c121SKalle Valo #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 96e705c121SKalle Valo #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 97e705c121SKalle Valo #define CSR_GP_CNTRL (CSR_BASE+0x024) 98e705c121SKalle Valo 99e705c121SKalle Valo /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ 100e705c121SKalle Valo #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) 101e705c121SKalle Valo 102e705c121SKalle Valo /* 103e705c121SKalle Valo * Hardware revision info 104e705c121SKalle Valo * Bit fields: 105e705c121SKalle Valo * 31-16: Reserved 106e705c121SKalle Valo * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions 107e705c121SKalle Valo * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 108e705c121SKalle Valo * 1-0: "Dash" (-) value, as in A-1, etc. 109e705c121SKalle Valo */ 110e705c121SKalle Valo #define CSR_HW_REV (CSR_BASE+0x028) 111e705c121SKalle Valo 112e705c121SKalle Valo /* 1131afb0ae4SHaim Dreyfuss * RF ID revision info 1141afb0ae4SHaim Dreyfuss * Bit fields: 1151afb0ae4SHaim Dreyfuss * 31:24: Reserved (set to 0x0) 1161afb0ae4SHaim Dreyfuss * 23:12: Type 1171afb0ae4SHaim Dreyfuss * 11:8: Step (A - 0x0, B - 0x1, etc) 1181afb0ae4SHaim Dreyfuss * 7:4: Dash 1191afb0ae4SHaim Dreyfuss * 3:0: Flavor 1201afb0ae4SHaim Dreyfuss */ 1211afb0ae4SHaim Dreyfuss #define CSR_HW_RF_ID (CSR_BASE+0x09c) 1221afb0ae4SHaim Dreyfuss 1231afb0ae4SHaim Dreyfuss /* 124e705c121SKalle Valo * EEPROM and OTP (one-time-programmable) memory reads 125e705c121SKalle Valo * 126e705c121SKalle Valo * NOTE: Device must be awake, initialized via apm_ops.init(), 127e705c121SKalle Valo * in order to read. 128e705c121SKalle Valo */ 129e705c121SKalle Valo #define CSR_EEPROM_REG (CSR_BASE+0x02c) 130e705c121SKalle Valo #define CSR_EEPROM_GP (CSR_BASE+0x030) 131e705c121SKalle Valo #define CSR_OTP_GP_REG (CSR_BASE+0x034) 132e705c121SKalle Valo 133e705c121SKalle Valo #define CSR_GIO_REG (CSR_BASE+0x03C) 134e705c121SKalle Valo #define CSR_GP_UCODE_REG (CSR_BASE+0x048) 135e705c121SKalle Valo #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) 136e705c121SKalle Valo 137e705c121SKalle Valo /* 138e705c121SKalle Valo * UCODE-DRIVER GP (general purpose) mailbox registers. 139e705c121SKalle Valo * SET/CLR registers set/clear bit(s) if "1" is written. 140e705c121SKalle Valo */ 141e705c121SKalle Valo #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 142e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 143e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 144e705c121SKalle Valo #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 145e705c121SKalle Valo 146e705c121SKalle Valo #define CSR_MBOX_SET_REG (CSR_BASE + 0x88) 147e705c121SKalle Valo 148e705c121SKalle Valo #define CSR_LED_REG (CSR_BASE+0x094) 149e705c121SKalle Valo #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) 150e705c121SKalle Valo #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */ 1511316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20) 1521316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC) 1531316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF 154e705c121SKalle Valo 155e705c121SKalle Valo /* GIO Chicken Bits (PCI Express bus link power management) */ 156e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 157e705c121SKalle Valo 158c00ee467SJohannes Berg /* host chicken bits */ 159c00ee467SJohannes Berg #define CSR_HOST_CHICKEN (CSR_BASE + 0x204) 160c00ee467SJohannes Berg #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19) 161c00ee467SJohannes Berg 162e705c121SKalle Valo /* Analog phase-lock-loop configuration */ 163e705c121SKalle Valo #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 164e705c121SKalle Valo 165e705c121SKalle Valo /* 166e705c121SKalle Valo * CSR HW resources monitor registers 167e705c121SKalle Valo */ 168e705c121SKalle Valo #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) 169e705c121SKalle Valo #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) 170e705c121SKalle Valo #define CSR_MONITOR_XTAL_RESOURCES (0x00000010) 171e705c121SKalle Valo 172e705c121SKalle Valo /* 173e705c121SKalle Valo * CSR Hardware Revision Workaround Register. Indicates hardware rev; 174fb70d49fSLuca Coelho * "step" determines CCK backoff for txpower calculation. 175e705c121SKalle Valo * See also CSR_HW_REV register. 176e705c121SKalle Valo * Bit fields: 177e705c121SKalle Valo * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 178e705c121SKalle Valo * 1-0: "Dash" (-) value, as in C-1, etc. 179e705c121SKalle Valo */ 180e705c121SKalle Valo #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 181e705c121SKalle Valo 182e705c121SKalle Valo #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 183e705c121SKalle Valo #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) 184e705c121SKalle Valo 185e705c121SKalle Valo /* Bits for CSR_HW_IF_CONFIG_REG */ 186e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 187e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 188e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 189e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 190e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 1912d8c2615SShahar S Matityahu #define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200) 192e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 193e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 194e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 195e705c121SKalle Valo 196e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 197e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 198e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 199e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 200e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 201e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 202e705c121SKalle Valo 203e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 204e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 205e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 206e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 207e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 208e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 209e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 210e705c121SKalle Valo 211e705c121SKalle Valo #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) 212e705c121SKalle Valo 213e705c121SKalle Valo #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 214e705c121SKalle Valo #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 215e705c121SKalle Valo 216e705c121SKalle Valo /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 217e705c121SKalle Valo * acknowledged (reset) by host writing "1" to flagged bits. */ 218e705c121SKalle Valo #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 219e705c121SKalle Valo #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 220e705c121SKalle Valo #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 221e705c121SKalle Valo #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 222e705c121SKalle Valo #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 223e705c121SKalle Valo #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 224e705c121SKalle Valo #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 225e705c121SKalle Valo #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 226e705c121SKalle Valo #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 227e705c121SKalle Valo #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 228e705c121SKalle Valo #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 229e705c121SKalle Valo 230e705c121SKalle Valo #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 231e705c121SKalle Valo CSR_INT_BIT_HW_ERR | \ 232e705c121SKalle Valo CSR_INT_BIT_FH_TX | \ 233e705c121SKalle Valo CSR_INT_BIT_SW_ERR | \ 234e705c121SKalle Valo CSR_INT_BIT_RF_KILL | \ 235e705c121SKalle Valo CSR_INT_BIT_SW_RX | \ 236e705c121SKalle Valo CSR_INT_BIT_WAKEUP | \ 237e705c121SKalle Valo CSR_INT_BIT_ALIVE | \ 238e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC) 239e705c121SKalle Valo 240e705c121SKalle Valo /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 241e705c121SKalle Valo #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 242e705c121SKalle Valo #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 243e705c121SKalle Valo #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 244e705c121SKalle Valo #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 245e705c121SKalle Valo #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 246e705c121SKalle Valo #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 247e705c121SKalle Valo 248e705c121SKalle Valo #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 249e705c121SKalle Valo CSR_FH_INT_BIT_RX_CHNL1 | \ 250e705c121SKalle Valo CSR_FH_INT_BIT_RX_CHNL0) 251e705c121SKalle Valo 252e705c121SKalle Valo #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 253e705c121SKalle Valo CSR_FH_INT_BIT_TX_CHNL0) 254e705c121SKalle Valo 255e705c121SKalle Valo /* GPIO */ 256e705c121SKalle Valo #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 257e705c121SKalle Valo #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 258e705c121SKalle Valo #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 259e705c121SKalle Valo 260e705c121SKalle Valo /* RESET */ 261e705c121SKalle Valo #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 262e705c121SKalle Valo #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 263e705c121SKalle Valo #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 264e705c121SKalle Valo #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 265e705c121SKalle Valo #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 266e705c121SKalle Valo 267e705c121SKalle Valo /* 268e705c121SKalle Valo * GP (general purpose) CONTROL REGISTER 269e705c121SKalle Valo * Bit fields: 270e705c121SKalle Valo * 27: HW_RF_KILL_SW 271e705c121SKalle Valo * Indicates state of (platform's) hardware RF-Kill switch 272e705c121SKalle Valo * 26-24: POWER_SAVE_TYPE 273e705c121SKalle Valo * Indicates current power-saving mode: 274e705c121SKalle Valo * 000 -- No power saving 275e705c121SKalle Valo * 001 -- MAC power-down 276e705c121SKalle Valo * 010 -- PHY (radio) power-down 277e705c121SKalle Valo * 011 -- Error 278e705c121SKalle Valo * 10: XTAL ON request 279e705c121SKalle Valo * 9-6: SYS_CONFIG 280e705c121SKalle Valo * Indicates current system configuration, reflecting pins on chip 281e705c121SKalle Valo * as forced high/low by device circuit board. 282e705c121SKalle Valo * 4: GOING_TO_SLEEP 283e705c121SKalle Valo * Indicates MAC is entering a power-saving sleep power-down. 284e705c121SKalle Valo * Not a good time to access device-internal resources. 285e705c121SKalle Valo */ 286e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 287e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) 288e705c121SKalle Valo 289e705c121SKalle Valo #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 290ae5bb2a6SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 291e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 292e705c121SKalle Valo 293e705c121SKalle Valo 294e705c121SKalle Valo /* HW REV */ 295e705c121SKalle Valo #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 296e705c121SKalle Valo #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 297e705c121SKalle Valo 2980705b953SHaim Dreyfuss /* HW RFID */ 2990705b953SHaim Dreyfuss #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) 3000705b953SHaim Dreyfuss #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) 3010705b953SHaim Dreyfuss #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) 3020705b953SHaim Dreyfuss #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) 303e705c121SKalle Valo 304e705c121SKalle Valo /** 305e705c121SKalle Valo * hw_rev values 306e705c121SKalle Valo */ 307e705c121SKalle Valo enum { 308e705c121SKalle Valo SILICON_A_STEP = 0, 309e705c121SKalle Valo SILICON_B_STEP, 310e705c121SKalle Valo SILICON_C_STEP, 311e705c121SKalle Valo }; 312e705c121SKalle Valo 313e705c121SKalle Valo 314e705c121SKalle Valo #define CSR_HW_REV_TYPE_MSK (0x000FFF0) 315e705c121SKalle Valo #define CSR_HW_REV_TYPE_5300 (0x0000020) 316e705c121SKalle Valo #define CSR_HW_REV_TYPE_5350 (0x0000030) 317e705c121SKalle Valo #define CSR_HW_REV_TYPE_5100 (0x0000050) 318e705c121SKalle Valo #define CSR_HW_REV_TYPE_5150 (0x0000040) 319e705c121SKalle Valo #define CSR_HW_REV_TYPE_1000 (0x0000060) 320e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x00 (0x0000070) 321e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x50 (0x0000080) 322e705c121SKalle Valo #define CSR_HW_REV_TYPE_6150 (0x0000084) 323e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x05 (0x00000B0) 324e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 325e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 326e705c121SKalle Valo #define CSR_HW_REV_TYPE_2x30 (0x00000C0) 327e705c121SKalle Valo #define CSR_HW_REV_TYPE_2x00 (0x0000100) 328e705c121SKalle Valo #define CSR_HW_REV_TYPE_105 (0x0000110) 329e705c121SKalle Valo #define CSR_HW_REV_TYPE_135 (0x0000120) 330e705c121SKalle Valo #define CSR_HW_REV_TYPE_7265D (0x0000210) 331e705c121SKalle Valo #define CSR_HW_REV_TYPE_NONE (0x00001F0) 3325f19d6ddSTzipi Peres #define CSR_HW_REV_TYPE_QNJ (0x0000360) 3335f19d6ddSTzipi Peres #define CSR_HW_REV_TYPE_HR_CDB (0x0000340) 334e705c121SKalle Valo 3351afb0ae4SHaim Dreyfuss /* RF_ID value */ 33636ae4f3aSLiad Kaufman #define CSR_HW_RF_ID_TYPE_JF (0x00105100) 337a85281ebSSara Sharon #define CSR_HW_RF_ID_TYPE_HR (0x0010A000) 3385f19d6ddSTzipi Peres #define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00) 3395f19d6ddSTzipi Peres 3405f19d6ddSTzipi Peres /* HW_RF CHIP ID */ 3415f19d6ddSTzipi Peres #define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF) 3421afb0ae4SHaim Dreyfuss 34333708052SLuca Coelho /* HW_RF CHIP STEP */ 34433708052SLuca Coelho #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF) 34533708052SLuca Coelho 346e705c121SKalle Valo /* EEPROM REG */ 347e705c121SKalle Valo #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 348e705c121SKalle Valo #define CSR_EEPROM_REG_BIT_CMD (0x00000002) 349e705c121SKalle Valo #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 350e705c121SKalle Valo #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 351e705c121SKalle Valo 352e705c121SKalle Valo /* EEPROM GP */ 353e705c121SKalle Valo #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 354e705c121SKalle Valo #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 355e705c121SKalle Valo #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 356e705c121SKalle Valo #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 357e705c121SKalle Valo #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 358e705c121SKalle Valo #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 359e705c121SKalle Valo 360e705c121SKalle Valo /* One-time-programmable memory general purpose reg */ 361e705c121SKalle Valo #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 362e705c121SKalle Valo #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 363e705c121SKalle Valo #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 364e705c121SKalle Valo #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 365e705c121SKalle Valo 366e705c121SKalle Valo /* GP REG */ 367e705c121SKalle Valo #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 368e705c121SKalle Valo #define CSR_GP_REG_NO_POWER_SAVE (0x00000000) 369e705c121SKalle Valo #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 370e705c121SKalle Valo #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 371e705c121SKalle Valo #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 372e705c121SKalle Valo 373e705c121SKalle Valo 374e705c121SKalle Valo /* CSR GIO */ 375e705c121SKalle Valo #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 376e705c121SKalle Valo 377e705c121SKalle Valo /* 378e705c121SKalle Valo * UCODE-DRIVER GP (general purpose) mailbox register 1 379e705c121SKalle Valo * Host driver and uCode write and/or read this register to communicate with 380e705c121SKalle Valo * each other. 381e705c121SKalle Valo * Bit fields: 382e705c121SKalle Valo * 4: UCODE_DISABLE 383e705c121SKalle Valo * Host sets this to request permanent halt of uCode, same as 384e705c121SKalle Valo * sending CARD_STATE command with "halt" bit set. 385e705c121SKalle Valo * 3: CT_KILL_EXIT 386e705c121SKalle Valo * Host sets this to request exit from CT_KILL state, i.e. host thinks 387e705c121SKalle Valo * device temperature is low enough to continue normal operation. 388e705c121SKalle Valo * 2: CMD_BLOCKED 389e705c121SKalle Valo * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 390e705c121SKalle Valo * to release uCode to clear all Tx and command queues, enter 391e705c121SKalle Valo * unassociated mode, and power down. 392e705c121SKalle Valo * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 393e705c121SKalle Valo * 1: SW_BIT_RFKILL 394e705c121SKalle Valo * Host sets this when issuing CARD_STATE command to request 395e705c121SKalle Valo * device sleep. 396e705c121SKalle Valo * 0: MAC_SLEEP 397e705c121SKalle Valo * uCode sets this when preparing a power-saving power-down. 398e705c121SKalle Valo * uCode resets this when power-up is complete and SRAM is sane. 399e705c121SKalle Valo * NOTE: device saves internal SRAM data to host when powering down, 400e705c121SKalle Valo * and must restore this data after powering back up. 401e705c121SKalle Valo * MAC_SLEEP is the best indication that restore is complete. 402e705c121SKalle Valo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 403e705c121SKalle Valo * do not need to save/restore it. 404e705c121SKalle Valo */ 405e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 406e705c121SKalle Valo #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 407e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 408e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 409e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 410e705c121SKalle Valo 411e705c121SKalle Valo /* GP Driver */ 412e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 413e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 414e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 415e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 416e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 417e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 418e705c121SKalle Valo 419e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 420e705c121SKalle Valo 421e705c121SKalle Valo /* GIO Chicken Bits (PCI Express bus link power management) */ 422e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 423e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 424e705c121SKalle Valo 425e705c121SKalle Valo /* LED */ 426e705c121SKalle Valo #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 427e705c121SKalle Valo #define CSR_LED_REG_TURN_ON (0x60) 428e705c121SKalle Valo #define CSR_LED_REG_TURN_OFF (0x20) 429e705c121SKalle Valo 430e705c121SKalle Valo /* ANA_PLL */ 431e705c121SKalle Valo #define CSR50_ANA_PLL_CFG_VAL (0x00880300) 432e705c121SKalle Valo 433e705c121SKalle Valo /* HPET MEM debug */ 434e705c121SKalle Valo #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 435e705c121SKalle Valo 436e705c121SKalle Valo /* DRAM INT TABLE */ 437e705c121SKalle Valo #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) 438e705c121SKalle Valo #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 439e705c121SKalle Valo #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 440e705c121SKalle Valo 441e705c121SKalle Valo /* 442e705c121SKalle Valo * SHR target access (Shared block memory space) 443e705c121SKalle Valo * 444e705c121SKalle Valo * Shared internal registers can be accessed directly from PCI bus through SHR 445e705c121SKalle Valo * arbiter without need for the MAC HW to be powered up. This is possible due to 446e705c121SKalle Valo * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and 447e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. 448e705c121SKalle Valo * 449e705c121SKalle Valo * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW 450e705c121SKalle Valo * need not be powered up so no "grab inc access" is required. 451e705c121SKalle Valo */ 452e705c121SKalle Valo 453e705c121SKalle Valo /* 454e705c121SKalle Valo * Registers for accessing shared registers (e.g. SHR_APMG_GP1, 455e705c121SKalle Valo * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), 456e705c121SKalle Valo * first, write to the control register: 457e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 458e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) 459e705c121SKalle Valo * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. 460e705c121SKalle Valo * 461e705c121SKalle Valo * To write the register, first, write to the data register 462e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: 463e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 464e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) 465e705c121SKalle Valo */ 466e705c121SKalle Valo #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) 467e705c121SKalle Valo #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) 468e705c121SKalle Valo 469e705c121SKalle Valo /* 470e705c121SKalle Valo * HBUS (Host-side Bus) 471e705c121SKalle Valo * 472e705c121SKalle Valo * HBUS registers are mapped directly into PCI bus space, but are used 473e705c121SKalle Valo * to indirectly access device's internal memory or registers that 474e705c121SKalle Valo * may be powered-down. 475e705c121SKalle Valo * 476e705c121SKalle Valo * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 477e705c121SKalle Valo * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 478e705c121SKalle Valo * to make sure the MAC (uCode processor, etc.) is powered up for accessing 479e705c121SKalle Valo * internal resources. 480e705c121SKalle Valo * 481e705c121SKalle Valo * Do not use iwl_write32()/iwl_read32() family to access these registers; 482e705c121SKalle Valo * these provide only simple PCI bus access, without waking up the MAC. 483e705c121SKalle Valo */ 484e705c121SKalle Valo #define HBUS_BASE (0x400) 485e705c121SKalle Valo 486e705c121SKalle Valo /* 487e705c121SKalle Valo * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 488e705c121SKalle Valo * structures, error log, event log, verifying uCode load). 489e705c121SKalle Valo * First write to address register, then read from or write to data register 490e705c121SKalle Valo * to complete the job. Once the address register is set up, accesses to 491e705c121SKalle Valo * data registers auto-increment the address by one dword. 492e705c121SKalle Valo * Bit usage for address registers (read or write): 493e705c121SKalle Valo * 0-31: memory address within device 494e705c121SKalle Valo */ 495e705c121SKalle Valo #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 496e705c121SKalle Valo #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 497e705c121SKalle Valo #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 498e705c121SKalle Valo #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 499e705c121SKalle Valo 500e705c121SKalle Valo /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 501e705c121SKalle Valo #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 502e705c121SKalle Valo #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 503e705c121SKalle Valo 504e705c121SKalle Valo /* 505e705c121SKalle Valo * Registers for accessing device's internal peripheral registers 506e705c121SKalle Valo * (e.g. SCD, BSM, etc.). First write to address register, 507e705c121SKalle Valo * then read from or write to data register to complete the job. 508e705c121SKalle Valo * Bit usage for address registers (read or write): 509e705c121SKalle Valo * 0-15: register address (offset) within device 510e705c121SKalle Valo * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 511e705c121SKalle Valo */ 512e705c121SKalle Valo #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 513e705c121SKalle Valo #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 514e705c121SKalle Valo #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 515e705c121SKalle Valo #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 516e705c121SKalle Valo 517e705c121SKalle Valo /* Used to enable DBGM */ 518e705c121SKalle Valo #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) 519e705c121SKalle Valo 520e705c121SKalle Valo /* 521e705c121SKalle Valo * Per-Tx-queue write pointer (index, really!) 522e705c121SKalle Valo * Indicates index to next TFD that driver will fill (1 past latest filled). 523e705c121SKalle Valo * Bit usage: 524e705c121SKalle Valo * 0-7: queue write index 525e705c121SKalle Valo * 11-8: queue selector 526e705c121SKalle Valo */ 527e705c121SKalle Valo #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 528e705c121SKalle Valo 529e705c121SKalle Valo /********************************************************** 530e705c121SKalle Valo * CSR values 531e705c121SKalle Valo **********************************************************/ 532e705c121SKalle Valo /* 533e705c121SKalle Valo * host interrupt timeout value 534e705c121SKalle Valo * used with setting interrupt coalescing timer 535e705c121SKalle Valo * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 536e705c121SKalle Valo * 537e705c121SKalle Valo * default interrupt coalescing timer is 64 x 32 = 2048 usecs 538e705c121SKalle Valo */ 539e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) 540e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_DEF (0x40) 541e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_MIN (0x0) 542e705c121SKalle Valo #define IWL_HOST_INT_OPER_MODE BIT(31) 543e705c121SKalle Valo 544e705c121SKalle Valo /***************************************************************************** 545e705c121SKalle Valo * 7000/3000 series SHR DTS addresses * 546e705c121SKalle Valo *****************************************************************************/ 547e705c121SKalle Valo 548e705c121SKalle Valo /* Diode Results Register Structure: */ 549e705c121SKalle Valo enum dtd_diode_reg { 550e705c121SKalle Valo DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 551e705c121SKalle Valo DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 552e705c121SKalle Valo DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 553e705c121SKalle Valo DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 554e705c121SKalle Valo DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 555e705c121SKalle Valo DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 556e705c121SKalle Valo /* Those are the masks INSIDE the flags bit-field: */ 557e705c121SKalle Valo DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 558e705c121SKalle Valo DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 559e705c121SKalle Valo DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 560e705c121SKalle Valo DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 561e705c121SKalle Valo }; 562e705c121SKalle Valo 5632e5d4a8fSHaim Dreyfuss /***************************************************************************** 5642e5d4a8fSHaim Dreyfuss * MSIX related registers * 5652e5d4a8fSHaim Dreyfuss *****************************************************************************/ 5662e5d4a8fSHaim Dreyfuss 5672e5d4a8fSHaim Dreyfuss #define CSR_MSIX_BASE (0x2000) 5682e5d4a8fSHaim Dreyfuss #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800) 5692e5d4a8fSHaim Dreyfuss #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804) 5702e5d4a8fSHaim Dreyfuss #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808) 5712e5d4a8fSHaim Dreyfuss #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C) 5722e5d4a8fSHaim Dreyfuss #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810) 5732e5d4a8fSHaim Dreyfuss #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880) 5742e5d4a8fSHaim Dreyfuss #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890) 5752e5d4a8fSHaim Dreyfuss #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000) 5762e5d4a8fSHaim Dreyfuss #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause)) 5772e5d4a8fSHaim Dreyfuss #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause)) 5782e5d4a8fSHaim Dreyfuss 5792e5d4a8fSHaim Dreyfuss #define MSIX_FH_INT_CAUSES_Q(q) (q) 5802e5d4a8fSHaim Dreyfuss 5812e5d4a8fSHaim Dreyfuss /* 5822e5d4a8fSHaim Dreyfuss * Causes for the FH register interrupts 5832e5d4a8fSHaim Dreyfuss */ 5842e5d4a8fSHaim Dreyfuss enum msix_fh_int_causes { 585496d83caSHaim Dreyfuss MSIX_FH_INT_CAUSES_Q0 = BIT(0), 586496d83caSHaim Dreyfuss MSIX_FH_INT_CAUSES_Q1 = BIT(1), 5872e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16), 5882e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17), 5892e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_S2D = BIT(19), 5902e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_FH_ERR = BIT(21), 5912e5d4a8fSHaim Dreyfuss }; 5922e5d4a8fSHaim Dreyfuss 5932e5d4a8fSHaim Dreyfuss /* 5942e5d4a8fSHaim Dreyfuss * Causes for the HW register interrupts 5952e5d4a8fSHaim Dreyfuss */ 5962e5d4a8fSHaim Dreyfuss enum msix_hw_int_causes { 5972e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0), 5982e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1), 5999b58419eSGolan Ben Ami MSIX_HW_INT_CAUSES_REG_IPC = BIT(1), 6009b58419eSGolan Ben Ami MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = BIT(5), 6012e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6), 6022e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7), 6032e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8), 6042e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25), 6052e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_SCD = BIT(26), 6062e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27), 6072e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29), 6082e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_HAP = BIT(30), 6092e5d4a8fSHaim Dreyfuss }; 6102e5d4a8fSHaim Dreyfuss 6112e5d4a8fSHaim Dreyfuss #define MSIX_MIN_INTERRUPT_VECTORS 2 6122e5d4a8fSHaim Dreyfuss #define MSIX_AUTO_CLEAR_CAUSE 0 6132e5d4a8fSHaim Dreyfuss #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 6142e5d4a8fSHaim Dreyfuss 61517c867bfSSara Sharon /***************************************************************************** 61617c867bfSSara Sharon * HW address related registers * 61717c867bfSSara Sharon *****************************************************************************/ 61817c867bfSSara Sharon 61917c867bfSSara Sharon #define CSR_ADDR_BASE (0x380) 62017c867bfSSara Sharon #define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE) 62117c867bfSSara Sharon #define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4) 62217c867bfSSara Sharon #define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8) 62317c867bfSSara Sharon #define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC) 62417c867bfSSara Sharon 625e705c121SKalle Valo #endif /* !__iwl_csr_h__ */ 626