18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 28e99ea8dSJohannes Berg /* 3*163c3615SJohannes Berg * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2014 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #ifndef __iwl_csr_h__ 8e705c121SKalle Valo #define __iwl_csr_h__ 9e705c121SKalle Valo /* 10e705c121SKalle Valo * CSR (control and status registers) 11e705c121SKalle Valo * 12e705c121SKalle Valo * CSR registers are mapped directly into PCI bus space, and are accessible 13e705c121SKalle Valo * whenever platform supplies power to device, even when device is in 14e705c121SKalle Valo * low power states due to driver-invoked device resets 15e705c121SKalle Valo * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 16e705c121SKalle Valo * 17e705c121SKalle Valo * Use iwl_write32() and iwl_read32() family to access these registers; 18e705c121SKalle Valo * these provide simple PCI bus access, without waking up the MAC. 19e705c121SKalle Valo * Do not use iwl_write_direct32() family for these registers; 20e705c121SKalle Valo * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 21e705c121SKalle Valo * The MAC (uCode processor, etc.) does not need to be powered up for accessing 22e705c121SKalle Valo * the CSR registers. 23e705c121SKalle Valo * 24e705c121SKalle Valo * NOTE: Device does need to be awake in order to read this memory 25e705c121SKalle Valo * via CSR_EEPROM and CSR_OTP registers 26e705c121SKalle Valo */ 27e705c121SKalle Valo #define CSR_BASE (0x000) 28e705c121SKalle Valo 29e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 30e705c121SKalle Valo #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 31e705c121SKalle Valo #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 32e705c121SKalle Valo #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 33e705c121SKalle Valo #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ 34e705c121SKalle Valo #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 35e705c121SKalle Valo #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ 36e705c121SKalle Valo #define CSR_GP_CNTRL (CSR_BASE+0x024) 37e705c121SKalle Valo 38e705c121SKalle Valo /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ 39e705c121SKalle Valo #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) 40e705c121SKalle Valo 41e705c121SKalle Valo /* 42e705c121SKalle Valo * Hardware revision info 43e705c121SKalle Valo * Bit fields: 44e705c121SKalle Valo * 31-16: Reserved 45e705c121SKalle Valo * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions 46e705c121SKalle Valo * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 47e705c121SKalle Valo * 1-0: "Dash" (-) value, as in A-1, etc. 48e705c121SKalle Valo */ 49e705c121SKalle Valo #define CSR_HW_REV (CSR_BASE+0x028) 50e705c121SKalle Valo 51e705c121SKalle Valo /* 521afb0ae4SHaim Dreyfuss * RF ID revision info 531afb0ae4SHaim Dreyfuss * Bit fields: 541afb0ae4SHaim Dreyfuss * 31:24: Reserved (set to 0x0) 551afb0ae4SHaim Dreyfuss * 23:12: Type 561afb0ae4SHaim Dreyfuss * 11:8: Step (A - 0x0, B - 0x1, etc) 571afb0ae4SHaim Dreyfuss * 7:4: Dash 581afb0ae4SHaim Dreyfuss * 3:0: Flavor 591afb0ae4SHaim Dreyfuss */ 601afb0ae4SHaim Dreyfuss #define CSR_HW_RF_ID (CSR_BASE+0x09c) 611afb0ae4SHaim Dreyfuss 621afb0ae4SHaim Dreyfuss /* 63e705c121SKalle Valo * EEPROM and OTP (one-time-programmable) memory reads 64e705c121SKalle Valo * 65e705c121SKalle Valo * NOTE: Device must be awake, initialized via apm_ops.init(), 66e705c121SKalle Valo * in order to read. 67e705c121SKalle Valo */ 68e705c121SKalle Valo #define CSR_EEPROM_REG (CSR_BASE+0x02c) 69e705c121SKalle Valo #define CSR_EEPROM_GP (CSR_BASE+0x030) 70e705c121SKalle Valo #define CSR_OTP_GP_REG (CSR_BASE+0x034) 71e705c121SKalle Valo 72e705c121SKalle Valo #define CSR_GIO_REG (CSR_BASE+0x03C) 73e705c121SKalle Valo #define CSR_GP_UCODE_REG (CSR_BASE+0x048) 74e705c121SKalle Valo #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) 75e705c121SKalle Valo 76e705c121SKalle Valo /* 77e705c121SKalle Valo * UCODE-DRIVER GP (general purpose) mailbox registers. 78e705c121SKalle Valo * SET/CLR registers set/clear bit(s) if "1" is written. 79e705c121SKalle Valo */ 80e705c121SKalle Valo #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 81e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 82e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 83e705c121SKalle Valo #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 84e705c121SKalle Valo 85e705c121SKalle Valo #define CSR_MBOX_SET_REG (CSR_BASE + 0x88) 86e705c121SKalle Valo 87e705c121SKalle Valo #define CSR_LED_REG (CSR_BASE+0x094) 88e705c121SKalle Valo #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) 89e705c121SKalle Valo #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */ 901316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20) 911316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC) 921316d595SSara Sharon #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF 93e705c121SKalle Valo 94edb62520SJohannes Berg /* LTR control (since IWL_DEVICE_FAMILY_22000) */ 95edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4) 96edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000 97edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE 0x1c000000 98edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL 0x03ff0000 99edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000 100edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE 0x00001c00 101edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff 102edb62520SJohannes Berg #define CSR_LTR_LONG_VAL_AD_SCALE_USEC 2 103edb62520SJohannes Berg 104e705c121SKalle Valo /* GIO Chicken Bits (PCI Express bus link power management) */ 105e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 106e705c121SKalle Valo 107c00ee467SJohannes Berg /* host chicken bits */ 108c00ee467SJohannes Berg #define CSR_HOST_CHICKEN (CSR_BASE + 0x204) 109c00ee467SJohannes Berg #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19) 110c00ee467SJohannes Berg 111e705c121SKalle Valo /* Analog phase-lock-loop configuration */ 112e705c121SKalle Valo #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 113e705c121SKalle Valo 114e705c121SKalle Valo /* 115e705c121SKalle Valo * CSR HW resources monitor registers 116e705c121SKalle Valo */ 117e705c121SKalle Valo #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) 118e705c121SKalle Valo #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) 119e705c121SKalle Valo #define CSR_MONITOR_XTAL_RESOURCES (0x00000010) 120e705c121SKalle Valo 121e705c121SKalle Valo /* 122e705c121SKalle Valo * CSR Hardware Revision Workaround Register. Indicates hardware rev; 123fb70d49fSLuca Coelho * "step" determines CCK backoff for txpower calculation. 124e705c121SKalle Valo * See also CSR_HW_REV register. 125e705c121SKalle Valo * Bit fields: 126e705c121SKalle Valo * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 127e705c121SKalle Valo * 1-0: "Dash" (-) value, as in C-1, etc. 128e705c121SKalle Valo */ 129e705c121SKalle Valo #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 130e705c121SKalle Valo 131e705c121SKalle Valo #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 132e705c121SKalle Valo #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) 133e705c121SKalle Valo 134e705c121SKalle Valo /* Bits for CSR_HW_IF_CONFIG_REG */ 135e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 136e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 137e41e2c26SShahar S Matityahu #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080) 138e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 139e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 140e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 1412d8c2615SShahar S Matityahu #define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200) 142e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 143e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 144e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 145e705c121SKalle Valo 146e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 147e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 148e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 149e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 150e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 151e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 152e705c121SKalle Valo 153e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 154e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 155e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 156e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 157e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 158e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 159e705c121SKalle Valo #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 160e705c121SKalle Valo 161e705c121SKalle Valo #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) 162e705c121SKalle Valo 163e705c121SKalle Valo #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 164e705c121SKalle Valo #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 165e705c121SKalle Valo 166e705c121SKalle Valo /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 167e705c121SKalle Valo * acknowledged (reset) by host writing "1" to flagged bits. */ 168e705c121SKalle Valo #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 169e705c121SKalle Valo #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 170e705c121SKalle Valo #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 171e705c121SKalle Valo #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 172e705c121SKalle Valo #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 173e705c121SKalle Valo #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 174e705c121SKalle Valo #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 175e705c121SKalle Valo #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 176e705c121SKalle Valo #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 177e705c121SKalle Valo #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 178e705c121SKalle Valo #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 179e705c121SKalle Valo 180e705c121SKalle Valo #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 181e705c121SKalle Valo CSR_INT_BIT_HW_ERR | \ 182e705c121SKalle Valo CSR_INT_BIT_FH_TX | \ 183e705c121SKalle Valo CSR_INT_BIT_SW_ERR | \ 184e705c121SKalle Valo CSR_INT_BIT_RF_KILL | \ 185e705c121SKalle Valo CSR_INT_BIT_SW_RX | \ 186e705c121SKalle Valo CSR_INT_BIT_WAKEUP | \ 187e705c121SKalle Valo CSR_INT_BIT_ALIVE | \ 188e705c121SKalle Valo CSR_INT_BIT_RX_PERIODIC) 189e705c121SKalle Valo 190e705c121SKalle Valo /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 191e705c121SKalle Valo #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 192e705c121SKalle Valo #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 193e705c121SKalle Valo #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 194e705c121SKalle Valo #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 195e705c121SKalle Valo #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 196e705c121SKalle Valo #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 197e705c121SKalle Valo 198e705c121SKalle Valo #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 199e705c121SKalle Valo CSR_FH_INT_BIT_RX_CHNL1 | \ 200e705c121SKalle Valo CSR_FH_INT_BIT_RX_CHNL0) 201e705c121SKalle Valo 202e705c121SKalle Valo #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ 203e705c121SKalle Valo CSR_FH_INT_BIT_TX_CHNL0) 204e705c121SKalle Valo 205e705c121SKalle Valo /* GPIO */ 206e705c121SKalle Valo #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 207e705c121SKalle Valo #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 208e705c121SKalle Valo #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 209e705c121SKalle Valo 210e705c121SKalle Valo /* RESET */ 211e705c121SKalle Valo #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 212e705c121SKalle Valo #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 2136dece0e9SLuca Coelho #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 214e705c121SKalle Valo #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 215e705c121SKalle Valo #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 216e705c121SKalle Valo #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 217e705c121SKalle Valo 218e705c121SKalle Valo /* 219e705c121SKalle Valo * GP (general purpose) CONTROL REGISTER 220e705c121SKalle Valo * Bit fields: 221e705c121SKalle Valo * 27: HW_RF_KILL_SW 222e705c121SKalle Valo * Indicates state of (platform's) hardware RF-Kill switch 223e705c121SKalle Valo * 26-24: POWER_SAVE_TYPE 224e705c121SKalle Valo * Indicates current power-saving mode: 225e705c121SKalle Valo * 000 -- No power saving 226e705c121SKalle Valo * 001 -- MAC power-down 227e705c121SKalle Valo * 010 -- PHY (radio) power-down 228e705c121SKalle Valo * 011 -- Error 229e705c121SKalle Valo * 10: XTAL ON request 230e705c121SKalle Valo * 9-6: SYS_CONFIG 231e705c121SKalle Valo * Indicates current system configuration, reflecting pins on chip 232e705c121SKalle Valo * as forced high/low by device circuit board. 233e705c121SKalle Valo * 4: GOING_TO_SLEEP 234e705c121SKalle Valo * Indicates MAC is entering a power-saving sleep power-down. 235e705c121SKalle Valo * Not a good time to access device-internal resources. 2366dece0e9SLuca Coelho * 3: MAC_ACCESS_REQ 2376dece0e9SLuca Coelho * Host sets this to request and maintain MAC wakeup, to allow host 2386dece0e9SLuca Coelho * access to device-internal resources. Host must wait for 2396dece0e9SLuca Coelho * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 2406dece0e9SLuca Coelho * device registers. 2416dece0e9SLuca Coelho * 2: INIT_DONE 2426dece0e9SLuca Coelho * Host sets this to put device into fully operational D0 power mode. 2436dece0e9SLuca Coelho * Host resets this after SW_RESET to put device into low power mode. 2446dece0e9SLuca Coelho * 0: MAC_CLOCK_READY 2456dece0e9SLuca Coelho * Indicates MAC (ucode processor, etc.) is powered up and can run. 2466dece0e9SLuca Coelho * Internal resources are accessible. 2476dece0e9SLuca Coelho * NOTE: This does not indicate that the processor is actually running. 2486dece0e9SLuca Coelho * NOTE: This does not indicate that device has completed 2496dece0e9SLuca Coelho * init or post-power-down restore of internal SRAM memory. 2506dece0e9SLuca Coelho * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 2516dece0e9SLuca Coelho * SRAM is restored and uCode is in normal operation mode. 2526dece0e9SLuca Coelho * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 2536dece0e9SLuca Coelho * do not need to save/restore it. 2546dece0e9SLuca Coelho * NOTE: After device reset, this bit remains "0" until host sets 2556dece0e9SLuca Coelho * INIT_DONE 256e705c121SKalle Valo */ 2576dece0e9SLuca Coelho #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 2589a47cb98SLuca Coelho #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 2596dece0e9SLuca Coelho #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 260e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 261e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) 262e705c121SKalle Valo 2636dece0e9SLuca Coelho #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 2646dece0e9SLuca Coelho 265e705c121SKalle Valo #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 266ae5bb2a6SJohannes Berg #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 267e705c121SKalle Valo #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 268e705c121SKalle Valo 269e705c121SKalle Valo 270e705c121SKalle Valo /* HW REV */ 271e705c121SKalle Valo #define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 272e705c121SKalle Valo #define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 273391481adSShahar S Matityahu #define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) 274e705c121SKalle Valo 2750705b953SHaim Dreyfuss /* HW RFID */ 2760705b953SHaim Dreyfuss #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) 2770705b953SHaim Dreyfuss #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) 2780705b953SHaim Dreyfuss #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) 2790705b953SHaim Dreyfuss #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) 280b964bfd0SMatti Gottlieb #define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) 281b964bfd0SMatti Gottlieb #define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) 282e705c121SKalle Valo 283e705c121SKalle Valo /** 284e705c121SKalle Valo * hw_rev values 285e705c121SKalle Valo */ 286e705c121SKalle Valo enum { 287e705c121SKalle Valo SILICON_A_STEP = 0, 288e705c121SKalle Valo SILICON_B_STEP, 289e705c121SKalle Valo SILICON_C_STEP, 290e705c121SKalle Valo }; 291e705c121SKalle Valo 292e705c121SKalle Valo 293e705c121SKalle Valo #define CSR_HW_REV_TYPE_MSK (0x000FFF0) 294e705c121SKalle Valo #define CSR_HW_REV_TYPE_5300 (0x0000020) 295e705c121SKalle Valo #define CSR_HW_REV_TYPE_5350 (0x0000030) 296e705c121SKalle Valo #define CSR_HW_REV_TYPE_5100 (0x0000050) 297e705c121SKalle Valo #define CSR_HW_REV_TYPE_5150 (0x0000040) 298e705c121SKalle Valo #define CSR_HW_REV_TYPE_1000 (0x0000060) 299e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x00 (0x0000070) 300e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x50 (0x0000080) 301e705c121SKalle Valo #define CSR_HW_REV_TYPE_6150 (0x0000084) 302e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x05 (0x00000B0) 303e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 304e705c121SKalle Valo #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 305e705c121SKalle Valo #define CSR_HW_REV_TYPE_2x30 (0x00000C0) 306e705c121SKalle Valo #define CSR_HW_REV_TYPE_2x00 (0x0000100) 307e705c121SKalle Valo #define CSR_HW_REV_TYPE_105 (0x0000110) 308e705c121SKalle Valo #define CSR_HW_REV_TYPE_135 (0x0000120) 309e705c121SKalle Valo #define CSR_HW_REV_TYPE_7265D (0x0000210) 310e705c121SKalle Valo #define CSR_HW_REV_TYPE_NONE (0x00001F0) 3115f19d6ddSTzipi Peres #define CSR_HW_REV_TYPE_QNJ (0x0000360) 31299be6166SLuca Coelho #define CSR_HW_REV_TYPE_QNJ_B0 (0x0000364) 313a7d544d6SLuca Coelho #define CSR_HW_REV_TYPE_QU_B0 (0x0000334) 314a7d544d6SLuca Coelho #define CSR_HW_REV_TYPE_QU_C0 (0x0000338) 315debec2f2SLuca Coelho #define CSR_HW_REV_TYPE_QUZ (0x0000354) 3165f19d6ddSTzipi Peres #define CSR_HW_REV_TYPE_HR_CDB (0x0000340) 317ff911dcaSShaul Triebitz #define CSR_HW_REV_TYPE_SO (0x0000370) 318ff911dcaSShaul Triebitz #define CSR_HW_REV_TYPE_TY (0x0000420) 319e705c121SKalle Valo 3201afb0ae4SHaim Dreyfuss /* RF_ID value */ 32136ae4f3aSLiad Kaufman #define CSR_HW_RF_ID_TYPE_JF (0x00105100) 322a85281ebSSara Sharon #define CSR_HW_RF_ID_TYPE_HR (0x0010A000) 323498d3eb5SOren Givon #define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100) 3245f19d6ddSTzipi Peres #define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00) 325ff911dcaSShaul Triebitz #define CSR_HW_RF_ID_TYPE_GF (0x0010D000) 3265bd757a6SShaul Triebitz #define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000) 3275f19d6ddSTzipi Peres 32833708052SLuca Coelho /* HW_RF CHIP STEP */ 32933708052SLuca Coelho #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF) 33033708052SLuca Coelho 331e705c121SKalle Valo /* EEPROM REG */ 332e705c121SKalle Valo #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 333e705c121SKalle Valo #define CSR_EEPROM_REG_BIT_CMD (0x00000002) 334e705c121SKalle Valo #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 335e705c121SKalle Valo #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 336e705c121SKalle Valo 337e705c121SKalle Valo /* EEPROM GP */ 338e705c121SKalle Valo #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 339e705c121SKalle Valo #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 340e705c121SKalle Valo #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 341e705c121SKalle Valo #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 342e705c121SKalle Valo #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 343e705c121SKalle Valo #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 344e705c121SKalle Valo 345e705c121SKalle Valo /* One-time-programmable memory general purpose reg */ 346e705c121SKalle Valo #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 347e705c121SKalle Valo #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 348e705c121SKalle Valo #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 349e705c121SKalle Valo #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 350e705c121SKalle Valo 351e705c121SKalle Valo /* GP REG */ 352e705c121SKalle Valo #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 353e705c121SKalle Valo #define CSR_GP_REG_NO_POWER_SAVE (0x00000000) 354e705c121SKalle Valo #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 355e705c121SKalle Valo #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 356e705c121SKalle Valo #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 357e705c121SKalle Valo 358e705c121SKalle Valo 359e705c121SKalle Valo /* CSR GIO */ 3603d1b28fdSLuca Coelho #define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) 361e705c121SKalle Valo 362e705c121SKalle Valo /* 363e705c121SKalle Valo * UCODE-DRIVER GP (general purpose) mailbox register 1 364e705c121SKalle Valo * Host driver and uCode write and/or read this register to communicate with 365e705c121SKalle Valo * each other. 366e705c121SKalle Valo * Bit fields: 367e705c121SKalle Valo * 4: UCODE_DISABLE 368e705c121SKalle Valo * Host sets this to request permanent halt of uCode, same as 369e705c121SKalle Valo * sending CARD_STATE command with "halt" bit set. 370e705c121SKalle Valo * 3: CT_KILL_EXIT 371e705c121SKalle Valo * Host sets this to request exit from CT_KILL state, i.e. host thinks 372e705c121SKalle Valo * device temperature is low enough to continue normal operation. 373e705c121SKalle Valo * 2: CMD_BLOCKED 374e705c121SKalle Valo * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 375e705c121SKalle Valo * to release uCode to clear all Tx and command queues, enter 376e705c121SKalle Valo * unassociated mode, and power down. 377e705c121SKalle Valo * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 378e705c121SKalle Valo * 1: SW_BIT_RFKILL 379e705c121SKalle Valo * Host sets this when issuing CARD_STATE command to request 380e705c121SKalle Valo * device sleep. 381e705c121SKalle Valo * 0: MAC_SLEEP 382e705c121SKalle Valo * uCode sets this when preparing a power-saving power-down. 383e705c121SKalle Valo * uCode resets this when power-up is complete and SRAM is sane. 384e705c121SKalle Valo * NOTE: device saves internal SRAM data to host when powering down, 385e705c121SKalle Valo * and must restore this data after powering back up. 386e705c121SKalle Valo * MAC_SLEEP is the best indication that restore is complete. 387e705c121SKalle Valo * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 388e705c121SKalle Valo * do not need to save/restore it. 389e705c121SKalle Valo */ 390e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 391e705c121SKalle Valo #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 392e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 393e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 394e705c121SKalle Valo #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 395e705c121SKalle Valo 396e705c121SKalle Valo /* GP Driver */ 397e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 398e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 399e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 400e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 401e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 402e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 403e705c121SKalle Valo 404e705c121SKalle Valo #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 405e705c121SKalle Valo 406e705c121SKalle Valo /* GIO Chicken Bits (PCI Express bus link power management) */ 407e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 408e705c121SKalle Valo #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 409e705c121SKalle Valo 410e705c121SKalle Valo /* LED */ 411e705c121SKalle Valo #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 412e705c121SKalle Valo #define CSR_LED_REG_TURN_ON (0x60) 413e705c121SKalle Valo #define CSR_LED_REG_TURN_OFF (0x20) 414e705c121SKalle Valo 415e705c121SKalle Valo /* ANA_PLL */ 416e705c121SKalle Valo #define CSR50_ANA_PLL_CFG_VAL (0x00880300) 417e705c121SKalle Valo 418e705c121SKalle Valo /* HPET MEM debug */ 419e705c121SKalle Valo #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 420e705c121SKalle Valo 421e705c121SKalle Valo /* DRAM INT TABLE */ 422e705c121SKalle Valo #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) 423e705c121SKalle Valo #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 424e705c121SKalle Valo #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 425e705c121SKalle Valo 426e705c121SKalle Valo /* 427e705c121SKalle Valo * SHR target access (Shared block memory space) 428e705c121SKalle Valo * 429e705c121SKalle Valo * Shared internal registers can be accessed directly from PCI bus through SHR 430e705c121SKalle Valo * arbiter without need for the MAC HW to be powered up. This is possible due to 431e705c121SKalle Valo * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and 432e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. 433e705c121SKalle Valo * 434e705c121SKalle Valo * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW 435e705c121SKalle Valo * need not be powered up so no "grab inc access" is required. 436e705c121SKalle Valo */ 437e705c121SKalle Valo 438e705c121SKalle Valo /* 439e705c121SKalle Valo * Registers for accessing shared registers (e.g. SHR_APMG_GP1, 440e705c121SKalle Valo * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), 441e705c121SKalle Valo * first, write to the control register: 442e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 443e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) 444e705c121SKalle Valo * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. 445e705c121SKalle Valo * 446e705c121SKalle Valo * To write the register, first, write to the data register 447e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: 448e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) 449e705c121SKalle Valo * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) 450e705c121SKalle Valo */ 451e705c121SKalle Valo #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) 452e705c121SKalle Valo #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) 453e705c121SKalle Valo 454e705c121SKalle Valo /* 455e705c121SKalle Valo * HBUS (Host-side Bus) 456e705c121SKalle Valo * 457e705c121SKalle Valo * HBUS registers are mapped directly into PCI bus space, but are used 458e705c121SKalle Valo * to indirectly access device's internal memory or registers that 459e705c121SKalle Valo * may be powered-down. 460e705c121SKalle Valo * 461e705c121SKalle Valo * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 462e705c121SKalle Valo * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 463e705c121SKalle Valo * to make sure the MAC (uCode processor, etc.) is powered up for accessing 464e705c121SKalle Valo * internal resources. 465e705c121SKalle Valo * 466e705c121SKalle Valo * Do not use iwl_write32()/iwl_read32() family to access these registers; 467e705c121SKalle Valo * these provide only simple PCI bus access, without waking up the MAC. 468e705c121SKalle Valo */ 469e705c121SKalle Valo #define HBUS_BASE (0x400) 470e705c121SKalle Valo 471e705c121SKalle Valo /* 472e705c121SKalle Valo * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 473e705c121SKalle Valo * structures, error log, event log, verifying uCode load). 474e705c121SKalle Valo * First write to address register, then read from or write to data register 475e705c121SKalle Valo * to complete the job. Once the address register is set up, accesses to 476e705c121SKalle Valo * data registers auto-increment the address by one dword. 477e705c121SKalle Valo * Bit usage for address registers (read or write): 478e705c121SKalle Valo * 0-31: memory address within device 479e705c121SKalle Valo */ 480e705c121SKalle Valo #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 481e705c121SKalle Valo #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 482e705c121SKalle Valo #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 483e705c121SKalle Valo #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 484e705c121SKalle Valo 485e705c121SKalle Valo /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 486e705c121SKalle Valo #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 487e705c121SKalle Valo #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 488e705c121SKalle Valo 489e705c121SKalle Valo /* 490e705c121SKalle Valo * Registers for accessing device's internal peripheral registers 491e705c121SKalle Valo * (e.g. SCD, BSM, etc.). First write to address register, 492e705c121SKalle Valo * then read from or write to data register to complete the job. 493e705c121SKalle Valo * Bit usage for address registers (read or write): 494e705c121SKalle Valo * 0-15: register address (offset) within device 495e705c121SKalle Valo * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 496e705c121SKalle Valo */ 497e705c121SKalle Valo #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 498e705c121SKalle Valo #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 499e705c121SKalle Valo #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 500e705c121SKalle Valo #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 501e705c121SKalle Valo 502e705c121SKalle Valo /* Used to enable DBGM */ 503e705c121SKalle Valo #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) 504e705c121SKalle Valo 505e705c121SKalle Valo /* 506e705c121SKalle Valo * Per-Tx-queue write pointer (index, really!) 507e705c121SKalle Valo * Indicates index to next TFD that driver will fill (1 past latest filled). 508e705c121SKalle Valo * Bit usage: 509e705c121SKalle Valo * 0-7: queue write index 510e705c121SKalle Valo * 11-8: queue selector 511e705c121SKalle Valo */ 512e705c121SKalle Valo #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 513e705c121SKalle Valo 514e705c121SKalle Valo /********************************************************** 515e705c121SKalle Valo * CSR values 516e705c121SKalle Valo **********************************************************/ 517e705c121SKalle Valo /* 518e705c121SKalle Valo * host interrupt timeout value 519e705c121SKalle Valo * used with setting interrupt coalescing timer 520e705c121SKalle Valo * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 521e705c121SKalle Valo * 522e705c121SKalle Valo * default interrupt coalescing timer is 64 x 32 = 2048 usecs 523e705c121SKalle Valo */ 524e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) 525e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_DEF (0x40) 526e705c121SKalle Valo #define IWL_HOST_INT_TIMEOUT_MIN (0x0) 527e705c121SKalle Valo #define IWL_HOST_INT_OPER_MODE BIT(31) 528e705c121SKalle Valo 529e705c121SKalle Valo /***************************************************************************** 530e705c121SKalle Valo * 7000/3000 series SHR DTS addresses * 531e705c121SKalle Valo *****************************************************************************/ 532e705c121SKalle Valo 533e705c121SKalle Valo /* Diode Results Register Structure: */ 534e705c121SKalle Valo enum dtd_diode_reg { 535e705c121SKalle Valo DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 536e705c121SKalle Valo DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 537e705c121SKalle Valo DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 538e705c121SKalle Valo DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 539e705c121SKalle Valo DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 540e705c121SKalle Valo DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 541e705c121SKalle Valo /* Those are the masks INSIDE the flags bit-field: */ 542e705c121SKalle Valo DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 543e705c121SKalle Valo DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 544e705c121SKalle Valo DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 545e705c121SKalle Valo DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 546e705c121SKalle Valo }; 547e705c121SKalle Valo 5482e5d4a8fSHaim Dreyfuss /***************************************************************************** 5492e5d4a8fSHaim Dreyfuss * MSIX related registers * 5502e5d4a8fSHaim Dreyfuss *****************************************************************************/ 5512e5d4a8fSHaim Dreyfuss 5522e5d4a8fSHaim Dreyfuss #define CSR_MSIX_BASE (0x2000) 5532e5d4a8fSHaim Dreyfuss #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800) 5542e5d4a8fSHaim Dreyfuss #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804) 5552e5d4a8fSHaim Dreyfuss #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808) 5562e5d4a8fSHaim Dreyfuss #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C) 5572e5d4a8fSHaim Dreyfuss #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810) 5582e5d4a8fSHaim Dreyfuss #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880) 5592e5d4a8fSHaim Dreyfuss #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890) 5602e5d4a8fSHaim Dreyfuss #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000) 5612e5d4a8fSHaim Dreyfuss #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause)) 5622e5d4a8fSHaim Dreyfuss #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause)) 5632e5d4a8fSHaim Dreyfuss 5642e5d4a8fSHaim Dreyfuss #define MSIX_FH_INT_CAUSES_Q(q) (q) 5652e5d4a8fSHaim Dreyfuss 5662e5d4a8fSHaim Dreyfuss /* 5672e5d4a8fSHaim Dreyfuss * Causes for the FH register interrupts 5682e5d4a8fSHaim Dreyfuss */ 5692e5d4a8fSHaim Dreyfuss enum msix_fh_int_causes { 570496d83caSHaim Dreyfuss MSIX_FH_INT_CAUSES_Q0 = BIT(0), 571496d83caSHaim Dreyfuss MSIX_FH_INT_CAUSES_Q1 = BIT(1), 5722e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16), 5732e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17), 5742e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_S2D = BIT(19), 5752e5d4a8fSHaim Dreyfuss MSIX_FH_INT_CAUSES_FH_ERR = BIT(21), 5762e5d4a8fSHaim Dreyfuss }; 5772e5d4a8fSHaim Dreyfuss 578d4626f91SMordechay Goodstein /* The low 16 bits are for rx data queue indication */ 579d4626f91SMordechay Goodstein #define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff 580d4626f91SMordechay Goodstein 5812e5d4a8fSHaim Dreyfuss /* 5822e5d4a8fSHaim Dreyfuss * Causes for the HW register interrupts 5832e5d4a8fSHaim Dreyfuss */ 5842e5d4a8fSHaim Dreyfuss enum msix_hw_int_causes { 5852e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0), 5862e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1), 587aa7fd946SJohannes Berg MSIX_HW_INT_CAUSES_REG_IML = BIT(1), 588906d4eb8SJohannes Berg MSIX_HW_INT_CAUSES_REG_RESET_DONE = BIT(2), 5892e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6), 5902e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7), 5912e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8), 5922e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25), 5932e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_SCD = BIT(26), 5942e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27), 5952e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29), 5962e5d4a8fSHaim Dreyfuss MSIX_HW_INT_CAUSES_REG_HAP = BIT(30), 5972e5d4a8fSHaim Dreyfuss }; 5982e5d4a8fSHaim Dreyfuss 5992e5d4a8fSHaim Dreyfuss #define MSIX_MIN_INTERRUPT_VECTORS 2 6002e5d4a8fSHaim Dreyfuss #define MSIX_AUTO_CLEAR_CAUSE 0 6012e5d4a8fSHaim Dreyfuss #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 6022e5d4a8fSHaim Dreyfuss 60317c867bfSSara Sharon /***************************************************************************** 60417c867bfSSara Sharon * HW address related registers * 60517c867bfSSara Sharon *****************************************************************************/ 60617c867bfSSara Sharon 60717c867bfSSara Sharon #define CSR_ADDR_BASE (0x380) 60817c867bfSSara Sharon #define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE) 60917c867bfSSara Sharon #define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4) 61017c867bfSSara Sharon #define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8) 61117c867bfSSara Sharon #define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC) 61217c867bfSSara Sharon 613e705c121SKalle Valo #endif /* !__iwl_csr_h__ */ 614