1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2017 Intel Deutschland GmbH 9 * Copyright(c) 2018 - 2020 Intel Corporation 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Copyright(c) 2017 Intel Deutschland GmbH 23 * Copyright(c) 2018 - 2020 Intel Corporation 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 30 * * Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * * Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in 34 * the documentation and/or other materials provided with the 35 * distribution. 36 * * Neither the name Intel Corporation nor the names of its 37 * contributors may be used to endorse or promote products derived 38 * from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 *****************************************************************************/ 53 54 #ifndef __iwl_context_info_file_h__ 55 #define __iwl_context_info_file_h__ 56 57 /* maximmum number of DRAM map entries supported by FW */ 58 #define IWL_MAX_DRAM_ENTRY 64 59 #define CSR_CTXT_INFO_BA 0x40 60 61 /** 62 * enum iwl_context_info_flags - Context information control flags 63 * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 64 * the init done for driver command that configures several system modes 65 * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug 66 * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump 67 * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size 68 * exponent, the actual size is 2**value, valid sizes are 8-2048. 69 * The value is four bits long. Maximum valid exponent is 12 70 * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 71 * default is short format - not supported by the driver) 72 * @IWL_CTXT_INFO_RB_SIZE: RB size mask 73 * (values are IWL_CTXT_INFO_RB_SIZE_*K) 74 * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 75 * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 76 * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 77 * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 78 * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 79 * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 80 * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 81 * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 82 * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 83 * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 84 */ 85 enum iwl_context_info_flags { 86 IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001, 87 IWL_CTXT_INFO_EARLY_DEBUG = 0x0002, 88 IWL_CTXT_INFO_ENABLE_CDMP = 0x0004, 89 IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0, 90 IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100, 91 IWL_CTXT_INFO_RB_SIZE = 0x1e00, 92 IWL_CTXT_INFO_RB_SIZE_1K = 0x1, 93 IWL_CTXT_INFO_RB_SIZE_2K = 0x2, 94 IWL_CTXT_INFO_RB_SIZE_4K = 0x4, 95 IWL_CTXT_INFO_RB_SIZE_8K = 0x8, 96 IWL_CTXT_INFO_RB_SIZE_12K = 0x9, 97 IWL_CTXT_INFO_RB_SIZE_16K = 0xa, 98 IWL_CTXT_INFO_RB_SIZE_20K = 0xb, 99 IWL_CTXT_INFO_RB_SIZE_24K = 0xc, 100 IWL_CTXT_INFO_RB_SIZE_28K = 0xd, 101 IWL_CTXT_INFO_RB_SIZE_32K = 0xe, 102 }; 103 104 /* 105 * struct iwl_context_info_version - version structure 106 * @mac_id: SKU and revision id 107 * @version: context information version id 108 * @size: the size of the context information in DWs 109 */ 110 struct iwl_context_info_version { 111 __le16 mac_id; 112 __le16 version; 113 __le16 size; 114 __le16 reserved; 115 } __packed; 116 117 /* 118 * struct iwl_context_info_control - version structure 119 * @control_flags: context information flags see &enum iwl_context_info_flags 120 */ 121 struct iwl_context_info_control { 122 __le32 control_flags; 123 __le32 reserved; 124 } __packed; 125 126 /* 127 * struct iwl_context_info_dram - images DRAM map 128 * each entry in the map represents a DRAM chunk of up to 32 KB 129 * @umac_img: UMAC image DRAM map 130 * @lmac_img: LMAC image DRAM map 131 * @virtual_img: paged image DRAM map 132 */ 133 struct iwl_context_info_dram { 134 __le64 umac_img[IWL_MAX_DRAM_ENTRY]; 135 __le64 lmac_img[IWL_MAX_DRAM_ENTRY]; 136 __le64 virtual_img[IWL_MAX_DRAM_ENTRY]; 137 } __packed; 138 139 /* 140 * struct iwl_context_info_rbd_cfg - RBDs configuration 141 * @free_rbd_addr: default queue free RB CB base address 142 * @used_rbd_addr: default queue used RB CB base address 143 * @status_wr_ptr: default queue used RB status write pointer 144 */ 145 struct iwl_context_info_rbd_cfg { 146 __le64 free_rbd_addr; 147 __le64 used_rbd_addr; 148 __le64 status_wr_ptr; 149 } __packed; 150 151 /* 152 * struct iwl_context_info_hcmd_cfg - command queue configuration 153 * @cmd_queue_addr: address of command queue 154 * @cmd_queue_size: number of entries 155 */ 156 struct iwl_context_info_hcmd_cfg { 157 __le64 cmd_queue_addr; 158 u8 cmd_queue_size; 159 u8 reserved[7]; 160 } __packed; 161 162 /* 163 * struct iwl_context_info_dump_cfg - Core Dump configuration 164 * @core_dump_addr: core dump (debug DRAM address) start address 165 * @core_dump_size: size, in DWs 166 */ 167 struct iwl_context_info_dump_cfg { 168 __le64 core_dump_addr; 169 __le32 core_dump_size; 170 __le32 reserved; 171 } __packed; 172 173 /* 174 * struct iwl_context_info_pnvm_cfg - platform NVM data configuration 175 * @platform_nvm_addr: Platform NVM data start address 176 * @platform_nvm_size: size in DWs 177 */ 178 struct iwl_context_info_pnvm_cfg { 179 __le64 platform_nvm_addr; 180 __le32 platform_nvm_size; 181 __le32 reserved; 182 } __packed; 183 184 /* 185 * struct iwl_context_info_early_dbg_cfg - early debug configuration for 186 * dumping DRAM addresses 187 * @early_debug_addr: early debug start address 188 * @early_debug_size: size in DWs 189 */ 190 struct iwl_context_info_early_dbg_cfg { 191 __le64 early_debug_addr; 192 __le32 early_debug_size; 193 __le32 reserved; 194 } __packed; 195 196 /* 197 * struct iwl_context_info - device INIT configuration 198 * @version: version information of context info and HW 199 * @control: control flags of FH configurations 200 * @rbd_cfg: default RX queue configuration 201 * @hcmd_cfg: command queue configuration 202 * @dump_cfg: core dump data 203 * @edbg_cfg: early debug configuration 204 * @pnvm_cfg: platform nvm configuration 205 * @dram: firmware image addresses in DRAM 206 */ 207 struct iwl_context_info { 208 struct iwl_context_info_version version; 209 struct iwl_context_info_control control; 210 __le64 reserved0; 211 struct iwl_context_info_rbd_cfg rbd_cfg; 212 struct iwl_context_info_hcmd_cfg hcmd_cfg; 213 __le32 reserved1[4]; 214 struct iwl_context_info_dump_cfg dump_cfg; 215 struct iwl_context_info_early_dbg_cfg edbg_cfg; 216 struct iwl_context_info_pnvm_cfg pnvm_cfg; 217 __le32 reserved2[16]; 218 struct iwl_context_info_dram dram; 219 __le32 reserved3[16]; 220 } __packed; 221 222 int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw); 223 void iwl_pcie_ctxt_info_free(struct iwl_trans *trans); 224 void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans); 225 int iwl_pcie_init_fw_sec(struct iwl_trans *trans, 226 const struct fw_img *fw, 227 struct iwl_context_info_dram *ctxt_dram); 228 int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 229 const void *data, u32 len, 230 struct iwl_dram_data *dram); 231 232 #endif /* __iwl_context_info_file_h__ */ 233