1*8e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*8e99ea8dSJohannes Berg /* 3*8e99ea8dSJohannes Berg * Copyright (C) 2017 Intel Deutschland GmbH 4*8e99ea8dSJohannes Berg * Copyright (C) 2018-2020 Intel Corporation 5*8e99ea8dSJohannes Berg */ 6eda50cdeSSara Sharon #ifndef __iwl_context_info_file_h__ 7eda50cdeSSara Sharon #define __iwl_context_info_file_h__ 8eda50cdeSSara Sharon 9eda50cdeSSara Sharon /* maximmum number of DRAM map entries supported by FW */ 10eda50cdeSSara Sharon #define IWL_MAX_DRAM_ENTRY 64 11eda50cdeSSara Sharon #define CSR_CTXT_INFO_BA 0x40 12eda50cdeSSara Sharon 13eda50cdeSSara Sharon /** 14eda50cdeSSara Sharon * enum iwl_context_info_flags - Context information control flags 15eda50cdeSSara Sharon * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 16eda50cdeSSara Sharon * the init done for driver command that configures several system modes 17eda50cdeSSara Sharon * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug 18eda50cdeSSara Sharon * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump 19c042f0c7SJohannes Berg * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size 20eda50cdeSSara Sharon * exponent, the actual size is 2**value, valid sizes are 8-2048. 21eda50cdeSSara Sharon * The value is four bits long. Maximum valid exponent is 12 22eda50cdeSSara Sharon * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 23eda50cdeSSara Sharon * default is short format - not supported by the driver) 24c042f0c7SJohannes Berg * @IWL_CTXT_INFO_RB_SIZE: RB size mask 25753e9761SShaul Triebitz * (values are IWL_CTXT_INFO_RB_SIZE_*K) 26753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 27753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 28753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 29753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 30753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 31753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 32753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 33753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 34753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 35753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 36eda50cdeSSara Sharon */ 37eda50cdeSSara Sharon enum iwl_context_info_flags { 38c042f0c7SJohannes Berg IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001, 39c042f0c7SJohannes Berg IWL_CTXT_INFO_EARLY_DEBUG = 0x0002, 40c042f0c7SJohannes Berg IWL_CTXT_INFO_ENABLE_CDMP = 0x0004, 41c042f0c7SJohannes Berg IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0, 42c042f0c7SJohannes Berg IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100, 43c042f0c7SJohannes Berg IWL_CTXT_INFO_RB_SIZE = 0x1e00, 44753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_1K = 0x1, 45753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_2K = 0x2, 46753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_4K = 0x4, 47753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_8K = 0x8, 48753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_12K = 0x9, 49753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_16K = 0xa, 50753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_20K = 0xb, 51753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_24K = 0xc, 52753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_28K = 0xd, 53753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_32K = 0xe, 54eda50cdeSSara Sharon }; 55eda50cdeSSara Sharon 56eda50cdeSSara Sharon /* 57eda50cdeSSara Sharon * struct iwl_context_info_version - version structure 58eda50cdeSSara Sharon * @mac_id: SKU and revision id 59eda50cdeSSara Sharon * @version: context information version id 60eda50cdeSSara Sharon * @size: the size of the context information in DWs 61eda50cdeSSara Sharon */ 62eda50cdeSSara Sharon struct iwl_context_info_version { 63eda50cdeSSara Sharon __le16 mac_id; 64eda50cdeSSara Sharon __le16 version; 65eda50cdeSSara Sharon __le16 size; 66eda50cdeSSara Sharon __le16 reserved; 67eda50cdeSSara Sharon } __packed; 68eda50cdeSSara Sharon 69eda50cdeSSara Sharon /* 70eda50cdeSSara Sharon * struct iwl_context_info_control - version structure 71eda50cdeSSara Sharon * @control_flags: context information flags see &enum iwl_context_info_flags 72eda50cdeSSara Sharon */ 73eda50cdeSSara Sharon struct iwl_context_info_control { 74eda50cdeSSara Sharon __le32 control_flags; 75eda50cdeSSara Sharon __le32 reserved; 76eda50cdeSSara Sharon } __packed; 77eda50cdeSSara Sharon 78eda50cdeSSara Sharon /* 79eda50cdeSSara Sharon * struct iwl_context_info_dram - images DRAM map 80eda50cdeSSara Sharon * each entry in the map represents a DRAM chunk of up to 32 KB 81eda50cdeSSara Sharon * @umac_img: UMAC image DRAM map 82eda50cdeSSara Sharon * @lmac_img: LMAC image DRAM map 83eda50cdeSSara Sharon * @virtual_img: paged image DRAM map 84eda50cdeSSara Sharon */ 85eda50cdeSSara Sharon struct iwl_context_info_dram { 86eda50cdeSSara Sharon __le64 umac_img[IWL_MAX_DRAM_ENTRY]; 87eda50cdeSSara Sharon __le64 lmac_img[IWL_MAX_DRAM_ENTRY]; 88eda50cdeSSara Sharon __le64 virtual_img[IWL_MAX_DRAM_ENTRY]; 89eda50cdeSSara Sharon } __packed; 90eda50cdeSSara Sharon 91eda50cdeSSara Sharon /* 92eda50cdeSSara Sharon * struct iwl_context_info_rbd_cfg - RBDs configuration 93eda50cdeSSara Sharon * @free_rbd_addr: default queue free RB CB base address 94eda50cdeSSara Sharon * @used_rbd_addr: default queue used RB CB base address 95eda50cdeSSara Sharon * @status_wr_ptr: default queue used RB status write pointer 96eda50cdeSSara Sharon */ 97eda50cdeSSara Sharon struct iwl_context_info_rbd_cfg { 98eda50cdeSSara Sharon __le64 free_rbd_addr; 99eda50cdeSSara Sharon __le64 used_rbd_addr; 100eda50cdeSSara Sharon __le64 status_wr_ptr; 101eda50cdeSSara Sharon } __packed; 102eda50cdeSSara Sharon 103eda50cdeSSara Sharon /* 104eda50cdeSSara Sharon * struct iwl_context_info_hcmd_cfg - command queue configuration 105eda50cdeSSara Sharon * @cmd_queue_addr: address of command queue 106eda50cdeSSara Sharon * @cmd_queue_size: number of entries 107eda50cdeSSara Sharon */ 108eda50cdeSSara Sharon struct iwl_context_info_hcmd_cfg { 109eda50cdeSSara Sharon __le64 cmd_queue_addr; 110eda50cdeSSara Sharon u8 cmd_queue_size; 111eda50cdeSSara Sharon u8 reserved[7]; 112eda50cdeSSara Sharon } __packed; 113eda50cdeSSara Sharon 114eda50cdeSSara Sharon /* 115eda50cdeSSara Sharon * struct iwl_context_info_dump_cfg - Core Dump configuration 116eda50cdeSSara Sharon * @core_dump_addr: core dump (debug DRAM address) start address 117eda50cdeSSara Sharon * @core_dump_size: size, in DWs 118eda50cdeSSara Sharon */ 119eda50cdeSSara Sharon struct iwl_context_info_dump_cfg { 120eda50cdeSSara Sharon __le64 core_dump_addr; 121eda50cdeSSara Sharon __le32 core_dump_size; 122eda50cdeSSara Sharon __le32 reserved; 123eda50cdeSSara Sharon } __packed; 124eda50cdeSSara Sharon 125eda50cdeSSara Sharon /* 126eda50cdeSSara Sharon * struct iwl_context_info_pnvm_cfg - platform NVM data configuration 127eda50cdeSSara Sharon * @platform_nvm_addr: Platform NVM data start address 128eda50cdeSSara Sharon * @platform_nvm_size: size in DWs 129eda50cdeSSara Sharon */ 130eda50cdeSSara Sharon struct iwl_context_info_pnvm_cfg { 131eda50cdeSSara Sharon __le64 platform_nvm_addr; 132eda50cdeSSara Sharon __le32 platform_nvm_size; 133eda50cdeSSara Sharon __le32 reserved; 134eda50cdeSSara Sharon } __packed; 135eda50cdeSSara Sharon 136eda50cdeSSara Sharon /* 137eda50cdeSSara Sharon * struct iwl_context_info_early_dbg_cfg - early debug configuration for 138eda50cdeSSara Sharon * dumping DRAM addresses 139eda50cdeSSara Sharon * @early_debug_addr: early debug start address 140eda50cdeSSara Sharon * @early_debug_size: size in DWs 141eda50cdeSSara Sharon */ 142eda50cdeSSara Sharon struct iwl_context_info_early_dbg_cfg { 143eda50cdeSSara Sharon __le64 early_debug_addr; 144eda50cdeSSara Sharon __le32 early_debug_size; 145eda50cdeSSara Sharon __le32 reserved; 146eda50cdeSSara Sharon } __packed; 147eda50cdeSSara Sharon 148eda50cdeSSara Sharon /* 149eda50cdeSSara Sharon * struct iwl_context_info - device INIT configuration 150eda50cdeSSara Sharon * @version: version information of context info and HW 151eda50cdeSSara Sharon * @control: control flags of FH configurations 152eda50cdeSSara Sharon * @rbd_cfg: default RX queue configuration 153eda50cdeSSara Sharon * @hcmd_cfg: command queue configuration 154eda50cdeSSara Sharon * @dump_cfg: core dump data 155eda50cdeSSara Sharon * @edbg_cfg: early debug configuration 156eda50cdeSSara Sharon * @pnvm_cfg: platform nvm configuration 157eda50cdeSSara Sharon * @dram: firmware image addresses in DRAM 158eda50cdeSSara Sharon */ 159eda50cdeSSara Sharon struct iwl_context_info { 160eda50cdeSSara Sharon struct iwl_context_info_version version; 161eda50cdeSSara Sharon struct iwl_context_info_control control; 162eda50cdeSSara Sharon __le64 reserved0; 163eda50cdeSSara Sharon struct iwl_context_info_rbd_cfg rbd_cfg; 164eda50cdeSSara Sharon struct iwl_context_info_hcmd_cfg hcmd_cfg; 165eda50cdeSSara Sharon __le32 reserved1[4]; 166eda50cdeSSara Sharon struct iwl_context_info_dump_cfg dump_cfg; 167eda50cdeSSara Sharon struct iwl_context_info_early_dbg_cfg edbg_cfg; 168eda50cdeSSara Sharon struct iwl_context_info_pnvm_cfg pnvm_cfg; 169eda50cdeSSara Sharon __le32 reserved2[16]; 170eda50cdeSSara Sharon struct iwl_context_info_dram dram; 171eda50cdeSSara Sharon __le32 reserved3[16]; 172eda50cdeSSara Sharon } __packed; 173eda50cdeSSara Sharon 174eda50cdeSSara Sharon int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw); 175eda50cdeSSara Sharon void iwl_pcie_ctxt_info_free(struct iwl_trans *trans); 176eda50cdeSSara Sharon void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans); 1772ee82402SGolan Ben Ami int iwl_pcie_init_fw_sec(struct iwl_trans *trans, 1782ee82402SGolan Ben Ami const struct fw_img *fw, 1792ee82402SGolan Ben Ami struct iwl_context_info_dram *ctxt_dram); 1806654cd4eSLuca Coelho int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 1816654cd4eSLuca Coelho const void *data, u32 len, 1826654cd4eSLuca Coelho struct iwl_dram_data *dram); 183eda50cdeSSara Sharon 184eda50cdeSSara Sharon #endif /* __iwl_context_info_file_h__ */ 185