1eda50cdeSSara Sharon /****************************************************************************** 2eda50cdeSSara Sharon * 3eda50cdeSSara Sharon * This file is provided under a dual BSD/GPLv2 license. When using or 4eda50cdeSSara Sharon * redistributing this file, you may do so under either license. 5eda50cdeSSara Sharon * 6eda50cdeSSara Sharon * GPL LICENSE SUMMARY 7eda50cdeSSara Sharon * 8eda50cdeSSara Sharon * Copyright(c) 2017 Intel Deutschland GmbH 96654cd4eSLuca Coelho * Copyright(c) 2018 - 2020 Intel Corporation 10eda50cdeSSara Sharon * 11eda50cdeSSara Sharon * This program is free software; you can redistribute it and/or modify 12eda50cdeSSara Sharon * it under the terms of version 2 of the GNU General Public License as 13eda50cdeSSara Sharon * published by the Free Software Foundation. 14eda50cdeSSara Sharon * 15eda50cdeSSara Sharon * This program is distributed in the hope that it will be useful, but 16eda50cdeSSara Sharon * WITHOUT ANY WARRANTY; without even the implied warranty of 17eda50cdeSSara Sharon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18eda50cdeSSara Sharon * General Public License for more details. 19eda50cdeSSara Sharon * 20eda50cdeSSara Sharon * BSD LICENSE 21eda50cdeSSara Sharon * 22eda50cdeSSara Sharon * Copyright(c) 2017 Intel Deutschland GmbH 236654cd4eSLuca Coelho * Copyright(c) 2018 - 2020 Intel Corporation 24eda50cdeSSara Sharon * All rights reserved. 25eda50cdeSSara Sharon * 26eda50cdeSSara Sharon * Redistribution and use in source and binary forms, with or without 27eda50cdeSSara Sharon * modification, are permitted provided that the following conditions 28eda50cdeSSara Sharon * are met: 29eda50cdeSSara Sharon * 30eda50cdeSSara Sharon * * Redistributions of source code must retain the above copyright 31eda50cdeSSara Sharon * notice, this list of conditions and the following disclaimer. 32eda50cdeSSara Sharon * * Redistributions in binary form must reproduce the above copyright 33eda50cdeSSara Sharon * notice, this list of conditions and the following disclaimer in 34eda50cdeSSara Sharon * the documentation and/or other materials provided with the 35eda50cdeSSara Sharon * distribution. 36eda50cdeSSara Sharon * * Neither the name Intel Corporation nor the names of its 37eda50cdeSSara Sharon * contributors may be used to endorse or promote products derived 38eda50cdeSSara Sharon * from this software without specific prior written permission. 39eda50cdeSSara Sharon * 40eda50cdeSSara Sharon * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41eda50cdeSSara Sharon * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42eda50cdeSSara Sharon * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43eda50cdeSSara Sharon * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44eda50cdeSSara Sharon * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45eda50cdeSSara Sharon * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46eda50cdeSSara Sharon * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47eda50cdeSSara Sharon * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48eda50cdeSSara Sharon * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49eda50cdeSSara Sharon * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50eda50cdeSSara Sharon * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51eda50cdeSSara Sharon * 52eda50cdeSSara Sharon *****************************************************************************/ 53eda50cdeSSara Sharon 54eda50cdeSSara Sharon #ifndef __iwl_context_info_file_h__ 55eda50cdeSSara Sharon #define __iwl_context_info_file_h__ 56eda50cdeSSara Sharon 57eda50cdeSSara Sharon /* maximmum number of DRAM map entries supported by FW */ 58eda50cdeSSara Sharon #define IWL_MAX_DRAM_ENTRY 64 59eda50cdeSSara Sharon #define CSR_CTXT_INFO_BA 0x40 60eda50cdeSSara Sharon 61eda50cdeSSara Sharon /** 62eda50cdeSSara Sharon * enum iwl_context_info_flags - Context information control flags 63eda50cdeSSara Sharon * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 64eda50cdeSSara Sharon * the init done for driver command that configures several system modes 65eda50cdeSSara Sharon * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug 66eda50cdeSSara Sharon * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump 67c042f0c7SJohannes Berg * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size 68eda50cdeSSara Sharon * exponent, the actual size is 2**value, valid sizes are 8-2048. 69eda50cdeSSara Sharon * The value is four bits long. Maximum valid exponent is 12 70eda50cdeSSara Sharon * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 71eda50cdeSSara Sharon * default is short format - not supported by the driver) 72c042f0c7SJohannes Berg * @IWL_CTXT_INFO_RB_SIZE: RB size mask 73753e9761SShaul Triebitz * (values are IWL_CTXT_INFO_RB_SIZE_*K) 74753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 75753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 76753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 77753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 78753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 79753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 80753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 81753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 82753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 83753e9761SShaul Triebitz * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 84eda50cdeSSara Sharon */ 85eda50cdeSSara Sharon enum iwl_context_info_flags { 86c042f0c7SJohannes Berg IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001, 87c042f0c7SJohannes Berg IWL_CTXT_INFO_EARLY_DEBUG = 0x0002, 88c042f0c7SJohannes Berg IWL_CTXT_INFO_ENABLE_CDMP = 0x0004, 89c042f0c7SJohannes Berg IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0, 90c042f0c7SJohannes Berg IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100, 91c042f0c7SJohannes Berg IWL_CTXT_INFO_RB_SIZE = 0x1e00, 92753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_1K = 0x1, 93753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_2K = 0x2, 94753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_4K = 0x4, 95753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_8K = 0x8, 96753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_12K = 0x9, 97753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_16K = 0xa, 98753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_20K = 0xb, 99753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_24K = 0xc, 100753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_28K = 0xd, 101753e9761SShaul Triebitz IWL_CTXT_INFO_RB_SIZE_32K = 0xe, 102eda50cdeSSara Sharon }; 103eda50cdeSSara Sharon 104eda50cdeSSara Sharon /* 105eda50cdeSSara Sharon * struct iwl_context_info_version - version structure 106eda50cdeSSara Sharon * @mac_id: SKU and revision id 107eda50cdeSSara Sharon * @version: context information version id 108eda50cdeSSara Sharon * @size: the size of the context information in DWs 109eda50cdeSSara Sharon */ 110eda50cdeSSara Sharon struct iwl_context_info_version { 111eda50cdeSSara Sharon __le16 mac_id; 112eda50cdeSSara Sharon __le16 version; 113eda50cdeSSara Sharon __le16 size; 114eda50cdeSSara Sharon __le16 reserved; 115eda50cdeSSara Sharon } __packed; 116eda50cdeSSara Sharon 117eda50cdeSSara Sharon /* 118eda50cdeSSara Sharon * struct iwl_context_info_control - version structure 119eda50cdeSSara Sharon * @control_flags: context information flags see &enum iwl_context_info_flags 120eda50cdeSSara Sharon */ 121eda50cdeSSara Sharon struct iwl_context_info_control { 122eda50cdeSSara Sharon __le32 control_flags; 123eda50cdeSSara Sharon __le32 reserved; 124eda50cdeSSara Sharon } __packed; 125eda50cdeSSara Sharon 126eda50cdeSSara Sharon /* 127eda50cdeSSara Sharon * struct iwl_context_info_dram - images DRAM map 128eda50cdeSSara Sharon * each entry in the map represents a DRAM chunk of up to 32 KB 129eda50cdeSSara Sharon * @umac_img: UMAC image DRAM map 130eda50cdeSSara Sharon * @lmac_img: LMAC image DRAM map 131eda50cdeSSara Sharon * @virtual_img: paged image DRAM map 132eda50cdeSSara Sharon */ 133eda50cdeSSara Sharon struct iwl_context_info_dram { 134eda50cdeSSara Sharon __le64 umac_img[IWL_MAX_DRAM_ENTRY]; 135eda50cdeSSara Sharon __le64 lmac_img[IWL_MAX_DRAM_ENTRY]; 136eda50cdeSSara Sharon __le64 virtual_img[IWL_MAX_DRAM_ENTRY]; 137eda50cdeSSara Sharon } __packed; 138eda50cdeSSara Sharon 139eda50cdeSSara Sharon /* 140eda50cdeSSara Sharon * struct iwl_context_info_rbd_cfg - RBDs configuration 141eda50cdeSSara Sharon * @free_rbd_addr: default queue free RB CB base address 142eda50cdeSSara Sharon * @used_rbd_addr: default queue used RB CB base address 143eda50cdeSSara Sharon * @status_wr_ptr: default queue used RB status write pointer 144eda50cdeSSara Sharon */ 145eda50cdeSSara Sharon struct iwl_context_info_rbd_cfg { 146eda50cdeSSara Sharon __le64 free_rbd_addr; 147eda50cdeSSara Sharon __le64 used_rbd_addr; 148eda50cdeSSara Sharon __le64 status_wr_ptr; 149eda50cdeSSara Sharon } __packed; 150eda50cdeSSara Sharon 151eda50cdeSSara Sharon /* 152eda50cdeSSara Sharon * struct iwl_context_info_hcmd_cfg - command queue configuration 153eda50cdeSSara Sharon * @cmd_queue_addr: address of command queue 154eda50cdeSSara Sharon * @cmd_queue_size: number of entries 155eda50cdeSSara Sharon */ 156eda50cdeSSara Sharon struct iwl_context_info_hcmd_cfg { 157eda50cdeSSara Sharon __le64 cmd_queue_addr; 158eda50cdeSSara Sharon u8 cmd_queue_size; 159eda50cdeSSara Sharon u8 reserved[7]; 160eda50cdeSSara Sharon } __packed; 161eda50cdeSSara Sharon 162eda50cdeSSara Sharon /* 163eda50cdeSSara Sharon * struct iwl_context_info_dump_cfg - Core Dump configuration 164eda50cdeSSara Sharon * @core_dump_addr: core dump (debug DRAM address) start address 165eda50cdeSSara Sharon * @core_dump_size: size, in DWs 166eda50cdeSSara Sharon */ 167eda50cdeSSara Sharon struct iwl_context_info_dump_cfg { 168eda50cdeSSara Sharon __le64 core_dump_addr; 169eda50cdeSSara Sharon __le32 core_dump_size; 170eda50cdeSSara Sharon __le32 reserved; 171eda50cdeSSara Sharon } __packed; 172eda50cdeSSara Sharon 173eda50cdeSSara Sharon /* 174eda50cdeSSara Sharon * struct iwl_context_info_pnvm_cfg - platform NVM data configuration 175eda50cdeSSara Sharon * @platform_nvm_addr: Platform NVM data start address 176eda50cdeSSara Sharon * @platform_nvm_size: size in DWs 177eda50cdeSSara Sharon */ 178eda50cdeSSara Sharon struct iwl_context_info_pnvm_cfg { 179eda50cdeSSara Sharon __le64 platform_nvm_addr; 180eda50cdeSSara Sharon __le32 platform_nvm_size; 181eda50cdeSSara Sharon __le32 reserved; 182eda50cdeSSara Sharon } __packed; 183eda50cdeSSara Sharon 184eda50cdeSSara Sharon /* 185eda50cdeSSara Sharon * struct iwl_context_info_early_dbg_cfg - early debug configuration for 186eda50cdeSSara Sharon * dumping DRAM addresses 187eda50cdeSSara Sharon * @early_debug_addr: early debug start address 188eda50cdeSSara Sharon * @early_debug_size: size in DWs 189eda50cdeSSara Sharon */ 190eda50cdeSSara Sharon struct iwl_context_info_early_dbg_cfg { 191eda50cdeSSara Sharon __le64 early_debug_addr; 192eda50cdeSSara Sharon __le32 early_debug_size; 193eda50cdeSSara Sharon __le32 reserved; 194eda50cdeSSara Sharon } __packed; 195eda50cdeSSara Sharon 196eda50cdeSSara Sharon /* 197eda50cdeSSara Sharon * struct iwl_context_info - device INIT configuration 198eda50cdeSSara Sharon * @version: version information of context info and HW 199eda50cdeSSara Sharon * @control: control flags of FH configurations 200eda50cdeSSara Sharon * @rbd_cfg: default RX queue configuration 201eda50cdeSSara Sharon * @hcmd_cfg: command queue configuration 202eda50cdeSSara Sharon * @dump_cfg: core dump data 203eda50cdeSSara Sharon * @edbg_cfg: early debug configuration 204eda50cdeSSara Sharon * @pnvm_cfg: platform nvm configuration 205eda50cdeSSara Sharon * @dram: firmware image addresses in DRAM 206eda50cdeSSara Sharon */ 207eda50cdeSSara Sharon struct iwl_context_info { 208eda50cdeSSara Sharon struct iwl_context_info_version version; 209eda50cdeSSara Sharon struct iwl_context_info_control control; 210eda50cdeSSara Sharon __le64 reserved0; 211eda50cdeSSara Sharon struct iwl_context_info_rbd_cfg rbd_cfg; 212eda50cdeSSara Sharon struct iwl_context_info_hcmd_cfg hcmd_cfg; 213eda50cdeSSara Sharon __le32 reserved1[4]; 214eda50cdeSSara Sharon struct iwl_context_info_dump_cfg dump_cfg; 215eda50cdeSSara Sharon struct iwl_context_info_early_dbg_cfg edbg_cfg; 216eda50cdeSSara Sharon struct iwl_context_info_pnvm_cfg pnvm_cfg; 217eda50cdeSSara Sharon __le32 reserved2[16]; 218eda50cdeSSara Sharon struct iwl_context_info_dram dram; 219eda50cdeSSara Sharon __le32 reserved3[16]; 220eda50cdeSSara Sharon } __packed; 221eda50cdeSSara Sharon 222eda50cdeSSara Sharon int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw); 223eda50cdeSSara Sharon void iwl_pcie_ctxt_info_free(struct iwl_trans *trans); 224eda50cdeSSara Sharon void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans); 2252ee82402SGolan Ben Ami int iwl_pcie_init_fw_sec(struct iwl_trans *trans, 2262ee82402SGolan Ben Ami const struct fw_img *fw, 2272ee82402SGolan Ben Ami struct iwl_context_info_dram *ctxt_dram); 2286654cd4eSLuca Coelho int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans, 2296654cd4eSLuca Coelho const void *data, u32 len, 2306654cd4eSLuca Coelho struct iwl_dram_data *dram); 231eda50cdeSSara Sharon 232eda50cdeSSara Sharon #endif /* __iwl_context_info_file_h__ */ 233