1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2018 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2018 Intel Corporation 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * * Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * * Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * * Neither the name Intel Corporation nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 * 50 *****************************************************************************/ 51 #ifndef __iwl_context_info_file_gen3_h__ 52 #define __iwl_context_info_file_gen3_h__ 53 54 #include "iwl-context-info.h" 55 56 #define CSR_CTXT_INFO_BOOT_CTRL 0x0 57 #define CSR_CTXT_INFO_ADDR 0x118 58 #define CSR_IML_DATA_ADDR 0x120 59 #define CSR_IML_SIZE_ADDR 0x128 60 #define CSR_IML_RESP_ADDR 0x12c 61 62 /* Set bit for enabling automatic function boot */ 63 #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 64 /* Set bit for initiating function boot */ 65 #define CSR_AUTO_FUNC_INIT BIT(7) 66 67 /** 68 * enum iwl_prph_scratch_mtr_format - tfd size configuration 69 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 70 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 71 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 72 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 73 */ 74 enum iwl_prph_scratch_mtr_format { 75 IWL_PRPH_MTR_FORMAT_16B = 0x0, 76 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 77 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 78 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 79 }; 80 81 /** 82 * enum iwl_prph_scratch_flags - PRPH scratch control flags 83 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 84 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 85 * in hwm config. 86 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 87 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 88 * multicomm. 89 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 90 * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 91 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 92 * completion descriptor, 1 for responses (legacy) 93 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 94 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 95 * 3: 256 bit. 96 */ 97 enum iwl_prph_scratch_flags { 98 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 99 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 100 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 101 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 102 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 103 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 104 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 105 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 106 }; 107 108 /* 109 * struct iwl_prph_scratch_version - version structure 110 * @mac_id: SKU and revision id 111 * @version: prph scratch information version id 112 * @size: the size of the context information in DWs 113 * @reserved: reserved 114 */ 115 struct iwl_prph_scratch_version { 116 __le16 mac_id; 117 __le16 version; 118 __le16 size; 119 __le16 reserved; 120 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 121 122 /* 123 * struct iwl_prph_scratch_control - control structure 124 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 125 * @reserved: reserved 126 */ 127 struct iwl_prph_scratch_control { 128 __le32 control_flags; 129 __le32 reserved; 130 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 131 132 /* 133 * struct iwl_prph_scratch_ror_cfg - ror config 134 * @ror_base_addr: ror start address 135 * @ror_size: ror size in DWs 136 * @reserved: reserved 137 */ 138 struct iwl_prph_scratch_ror_cfg { 139 __le64 ror_base_addr; 140 __le32 ror_size; 141 __le32 reserved; 142 } __packed; /* PERIPH_SCRATCH_ROR_CFG_S */ 143 144 /* 145 * struct iwl_prph_scratch_hwm_cfg - hwm config 146 * @hwm_base_addr: hwm start address 147 * @hwm_size: hwm size in DWs 148 * @reserved: reserved 149 */ 150 struct iwl_prph_scratch_hwm_cfg { 151 __le64 hwm_base_addr; 152 __le32 hwm_size; 153 __le32 reserved; 154 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 155 156 /* 157 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 158 * @free_rbd_addr: default queue free RB CB base address 159 * @reserved: reserved 160 */ 161 struct iwl_prph_scratch_rbd_cfg { 162 __le64 free_rbd_addr; 163 __le32 reserved; 164 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 165 166 /* 167 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 168 * @version: version information of context info and HW 169 * @control: control flags of FH configurations 170 * @ror_cfg: ror configuration 171 * @hwm_cfg: hwm configuration 172 * @rbd_cfg: default RX queue configuration 173 */ 174 struct iwl_prph_scratch_ctrl_cfg { 175 struct iwl_prph_scratch_version version; 176 struct iwl_prph_scratch_control control; 177 struct iwl_prph_scratch_ror_cfg ror_cfg; 178 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 179 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 180 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 181 182 /* 183 * struct iwl_prph_scratch - peripheral scratch mapping 184 * @ctrl_cfg: control and configuration of prph scratch 185 * @dram: firmware images addresses in DRAM 186 * @reserved: reserved 187 */ 188 struct iwl_prph_scratch { 189 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 190 __le32 reserved[16]; 191 struct iwl_context_info_dram dram; 192 } __packed; /* PERIPH_SCRATCH_S */ 193 194 /* 195 * struct iwl_prph_info - peripheral information 196 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 197 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 198 * @sleep_notif: indicates the peripheral sleep status 199 * @reserved: reserved 200 */ 201 struct iwl_prph_info { 202 __le32 boot_stage_mirror; 203 __le32 ipc_status_mirror; 204 __le32 sleep_notif; 205 __le32 reserved; 206 } __packed; /* PERIPH_INFO_S */ 207 208 /* 209 * struct iwl_context_info_gen3 - device INIT configuration 210 * @version: version of the context information 211 * @size: size of context information in DWs 212 * @config: context in which the peripheral would execute - a subset of 213 * capability csr register published by the peripheral 214 * @prph_info_base_addr: the peripheral information structure start address 215 * @cr_head_idx_arr_base_addr: the completion ring head index array 216 * start address 217 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 218 * start address 219 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 220 * start address 221 * @tr_head_idx_arr_base_addr: the transfer ring head index array 222 * start address 223 * @cr_idx_arr_size: number of entries in the completion ring index array 224 * @tr_idx_arr_size: number of entries in the transfer ring index array 225 * @mtr_base_addr: the message transfer ring start address 226 * @mcr_base_addr: the message completion ring start address 227 * @mtr_size: number of entries which the message transfer ring can hold 228 * @mcr_size: number of entries which the message completion ring can hold 229 * @mtr_doorbell_vec: the doorbell vector associated with the message 230 * transfer ring 231 * @mcr_doorbell_vec: the doorbell vector associated with the message 232 * completion ring 233 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 234 * completing a transfer descriptor in the message transfer ring 235 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 236 * completing a completion descriptor in the message completion ring 237 * @mtr_opt_header_size: the size of the optional header in the transfer 238 * descriptor associated with the message transfer ring in DWs 239 * @mtr_opt_footer_size: the size of the optional footer in the transfer 240 * descriptor associated with the message transfer ring in DWs 241 * @mcr_opt_header_size: the size of the optional header in the completion 242 * descriptor associated with the message completion ring in DWs 243 * @mcr_opt_footer_size: the size of the optional footer in the completion 244 * descriptor associated with the message completion ring in DWs 245 * @msg_rings_ctrl_flags: message rings control flags 246 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 247 * after updating the Peripheral Information structure 248 * @prph_scratch_base_addr: the peripheral scratch structure start address 249 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 250 * @reserved: reserved 251 */ 252 struct iwl_context_info_gen3 { 253 __le16 version; 254 __le16 size; 255 __le32 config; 256 __le64 prph_info_base_addr; 257 __le64 cr_head_idx_arr_base_addr; 258 __le64 tr_tail_idx_arr_base_addr; 259 __le64 cr_tail_idx_arr_base_addr; 260 __le64 tr_head_idx_arr_base_addr; 261 __le16 cr_idx_arr_size; 262 __le16 tr_idx_arr_size; 263 __le64 mtr_base_addr; 264 __le64 mcr_base_addr; 265 __le16 mtr_size; 266 __le16 mcr_size; 267 __le16 mtr_doorbell_vec; 268 __le16 mcr_doorbell_vec; 269 __le16 mtr_msi_vec; 270 __le16 mcr_msi_vec; 271 u8 mtr_opt_header_size; 272 u8 mtr_opt_footer_size; 273 u8 mcr_opt_header_size; 274 u8 mcr_opt_footer_size; 275 __le16 msg_rings_ctrl_flags; 276 __le16 prph_info_msi_vec; 277 __le64 prph_scratch_base_addr; 278 __le32 prph_scratch_size; 279 __le32 reserved; 280 } __packed; /* IPC_CONTEXT_INFO_S */ 281 282 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 283 const struct fw_img *fw); 284 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans); 285 286 #endif /* __iwl_context_info_file_gen3_h__ */ 287