1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2018, 2020 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2018, 2020 Intel Corporation 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * * Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * * Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * * Neither the name Intel Corporation nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 * 50 *****************************************************************************/ 51 #ifndef __iwl_context_info_file_gen3_h__ 52 #define __iwl_context_info_file_gen3_h__ 53 54 #include "iwl-context-info.h" 55 56 #define CSR_CTXT_INFO_BOOT_CTRL 0x0 57 #define CSR_CTXT_INFO_ADDR 0x118 58 #define CSR_IML_DATA_ADDR 0x120 59 #define CSR_IML_SIZE_ADDR 0x128 60 #define CSR_IML_RESP_ADDR 0x12c 61 62 /* Set bit for enabling automatic function boot */ 63 #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 64 /* Set bit for initiating function boot */ 65 #define CSR_AUTO_FUNC_INIT BIT(7) 66 67 /** 68 * enum iwl_prph_scratch_mtr_format - tfd size configuration 69 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 70 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 71 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 72 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 73 */ 74 enum iwl_prph_scratch_mtr_format { 75 IWL_PRPH_MTR_FORMAT_16B = 0x0, 76 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 77 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 78 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 79 }; 80 81 /** 82 * enum iwl_prph_scratch_flags - PRPH scratch control flags 83 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 84 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 85 * in hwm config. 86 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 87 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 88 * multicomm. 89 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 90 * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 91 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 92 * completion descriptor, 1 for responses (legacy) 93 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 94 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 95 * 3: 256 bit. 96 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 97 * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 98 * appropriately; use the below values for this. 99 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 100 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 101 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 102 */ 103 enum iwl_prph_scratch_flags { 104 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 105 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 106 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 107 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 108 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 109 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 110 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 111 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 112 IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 113 IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 114 IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 115 IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 116 }; 117 118 /* 119 * struct iwl_prph_scratch_version - version structure 120 * @mac_id: SKU and revision id 121 * @version: prph scratch information version id 122 * @size: the size of the context information in DWs 123 * @reserved: reserved 124 */ 125 struct iwl_prph_scratch_version { 126 __le16 mac_id; 127 __le16 version; 128 __le16 size; 129 __le16 reserved; 130 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 131 132 /* 133 * struct iwl_prph_scratch_control - control structure 134 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 135 * @reserved: reserved 136 */ 137 struct iwl_prph_scratch_control { 138 __le32 control_flags; 139 __le32 reserved; 140 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 141 142 /* 143 * struct iwl_prph_scratch_pnvm_cfg - ror config 144 * @pnvm_base_addr: PNVM start address 145 * @pnvm_size: PNVM size in DWs 146 * @reserved: reserved 147 */ 148 struct iwl_prph_scratch_pnvm_cfg { 149 __le64 pnvm_base_addr; 150 __le32 pnvm_size; 151 __le32 reserved; 152 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 153 154 /* 155 * struct iwl_prph_scratch_hwm_cfg - hwm config 156 * @hwm_base_addr: hwm start address 157 * @hwm_size: hwm size in DWs 158 * @reserved: reserved 159 */ 160 struct iwl_prph_scratch_hwm_cfg { 161 __le64 hwm_base_addr; 162 __le32 hwm_size; 163 __le32 reserved; 164 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 165 166 /* 167 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 168 * @free_rbd_addr: default queue free RB CB base address 169 * @reserved: reserved 170 */ 171 struct iwl_prph_scratch_rbd_cfg { 172 __le64 free_rbd_addr; 173 __le32 reserved; 174 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 175 176 /* 177 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 178 * @version: version information of context info and HW 179 * @control: control flags of FH configurations 180 * @pnvm_cfg: ror configuration 181 * @hwm_cfg: hwm configuration 182 * @rbd_cfg: default RX queue configuration 183 */ 184 struct iwl_prph_scratch_ctrl_cfg { 185 struct iwl_prph_scratch_version version; 186 struct iwl_prph_scratch_control control; 187 struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 188 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 189 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 190 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 191 192 /* 193 * struct iwl_prph_scratch - peripheral scratch mapping 194 * @ctrl_cfg: control and configuration of prph scratch 195 * @dram: firmware images addresses in DRAM 196 * @reserved: reserved 197 */ 198 struct iwl_prph_scratch { 199 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 200 __le32 reserved[16]; 201 struct iwl_context_info_dram dram; 202 } __packed; /* PERIPH_SCRATCH_S */ 203 204 /* 205 * struct iwl_prph_info - peripheral information 206 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 207 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 208 * @sleep_notif: indicates the peripheral sleep status 209 * @reserved: reserved 210 */ 211 struct iwl_prph_info { 212 __le32 boot_stage_mirror; 213 __le32 ipc_status_mirror; 214 __le32 sleep_notif; 215 __le32 reserved; 216 } __packed; /* PERIPH_INFO_S */ 217 218 /* 219 * struct iwl_context_info_gen3 - device INIT configuration 220 * @version: version of the context information 221 * @size: size of context information in DWs 222 * @config: context in which the peripheral would execute - a subset of 223 * capability csr register published by the peripheral 224 * @prph_info_base_addr: the peripheral information structure start address 225 * @cr_head_idx_arr_base_addr: the completion ring head index array 226 * start address 227 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 228 * start address 229 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 230 * start address 231 * @tr_head_idx_arr_base_addr: the transfer ring head index array 232 * start address 233 * @cr_idx_arr_size: number of entries in the completion ring index array 234 * @tr_idx_arr_size: number of entries in the transfer ring index array 235 * @mtr_base_addr: the message transfer ring start address 236 * @mcr_base_addr: the message completion ring start address 237 * @mtr_size: number of entries which the message transfer ring can hold 238 * @mcr_size: number of entries which the message completion ring can hold 239 * @mtr_doorbell_vec: the doorbell vector associated with the message 240 * transfer ring 241 * @mcr_doorbell_vec: the doorbell vector associated with the message 242 * completion ring 243 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 244 * completing a transfer descriptor in the message transfer ring 245 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 246 * completing a completion descriptor in the message completion ring 247 * @mtr_opt_header_size: the size of the optional header in the transfer 248 * descriptor associated with the message transfer ring in DWs 249 * @mtr_opt_footer_size: the size of the optional footer in the transfer 250 * descriptor associated with the message transfer ring in DWs 251 * @mcr_opt_header_size: the size of the optional header in the completion 252 * descriptor associated with the message completion ring in DWs 253 * @mcr_opt_footer_size: the size of the optional footer in the completion 254 * descriptor associated with the message completion ring in DWs 255 * @msg_rings_ctrl_flags: message rings control flags 256 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 257 * after updating the Peripheral Information structure 258 * @prph_scratch_base_addr: the peripheral scratch structure start address 259 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 260 * @reserved: reserved 261 */ 262 struct iwl_context_info_gen3 { 263 __le16 version; 264 __le16 size; 265 __le32 config; 266 __le64 prph_info_base_addr; 267 __le64 cr_head_idx_arr_base_addr; 268 __le64 tr_tail_idx_arr_base_addr; 269 __le64 cr_tail_idx_arr_base_addr; 270 __le64 tr_head_idx_arr_base_addr; 271 __le16 cr_idx_arr_size; 272 __le16 tr_idx_arr_size; 273 __le64 mtr_base_addr; 274 __le64 mcr_base_addr; 275 __le16 mtr_size; 276 __le16 mcr_size; 277 __le16 mtr_doorbell_vec; 278 __le16 mcr_doorbell_vec; 279 __le16 mtr_msi_vec; 280 __le16 mcr_msi_vec; 281 u8 mtr_opt_header_size; 282 u8 mtr_opt_footer_size; 283 u8 mcr_opt_header_size; 284 u8 mcr_opt_footer_size; 285 __le16 msg_rings_ctrl_flags; 286 __le16 prph_info_msi_vec; 287 __le64 prph_scratch_base_addr; 288 __le32 prph_scratch_size; 289 __le32 reserved; 290 } __packed; /* IPC_CONTEXT_INFO_S */ 291 292 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 293 const struct fw_img *fw); 294 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans); 295 296 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 297 const void *data, u32 len); 298 299 #endif /* __iwl_context_info_file_gen3_h__ */ 300