1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, 2020-2022 Intel Corporation 4 */ 5 #ifndef __iwl_context_info_file_gen3_h__ 6 #define __iwl_context_info_file_gen3_h__ 7 8 #include "iwl-context-info.h" 9 10 #define CSR_CTXT_INFO_BOOT_CTRL 0x0 11 #define CSR_CTXT_INFO_ADDR 0x118 12 #define CSR_IML_DATA_ADDR 0x120 13 #define CSR_IML_SIZE_ADDR 0x128 14 #define CSR_IML_RESP_ADDR 0x12c 15 16 /* Set bit for enabling automatic function boot */ 17 #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 18 /* Set bit for initiating function boot */ 19 #define CSR_AUTO_FUNC_INIT BIT(7) 20 21 /** 22 * enum iwl_prph_scratch_mtr_format - tfd size configuration 23 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 24 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 25 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 26 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 27 */ 28 enum iwl_prph_scratch_mtr_format { 29 IWL_PRPH_MTR_FORMAT_16B = 0x0, 30 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 31 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 32 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 33 }; 34 35 /** 36 * enum iwl_prph_scratch_flags - PRPH scratch control flags 37 * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 38 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 39 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 40 * in hwm config. 41 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 42 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 43 * multicomm. 44 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 45 * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 46 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 47 * completion descriptor, 1 for responses (legacy) 48 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 49 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 50 * 3: 256 bit. 51 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 52 * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 53 * appropriately; use the below values for this. 54 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 55 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 56 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 57 */ 58 enum iwl_prph_scratch_flags { 59 IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1), 60 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 61 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 62 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 63 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 64 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 65 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 66 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 67 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 68 IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 69 IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 70 IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 71 IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 72 }; 73 74 /* 75 * struct iwl_prph_scratch_version - version structure 76 * @mac_id: SKU and revision id 77 * @version: prph scratch information version id 78 * @size: the size of the context information in DWs 79 * @reserved: reserved 80 */ 81 struct iwl_prph_scratch_version { 82 __le16 mac_id; 83 __le16 version; 84 __le16 size; 85 __le16 reserved; 86 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 87 88 /* 89 * struct iwl_prph_scratch_control - control structure 90 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 91 * @reserved: reserved 92 */ 93 struct iwl_prph_scratch_control { 94 __le32 control_flags; 95 __le32 reserved; 96 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 97 98 /* 99 * struct iwl_prph_scratch_pnvm_cfg - ror config 100 * @pnvm_base_addr: PNVM start address 101 * @pnvm_size: PNVM size in DWs 102 * @reserved: reserved 103 */ 104 struct iwl_prph_scratch_pnvm_cfg { 105 __le64 pnvm_base_addr; 106 __le32 pnvm_size; 107 __le32 reserved; 108 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 109 110 /* 111 * struct iwl_prph_scratch_hwm_cfg - hwm config 112 * @hwm_base_addr: hwm start address 113 * @hwm_size: hwm size in DWs 114 * @debug_token_config: debug preset 115 */ 116 struct iwl_prph_scratch_hwm_cfg { 117 __le64 hwm_base_addr; 118 __le32 hwm_size; 119 __le32 debug_token_config; 120 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 121 122 /* 123 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 124 * @free_rbd_addr: default queue free RB CB base address 125 * @reserved: reserved 126 */ 127 struct iwl_prph_scratch_rbd_cfg { 128 __le64 free_rbd_addr; 129 __le32 reserved; 130 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 131 132 /* 133 * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table 134 * @base_addr: reduce power table address 135 * @size: table size in dwords 136 */ 137 struct iwl_prph_scratch_uefi_cfg { 138 __le64 base_addr; 139 __le32 size; 140 __le32 reserved; 141 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 142 143 /* 144 * struct iwl_prph_scratch_step_cfg - prph scratch step configuration 145 * @mbx_addr_0: [0:7] revision, 146 * [8:15] cnvi_to_cnvr length, 147 * [16:23] cnvr_to_cnvi channel length, 148 * [24:31] radio1 reserved 149 * @mbx_addr_1: [0:7] radio2 reserved 150 */ 151 152 struct iwl_prph_scratch_step_cfg { 153 __le32 mbx_addr_0; 154 __le32 mbx_addr_1; 155 } __packed; 156 157 /* 158 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 159 * @version: version information of context info and HW 160 * @control: control flags of FH configurations 161 * @pnvm_cfg: ror configuration 162 * @hwm_cfg: hwm configuration 163 * @rbd_cfg: default RX queue configuration 164 * @step_cfg: step configuration 165 */ 166 struct iwl_prph_scratch_ctrl_cfg { 167 struct iwl_prph_scratch_version version; 168 struct iwl_prph_scratch_control control; 169 struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 170 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 171 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 172 struct iwl_prph_scratch_uefi_cfg reduce_power_cfg; 173 struct iwl_prph_scratch_step_cfg step_cfg; 174 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 175 176 /* 177 * struct iwl_prph_scratch - peripheral scratch mapping 178 * @ctrl_cfg: control and configuration of prph scratch 179 * @dram: firmware images addresses in DRAM 180 * @reserved: reserved 181 */ 182 struct iwl_prph_scratch { 183 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 184 __le32 reserved[10]; 185 struct iwl_context_info_dram dram; 186 } __packed; /* PERIPH_SCRATCH_S */ 187 188 /* 189 * struct iwl_prph_info - peripheral information 190 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 191 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 192 * @sleep_notif: indicates the peripheral sleep status 193 * @reserved: reserved 194 */ 195 struct iwl_prph_info { 196 __le32 boot_stage_mirror; 197 __le32 ipc_status_mirror; 198 __le32 sleep_notif; 199 __le32 reserved; 200 } __packed; /* PERIPH_INFO_S */ 201 202 /* 203 * struct iwl_context_info_gen3 - device INIT configuration 204 * @version: version of the context information 205 * @size: size of context information in DWs 206 * @config: context in which the peripheral would execute - a subset of 207 * capability csr register published by the peripheral 208 * @prph_info_base_addr: the peripheral information structure start address 209 * @cr_head_idx_arr_base_addr: the completion ring head index array 210 * start address 211 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 212 * start address 213 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 214 * start address 215 * @tr_head_idx_arr_base_addr: the transfer ring head index array 216 * start address 217 * @cr_idx_arr_size: number of entries in the completion ring index array 218 * @tr_idx_arr_size: number of entries in the transfer ring index array 219 * @mtr_base_addr: the message transfer ring start address 220 * @mcr_base_addr: the message completion ring start address 221 * @mtr_size: number of entries which the message transfer ring can hold 222 * @mcr_size: number of entries which the message completion ring can hold 223 * @mtr_doorbell_vec: the doorbell vector associated with the message 224 * transfer ring 225 * @mcr_doorbell_vec: the doorbell vector associated with the message 226 * completion ring 227 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 228 * completing a transfer descriptor in the message transfer ring 229 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 230 * completing a completion descriptor in the message completion ring 231 * @mtr_opt_header_size: the size of the optional header in the transfer 232 * descriptor associated with the message transfer ring in DWs 233 * @mtr_opt_footer_size: the size of the optional footer in the transfer 234 * descriptor associated with the message transfer ring in DWs 235 * @mcr_opt_header_size: the size of the optional header in the completion 236 * descriptor associated with the message completion ring in DWs 237 * @mcr_opt_footer_size: the size of the optional footer in the completion 238 * descriptor associated with the message completion ring in DWs 239 * @msg_rings_ctrl_flags: message rings control flags 240 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 241 * after updating the Peripheral Information structure 242 * @prph_scratch_base_addr: the peripheral scratch structure start address 243 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 244 * @reserved: reserved 245 */ 246 struct iwl_context_info_gen3 { 247 __le16 version; 248 __le16 size; 249 __le32 config; 250 __le64 prph_info_base_addr; 251 __le64 cr_head_idx_arr_base_addr; 252 __le64 tr_tail_idx_arr_base_addr; 253 __le64 cr_tail_idx_arr_base_addr; 254 __le64 tr_head_idx_arr_base_addr; 255 __le16 cr_idx_arr_size; 256 __le16 tr_idx_arr_size; 257 __le64 mtr_base_addr; 258 __le64 mcr_base_addr; 259 __le16 mtr_size; 260 __le16 mcr_size; 261 __le16 mtr_doorbell_vec; 262 __le16 mcr_doorbell_vec; 263 __le16 mtr_msi_vec; 264 __le16 mcr_msi_vec; 265 u8 mtr_opt_header_size; 266 u8 mtr_opt_footer_size; 267 u8 mcr_opt_header_size; 268 u8 mcr_opt_footer_size; 269 __le16 msg_rings_ctrl_flags; 270 __le16 prph_info_msi_vec; 271 __le64 prph_scratch_base_addr; 272 __le32 prph_scratch_size; 273 __le32 reserved; 274 } __packed; /* IPC_CONTEXT_INFO_S */ 275 276 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 277 const struct fw_img *fw); 278 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive); 279 280 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 281 const void *data, u32 len); 282 int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 283 const void *data, u32 len); 284 int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans, 285 u32 mbx_addr_0_step, u32 mbx_addr_1_step); 286 #endif /* __iwl_context_info_file_gen3_h__ */ 287