1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, 2020-2022 Intel Corporation 4 */ 5 #ifndef __iwl_context_info_file_gen3_h__ 6 #define __iwl_context_info_file_gen3_h__ 7 8 #include "iwl-context-info.h" 9 10 #define CSR_CTXT_INFO_BOOT_CTRL 0x0 11 #define CSR_CTXT_INFO_ADDR 0x118 12 #define CSR_IML_DATA_ADDR 0x120 13 #define CSR_IML_SIZE_ADDR 0x128 14 #define CSR_IML_RESP_ADDR 0x12c 15 16 #define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2 17 18 /* Set bit for enabling automatic function boot */ 19 #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 20 /* Set bit for initiating function boot */ 21 #define CSR_AUTO_FUNC_INIT BIT(7) 22 23 /** 24 * enum iwl_prph_scratch_mtr_format - tfd size configuration 25 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 26 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 27 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 28 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 29 */ 30 enum iwl_prph_scratch_mtr_format { 31 IWL_PRPH_MTR_FORMAT_16B = 0x0, 32 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 33 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 34 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 35 }; 36 37 /** 38 * enum iwl_prph_scratch_flags - PRPH scratch control flags 39 * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 40 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 41 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 42 * in hwm config. 43 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 44 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 45 * multicomm. 46 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 47 * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 48 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 49 * completion descriptor, 1 for responses (legacy) 50 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 51 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 52 * 3: 256 bit. 53 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 54 * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 55 * appropriately; use the below values for this. 56 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 57 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 58 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 59 */ 60 enum iwl_prph_scratch_flags { 61 IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1), 62 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 63 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 64 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 65 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 66 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 67 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 68 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 69 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 70 IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 71 IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 72 IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 73 IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 74 }; 75 76 /* 77 * struct iwl_prph_scratch_version - version structure 78 * @mac_id: SKU and revision id 79 * @version: prph scratch information version id 80 * @size: the size of the context information in DWs 81 * @reserved: reserved 82 */ 83 struct iwl_prph_scratch_version { 84 __le16 mac_id; 85 __le16 version; 86 __le16 size; 87 __le16 reserved; 88 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 89 90 /* 91 * struct iwl_prph_scratch_control - control structure 92 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 93 * @reserved: reserved 94 */ 95 struct iwl_prph_scratch_control { 96 __le32 control_flags; 97 __le32 reserved; 98 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 99 100 /* 101 * struct iwl_prph_scratch_pnvm_cfg - ror config 102 * @pnvm_base_addr: PNVM start address 103 * @pnvm_size: PNVM size in DWs 104 * @reserved: reserved 105 */ 106 struct iwl_prph_scratch_pnvm_cfg { 107 __le64 pnvm_base_addr; 108 __le32 pnvm_size; 109 __le32 reserved; 110 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 111 112 /* 113 * struct iwl_prph_scratch_hwm_cfg - hwm config 114 * @hwm_base_addr: hwm start address 115 * @hwm_size: hwm size in DWs 116 * @debug_token_config: debug preset 117 */ 118 struct iwl_prph_scratch_hwm_cfg { 119 __le64 hwm_base_addr; 120 __le32 hwm_size; 121 __le32 debug_token_config; 122 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 123 124 /* 125 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 126 * @free_rbd_addr: default queue free RB CB base address 127 * @reserved: reserved 128 */ 129 struct iwl_prph_scratch_rbd_cfg { 130 __le64 free_rbd_addr; 131 __le32 reserved; 132 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 133 134 /* 135 * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table 136 * @base_addr: reduce power table address 137 * @size: table size in dwords 138 */ 139 struct iwl_prph_scratch_uefi_cfg { 140 __le64 base_addr; 141 __le32 size; 142 __le32 reserved; 143 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 144 145 /* 146 * struct iwl_prph_scratch_step_cfg - prph scratch step configuration 147 * @mbx_addr_0: [0:7] revision, 148 * [8:15] cnvi_to_cnvr length, 149 * [16:23] cnvr_to_cnvi channel length, 150 * [24:31] radio1 reserved 151 * @mbx_addr_1: [0:7] radio2 reserved 152 */ 153 154 struct iwl_prph_scratch_step_cfg { 155 __le32 mbx_addr_0; 156 __le32 mbx_addr_1; 157 } __packed; 158 159 /* 160 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 161 * @version: version information of context info and HW 162 * @control: control flags of FH configurations 163 * @pnvm_cfg: ror configuration 164 * @hwm_cfg: hwm configuration 165 * @rbd_cfg: default RX queue configuration 166 * @step_cfg: step configuration 167 */ 168 struct iwl_prph_scratch_ctrl_cfg { 169 struct iwl_prph_scratch_version version; 170 struct iwl_prph_scratch_control control; 171 struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 172 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 173 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 174 struct iwl_prph_scratch_uefi_cfg reduce_power_cfg; 175 struct iwl_prph_scratch_step_cfg step_cfg; 176 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 177 178 /* 179 * struct iwl_prph_scratch - peripheral scratch mapping 180 * @ctrl_cfg: control and configuration of prph scratch 181 * @dram: firmware images addresses in DRAM 182 * @reserved: reserved 183 */ 184 struct iwl_prph_scratch { 185 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 186 __le32 reserved[10]; 187 struct iwl_context_info_dram dram; 188 } __packed; /* PERIPH_SCRATCH_S */ 189 190 /* 191 * struct iwl_prph_info - peripheral information 192 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 193 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 194 * @sleep_notif: indicates the peripheral sleep status 195 * @reserved: reserved 196 */ 197 struct iwl_prph_info { 198 __le32 boot_stage_mirror; 199 __le32 ipc_status_mirror; 200 __le32 sleep_notif; 201 __le32 reserved; 202 } __packed; /* PERIPH_INFO_S */ 203 204 /* 205 * struct iwl_context_info_gen3 - device INIT configuration 206 * @version: version of the context information 207 * @size: size of context information in DWs 208 * @config: context in which the peripheral would execute - a subset of 209 * capability csr register published by the peripheral 210 * @prph_info_base_addr: the peripheral information structure start address 211 * @cr_head_idx_arr_base_addr: the completion ring head index array 212 * start address 213 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 214 * start address 215 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 216 * start address 217 * @tr_head_idx_arr_base_addr: the transfer ring head index array 218 * start address 219 * @cr_idx_arr_size: number of entries in the completion ring index array 220 * @tr_idx_arr_size: number of entries in the transfer ring index array 221 * @mtr_base_addr: the message transfer ring start address 222 * @mcr_base_addr: the message completion ring start address 223 * @mtr_size: number of entries which the message transfer ring can hold 224 * @mcr_size: number of entries which the message completion ring can hold 225 * @mtr_doorbell_vec: the doorbell vector associated with the message 226 * transfer ring 227 * @mcr_doorbell_vec: the doorbell vector associated with the message 228 * completion ring 229 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 230 * completing a transfer descriptor in the message transfer ring 231 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 232 * completing a completion descriptor in the message completion ring 233 * @mtr_opt_header_size: the size of the optional header in the transfer 234 * descriptor associated with the message transfer ring in DWs 235 * @mtr_opt_footer_size: the size of the optional footer in the transfer 236 * descriptor associated with the message transfer ring in DWs 237 * @mcr_opt_header_size: the size of the optional header in the completion 238 * descriptor associated with the message completion ring in DWs 239 * @mcr_opt_footer_size: the size of the optional footer in the completion 240 * descriptor associated with the message completion ring in DWs 241 * @msg_rings_ctrl_flags: message rings control flags 242 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 243 * after updating the Peripheral Information structure 244 * @prph_scratch_base_addr: the peripheral scratch structure start address 245 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 246 * @reserved: reserved 247 */ 248 struct iwl_context_info_gen3 { 249 __le16 version; 250 __le16 size; 251 __le32 config; 252 __le64 prph_info_base_addr; 253 __le64 cr_head_idx_arr_base_addr; 254 __le64 tr_tail_idx_arr_base_addr; 255 __le64 cr_tail_idx_arr_base_addr; 256 __le64 tr_head_idx_arr_base_addr; 257 __le16 cr_idx_arr_size; 258 __le16 tr_idx_arr_size; 259 __le64 mtr_base_addr; 260 __le64 mcr_base_addr; 261 __le16 mtr_size; 262 __le16 mcr_size; 263 __le16 mtr_doorbell_vec; 264 __le16 mcr_doorbell_vec; 265 __le16 mtr_msi_vec; 266 __le16 mcr_msi_vec; 267 u8 mtr_opt_header_size; 268 u8 mtr_opt_footer_size; 269 u8 mcr_opt_header_size; 270 u8 mcr_opt_footer_size; 271 __le16 msg_rings_ctrl_flags; 272 __le16 prph_info_msi_vec; 273 __le64 prph_scratch_base_addr; 274 __le32 prph_scratch_size; 275 __le32 reserved; 276 } __packed; /* IPC_CONTEXT_INFO_S */ 277 278 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 279 const struct fw_img *fw); 280 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive); 281 282 int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, 283 const struct iwl_pnvm_image *pnvm_payloads, 284 const struct iwl_ucode_capabilities *capa); 285 void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 286 const struct iwl_ucode_capabilities *capa); 287 int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 288 const void *data, u32 len); 289 int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans, 290 u32 mbx_addr_0_step, u32 mbx_addr_1_step); 291 #endif /* __iwl_context_info_file_gen3_h__ */ 292