1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2018 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2018 Intel Corporation 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * * Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * * Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * * Neither the name Intel Corporation nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 * 50 *****************************************************************************/ 51 #ifndef __iwl_context_info_file_gen3_h__ 52 #define __iwl_context_info_file_gen3_h__ 53 54 #include "iwl-context-info.h" 55 56 #define CSR_CTXT_INFO_BOOT_CTRL 0x0 57 #define CSR_CTXT_INFO_ADDR 0x118 58 #define CSR_IML_DATA_ADDR 0x120 59 #define CSR_IML_SIZE_ADDR 0x128 60 61 /* Set bit for enabling automatic function boot */ 62 #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 63 /* Set bit for initiating function boot */ 64 #define CSR_AUTO_FUNC_INIT BIT(7) 65 66 /** 67 * enum iwl_prph_scratch_mtr_format - tfd size configuration 68 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 69 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 70 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 71 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 72 */ 73 enum iwl_prph_scratch_mtr_format { 74 IWL_PRPH_MTR_FORMAT_16B = 0x0, 75 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 76 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 77 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 78 }; 79 80 /** 81 * enum iwl_prph_scratch_flags - PRPH scratch control flags 82 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 83 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 84 * in hwm config. 85 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 86 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 87 * multicomm. 88 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 89 * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 90 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 91 * completion descriptor, 1 for responses (legacy) 92 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 93 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 94 * 3: 256 bit. 95 */ 96 enum iwl_prph_scratch_flags { 97 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 98 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 99 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 100 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 101 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 102 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 103 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 104 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 105 }; 106 107 /* 108 * struct iwl_prph_scratch_version - version structure 109 * @mac_id: SKU and revision id 110 * @version: prph scratch information version id 111 * @size: the size of the context information in DWs 112 * @reserved: reserved 113 */ 114 struct iwl_prph_scratch_version { 115 __le16 mac_id; 116 __le16 version; 117 __le16 size; 118 __le16 reserved; 119 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 120 121 /* 122 * struct iwl_prph_scratch_control - control structure 123 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 124 * @reserved: reserved 125 */ 126 struct iwl_prph_scratch_control { 127 __le32 control_flags; 128 __le32 reserved; 129 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 130 131 /* 132 * struct iwl_prph_scratch_ror_cfg - ror config 133 * @ror_base_addr: ror start address 134 * @ror_size: ror size in DWs 135 * @reserved: reserved 136 */ 137 struct iwl_prph_scratch_ror_cfg { 138 __le64 ror_base_addr; 139 __le32 ror_size; 140 __le32 reserved; 141 } __packed; /* PERIPH_SCRATCH_ROR_CFG_S */ 142 143 /* 144 * struct iwl_prph_scratch_hwm_cfg - hwm config 145 * @hwm_base_addr: hwm start address 146 * @hwm_size: hwm size in DWs 147 * @reserved: reserved 148 */ 149 struct iwl_prph_scratch_hwm_cfg { 150 __le64 hwm_base_addr; 151 __le32 hwm_size; 152 __le32 reserved; 153 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 154 155 /* 156 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 157 * @free_rbd_addr: default queue free RB CB base address 158 * @reserved: reserved 159 */ 160 struct iwl_prph_scratch_rbd_cfg { 161 __le64 free_rbd_addr; 162 __le32 reserved; 163 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 164 165 /* 166 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 167 * @version: version information of context info and HW 168 * @control: control flags of FH configurations 169 * @ror_cfg: ror configuration 170 * @hwm_cfg: hwm configuration 171 * @rbd_cfg: default RX queue configuration 172 */ 173 struct iwl_prph_scratch_ctrl_cfg { 174 struct iwl_prph_scratch_version version; 175 struct iwl_prph_scratch_control control; 176 struct iwl_prph_scratch_ror_cfg ror_cfg; 177 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 178 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 179 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 180 181 /* 182 * struct iwl_prph_scratch - peripheral scratch mapping 183 * @ctrl_cfg: control and configuration of prph scratch 184 * @dram: firmware images addresses in DRAM 185 * @reserved: reserved 186 */ 187 struct iwl_prph_scratch { 188 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 189 __le32 reserved[16]; 190 struct iwl_context_info_dram dram; 191 } __packed; /* PERIPH_SCRATCH_S */ 192 193 /* 194 * struct iwl_prph_info - peripheral information 195 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 196 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 197 * @sleep_notif: indicates the peripheral sleep status 198 * @reserved: reserved 199 */ 200 struct iwl_prph_info { 201 __le32 boot_stage_mirror; 202 __le32 ipc_status_mirror; 203 __le32 sleep_notif; 204 __le32 reserved; 205 } __packed; /* PERIPH_INFO_S */ 206 207 /* 208 * struct iwl_context_info_gen3 - device INIT configuration 209 * @version: version of the context information 210 * @size: size of context information in DWs 211 * @config: context in which the peripheral would execute - a subset of 212 * capability csr register published by the peripheral 213 * @prph_info_base_addr: the peripheral information structure start address 214 * @cr_head_idx_arr_base_addr: the completion ring head index array 215 * start address 216 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 217 * start address 218 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 219 * start address 220 * @tr_head_idx_arr_base_addr: the transfer ring head index array 221 * start address 222 * @cr_idx_arr_size: number of entries in the completion ring index array 223 * @tr_idx_arr_size: number of entries in the transfer ring index array 224 * @mtr_base_addr: the message transfer ring start address 225 * @mcr_base_addr: the message completion ring start address 226 * @mtr_size: number of entries which the message transfer ring can hold 227 * @mcr_size: number of entries which the message completion ring can hold 228 * @mtr_doorbell_vec: the doorbell vector associated with the message 229 * transfer ring 230 * @mcr_doorbell_vec: the doorbell vector associated with the message 231 * completion ring 232 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 233 * completing a transfer descriptor in the message transfer ring 234 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 235 * completing a completion descriptor in the message completion ring 236 * @mtr_opt_header_size: the size of the optional header in the transfer 237 * descriptor associated with the message transfer ring in DWs 238 * @mtr_opt_footer_size: the size of the optional footer in the transfer 239 * descriptor associated with the message transfer ring in DWs 240 * @mcr_opt_header_size: the size of the optional header in the completion 241 * descriptor associated with the message completion ring in DWs 242 * @mcr_opt_footer_size: the size of the optional footer in the completion 243 * descriptor associated with the message completion ring in DWs 244 * @msg_rings_ctrl_flags: message rings control flags 245 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 246 * after updating the Peripheral Information structure 247 * @prph_scratch_base_addr: the peripheral scratch structure start address 248 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 249 * @reserved: reserved 250 */ 251 struct iwl_context_info_gen3 { 252 __le16 version; 253 __le16 size; 254 __le32 config; 255 __le64 prph_info_base_addr; 256 __le64 cr_head_idx_arr_base_addr; 257 __le64 tr_tail_idx_arr_base_addr; 258 __le64 cr_tail_idx_arr_base_addr; 259 __le64 tr_head_idx_arr_base_addr; 260 __le16 cr_idx_arr_size; 261 __le16 tr_idx_arr_size; 262 __le64 mtr_base_addr; 263 __le64 mcr_base_addr; 264 __le16 mtr_size; 265 __le16 mcr_size; 266 __le16 mtr_doorbell_vec; 267 __le16 mcr_doorbell_vec; 268 __le16 mtr_msi_vec; 269 __le16 mcr_msi_vec; 270 u8 mtr_opt_header_size; 271 u8 mtr_opt_footer_size; 272 u8 mcr_opt_header_size; 273 u8 mcr_opt_footer_size; 274 __le16 msg_rings_ctrl_flags; 275 __le16 prph_info_msi_vec; 276 __le64 prph_scratch_base_addr; 277 __le32 prph_scratch_size; 278 __le32 reserved; 279 } __packed; /* IPC_CONTEXT_INFO_S */ 280 281 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 282 const struct fw_img *fw); 283 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans); 284 285 #endif /* __iwl_context_info_file_gen3_h__ */ 286