1*8e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*8e99ea8dSJohannes Berg /* 3*8e99ea8dSJohannes Berg * Copyright (C) 2018, 2020 Intel Corporation 4*8e99ea8dSJohannes Berg */ 52ee82402SGolan Ben Ami #ifndef __iwl_context_info_file_gen3_h__ 62ee82402SGolan Ben Ami #define __iwl_context_info_file_gen3_h__ 72ee82402SGolan Ben Ami 82ee82402SGolan Ben Ami #include "iwl-context-info.h" 92ee82402SGolan Ben Ami 102ee82402SGolan Ben Ami #define CSR_CTXT_INFO_BOOT_CTRL 0x0 112ee82402SGolan Ben Ami #define CSR_CTXT_INFO_ADDR 0x118 122ee82402SGolan Ben Ami #define CSR_IML_DATA_ADDR 0x120 132ee82402SGolan Ben Ami #define CSR_IML_SIZE_ADDR 0x128 149b58419eSGolan Ben Ami #define CSR_IML_RESP_ADDR 0x12c 152ee82402SGolan Ben Ami 162ee82402SGolan Ben Ami /* Set bit for enabling automatic function boot */ 172ee82402SGolan Ben Ami #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 182ee82402SGolan Ben Ami /* Set bit for initiating function boot */ 192ee82402SGolan Ben Ami #define CSR_AUTO_FUNC_INIT BIT(7) 202ee82402SGolan Ben Ami 212ee82402SGolan Ben Ami /** 222ee82402SGolan Ben Ami * enum iwl_prph_scratch_mtr_format - tfd size configuration 232ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 242ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 252ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 262ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 272ee82402SGolan Ben Ami */ 282ee82402SGolan Ben Ami enum iwl_prph_scratch_mtr_format { 292ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_16B = 0x0, 302ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_32B = 0x40000, 312ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_64B = 0x80000, 322ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 332ee82402SGolan Ben Ami }; 342ee82402SGolan Ben Ami 352ee82402SGolan Ben Ami /** 362ee82402SGolan Ben Ami * enum iwl_prph_scratch_flags - PRPH scratch control flags 372ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 382ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 392ee82402SGolan Ben Ami * in hwm config. 402ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 412ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 422ee82402SGolan Ben Ami * multicomm. 432ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 442ee82402SGolan Ben Ami * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 452ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 462ee82402SGolan Ben Ami * completion descriptor, 1 for responses (legacy) 472ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 482ee82402SGolan Ben Ami * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 492ee82402SGolan Ben Ami * 3: 256 bit. 5061576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 5161576240SJohannes Berg * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 5261576240SJohannes Berg * appropriately; use the below values for this. 5361576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 5461576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 553fa965c2SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 562ee82402SGolan Ben Ami */ 572ee82402SGolan Ben Ami enum iwl_prph_scratch_flags { 582ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 592ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 602ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 612ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 622ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 632ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 642ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 652ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 6661576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 6761576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 6861576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 693fa965c2SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 702ee82402SGolan Ben Ami }; 712ee82402SGolan Ben Ami 722ee82402SGolan Ben Ami /* 732ee82402SGolan Ben Ami * struct iwl_prph_scratch_version - version structure 742ee82402SGolan Ben Ami * @mac_id: SKU and revision id 752ee82402SGolan Ben Ami * @version: prph scratch information version id 762ee82402SGolan Ben Ami * @size: the size of the context information in DWs 772ee82402SGolan Ben Ami * @reserved: reserved 782ee82402SGolan Ben Ami */ 792ee82402SGolan Ben Ami struct iwl_prph_scratch_version { 802ee82402SGolan Ben Ami __le16 mac_id; 812ee82402SGolan Ben Ami __le16 version; 822ee82402SGolan Ben Ami __le16 size; 832ee82402SGolan Ben Ami __le16 reserved; 842ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_VERSION_S */ 852ee82402SGolan Ben Ami 862ee82402SGolan Ben Ami /* 872ee82402SGolan Ben Ami * struct iwl_prph_scratch_control - control structure 882ee82402SGolan Ben Ami * @control_flags: context information flags see &enum iwl_prph_scratch_flags 892ee82402SGolan Ben Ami * @reserved: reserved 902ee82402SGolan Ben Ami */ 912ee82402SGolan Ben Ami struct iwl_prph_scratch_control { 922ee82402SGolan Ben Ami __le32 control_flags; 932ee82402SGolan Ben Ami __le32 reserved; 942ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 952ee82402SGolan Ben Ami 962ee82402SGolan Ben Ami /* 977ef3e224SLuca Coelho * struct iwl_prph_scratch_pnvm_cfg - ror config 987ef3e224SLuca Coelho * @pnvm_base_addr: PNVM start address 997ef3e224SLuca Coelho * @pnvm_size: PNVM size in DWs 1002ee82402SGolan Ben Ami * @reserved: reserved 1012ee82402SGolan Ben Ami */ 1027ef3e224SLuca Coelho struct iwl_prph_scratch_pnvm_cfg { 1037ef3e224SLuca Coelho __le64 pnvm_base_addr; 1047ef3e224SLuca Coelho __le32 pnvm_size; 1052ee82402SGolan Ben Ami __le32 reserved; 1067ef3e224SLuca Coelho } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 1072ee82402SGolan Ben Ami 1082ee82402SGolan Ben Ami /* 1092ee82402SGolan Ben Ami * struct iwl_prph_scratch_hwm_cfg - hwm config 1102ee82402SGolan Ben Ami * @hwm_base_addr: hwm start address 1112ee82402SGolan Ben Ami * @hwm_size: hwm size in DWs 1122ee82402SGolan Ben Ami * @reserved: reserved 1132ee82402SGolan Ben Ami */ 1142ee82402SGolan Ben Ami struct iwl_prph_scratch_hwm_cfg { 1152ee82402SGolan Ben Ami __le64 hwm_base_addr; 1162ee82402SGolan Ben Ami __le32 hwm_size; 1172ee82402SGolan Ben Ami __le32 reserved; 1182ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 1192ee82402SGolan Ben Ami 1202ee82402SGolan Ben Ami /* 1212ee82402SGolan Ben Ami * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 1222ee82402SGolan Ben Ami * @free_rbd_addr: default queue free RB CB base address 1232ee82402SGolan Ben Ami * @reserved: reserved 1242ee82402SGolan Ben Ami */ 1252ee82402SGolan Ben Ami struct iwl_prph_scratch_rbd_cfg { 1262ee82402SGolan Ben Ami __le64 free_rbd_addr; 1272ee82402SGolan Ben Ami __le32 reserved; 1282ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 1292ee82402SGolan Ben Ami 1302ee82402SGolan Ben Ami /* 1312ee82402SGolan Ben Ami * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 1322ee82402SGolan Ben Ami * @version: version information of context info and HW 1332ee82402SGolan Ben Ami * @control: control flags of FH configurations 1347ef3e224SLuca Coelho * @pnvm_cfg: ror configuration 1352ee82402SGolan Ben Ami * @hwm_cfg: hwm configuration 1362ee82402SGolan Ben Ami * @rbd_cfg: default RX queue configuration 1372ee82402SGolan Ben Ami */ 1382ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg { 1392ee82402SGolan Ben Ami struct iwl_prph_scratch_version version; 1402ee82402SGolan Ben Ami struct iwl_prph_scratch_control control; 1417ef3e224SLuca Coelho struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 1422ee82402SGolan Ben Ami struct iwl_prph_scratch_hwm_cfg hwm_cfg; 1432ee82402SGolan Ben Ami struct iwl_prph_scratch_rbd_cfg rbd_cfg; 1442ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 1452ee82402SGolan Ben Ami 1462ee82402SGolan Ben Ami /* 1472ee82402SGolan Ben Ami * struct iwl_prph_scratch - peripheral scratch mapping 1482ee82402SGolan Ben Ami * @ctrl_cfg: control and configuration of prph scratch 1492ee82402SGolan Ben Ami * @dram: firmware images addresses in DRAM 1502ee82402SGolan Ben Ami * @reserved: reserved 1512ee82402SGolan Ben Ami */ 1522ee82402SGolan Ben Ami struct iwl_prph_scratch { 1532ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 1542ee82402SGolan Ben Ami __le32 reserved[16]; 1552ee82402SGolan Ben Ami struct iwl_context_info_dram dram; 1562ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_S */ 1572ee82402SGolan Ben Ami 1582ee82402SGolan Ben Ami /* 1592ee82402SGolan Ben Ami * struct iwl_prph_info - peripheral information 1602ee82402SGolan Ben Ami * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 1612ee82402SGolan Ben Ami * @ipc_status_mirror: reflects the value in the IPC Status CSR register 1622ee82402SGolan Ben Ami * @sleep_notif: indicates the peripheral sleep status 1632ee82402SGolan Ben Ami * @reserved: reserved 1642ee82402SGolan Ben Ami */ 1652ee82402SGolan Ben Ami struct iwl_prph_info { 1662ee82402SGolan Ben Ami __le32 boot_stage_mirror; 1672ee82402SGolan Ben Ami __le32 ipc_status_mirror; 1682ee82402SGolan Ben Ami __le32 sleep_notif; 1692ee82402SGolan Ben Ami __le32 reserved; 1702ee82402SGolan Ben Ami } __packed; /* PERIPH_INFO_S */ 1712ee82402SGolan Ben Ami 1722ee82402SGolan Ben Ami /* 1732ee82402SGolan Ben Ami * struct iwl_context_info_gen3 - device INIT configuration 1742ee82402SGolan Ben Ami * @version: version of the context information 1752ee82402SGolan Ben Ami * @size: size of context information in DWs 1762ee82402SGolan Ben Ami * @config: context in which the peripheral would execute - a subset of 1772ee82402SGolan Ben Ami * capability csr register published by the peripheral 1782ee82402SGolan Ben Ami * @prph_info_base_addr: the peripheral information structure start address 1792ee82402SGolan Ben Ami * @cr_head_idx_arr_base_addr: the completion ring head index array 1802ee82402SGolan Ben Ami * start address 1812ee82402SGolan Ben Ami * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 1822ee82402SGolan Ben Ami * start address 1832ee82402SGolan Ben Ami * @cr_tail_idx_arr_base_addr: the completion ring tail index array 1842ee82402SGolan Ben Ami * start address 1852ee82402SGolan Ben Ami * @tr_head_idx_arr_base_addr: the transfer ring head index array 1862ee82402SGolan Ben Ami * start address 1872ee82402SGolan Ben Ami * @cr_idx_arr_size: number of entries in the completion ring index array 1882ee82402SGolan Ben Ami * @tr_idx_arr_size: number of entries in the transfer ring index array 1892ee82402SGolan Ben Ami * @mtr_base_addr: the message transfer ring start address 1902ee82402SGolan Ben Ami * @mcr_base_addr: the message completion ring start address 1912ee82402SGolan Ben Ami * @mtr_size: number of entries which the message transfer ring can hold 1922ee82402SGolan Ben Ami * @mcr_size: number of entries which the message completion ring can hold 1932ee82402SGolan Ben Ami * @mtr_doorbell_vec: the doorbell vector associated with the message 1942ee82402SGolan Ben Ami * transfer ring 1952ee82402SGolan Ben Ami * @mcr_doorbell_vec: the doorbell vector associated with the message 1962ee82402SGolan Ben Ami * completion ring 1972ee82402SGolan Ben Ami * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 1982ee82402SGolan Ben Ami * completing a transfer descriptor in the message transfer ring 1992ee82402SGolan Ben Ami * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 2002ee82402SGolan Ben Ami * completing a completion descriptor in the message completion ring 2012ee82402SGolan Ben Ami * @mtr_opt_header_size: the size of the optional header in the transfer 2022ee82402SGolan Ben Ami * descriptor associated with the message transfer ring in DWs 2032ee82402SGolan Ben Ami * @mtr_opt_footer_size: the size of the optional footer in the transfer 2042ee82402SGolan Ben Ami * descriptor associated with the message transfer ring in DWs 2052ee82402SGolan Ben Ami * @mcr_opt_header_size: the size of the optional header in the completion 2062ee82402SGolan Ben Ami * descriptor associated with the message completion ring in DWs 2072ee82402SGolan Ben Ami * @mcr_opt_footer_size: the size of the optional footer in the completion 2082ee82402SGolan Ben Ami * descriptor associated with the message completion ring in DWs 2092ee82402SGolan Ben Ami * @msg_rings_ctrl_flags: message rings control flags 2102ee82402SGolan Ben Ami * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 2112ee82402SGolan Ben Ami * after updating the Peripheral Information structure 2122ee82402SGolan Ben Ami * @prph_scratch_base_addr: the peripheral scratch structure start address 2132ee82402SGolan Ben Ami * @prph_scratch_size: the size of the peripheral scratch structure in DWs 2142ee82402SGolan Ben Ami * @reserved: reserved 2152ee82402SGolan Ben Ami */ 2162ee82402SGolan Ben Ami struct iwl_context_info_gen3 { 2172ee82402SGolan Ben Ami __le16 version; 2182ee82402SGolan Ben Ami __le16 size; 2192ee82402SGolan Ben Ami __le32 config; 2202ee82402SGolan Ben Ami __le64 prph_info_base_addr; 2212ee82402SGolan Ben Ami __le64 cr_head_idx_arr_base_addr; 2222ee82402SGolan Ben Ami __le64 tr_tail_idx_arr_base_addr; 2232ee82402SGolan Ben Ami __le64 cr_tail_idx_arr_base_addr; 2242ee82402SGolan Ben Ami __le64 tr_head_idx_arr_base_addr; 2252ee82402SGolan Ben Ami __le16 cr_idx_arr_size; 2262ee82402SGolan Ben Ami __le16 tr_idx_arr_size; 2272ee82402SGolan Ben Ami __le64 mtr_base_addr; 2282ee82402SGolan Ben Ami __le64 mcr_base_addr; 2292ee82402SGolan Ben Ami __le16 mtr_size; 2302ee82402SGolan Ben Ami __le16 mcr_size; 2312ee82402SGolan Ben Ami __le16 mtr_doorbell_vec; 2322ee82402SGolan Ben Ami __le16 mcr_doorbell_vec; 2332ee82402SGolan Ben Ami __le16 mtr_msi_vec; 2342ee82402SGolan Ben Ami __le16 mcr_msi_vec; 2352ee82402SGolan Ben Ami u8 mtr_opt_header_size; 2362ee82402SGolan Ben Ami u8 mtr_opt_footer_size; 2372ee82402SGolan Ben Ami u8 mcr_opt_header_size; 2382ee82402SGolan Ben Ami u8 mcr_opt_footer_size; 2392ee82402SGolan Ben Ami __le16 msg_rings_ctrl_flags; 2402ee82402SGolan Ben Ami __le16 prph_info_msi_vec; 2412ee82402SGolan Ben Ami __le64 prph_scratch_base_addr; 2422ee82402SGolan Ben Ami __le32 prph_scratch_size; 2432ee82402SGolan Ben Ami __le32 reserved; 2442ee82402SGolan Ben Ami } __packed; /* IPC_CONTEXT_INFO_S */ 2452ee82402SGolan Ben Ami 2462ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 2472ee82402SGolan Ben Ami const struct fw_img *fw); 2482ee82402SGolan Ben Ami void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans); 2492ee82402SGolan Ben Ami 2506654cd4eSLuca Coelho int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 2516654cd4eSLuca Coelho const void *data, u32 len); 2526654cd4eSLuca Coelho 2532ee82402SGolan Ben Ami #endif /* __iwl_context_info_file_gen3_h__ */ 254