12ee82402SGolan Ben Ami /****************************************************************************** 22ee82402SGolan Ben Ami * 32ee82402SGolan Ben Ami * This file is provided under a dual BSD/GPLv2 license. When using or 42ee82402SGolan Ben Ami * redistributing this file, you may do so under either license. 52ee82402SGolan Ben Ami * 62ee82402SGolan Ben Ami * GPL LICENSE SUMMARY 72ee82402SGolan Ben Ami * 861576240SJohannes Berg * Copyright(c) 2018, 2020 Intel Corporation 92ee82402SGolan Ben Ami * 102ee82402SGolan Ben Ami * This program is free software; you can redistribute it and/or modify 112ee82402SGolan Ben Ami * it under the terms of version 2 of the GNU General Public License as 122ee82402SGolan Ben Ami * published by the Free Software Foundation. 132ee82402SGolan Ben Ami * 142ee82402SGolan Ben Ami * This program is distributed in the hope that it will be useful, but 152ee82402SGolan Ben Ami * WITHOUT ANY WARRANTY; without even the implied warranty of 162ee82402SGolan Ben Ami * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 172ee82402SGolan Ben Ami * General Public License for more details. 182ee82402SGolan Ben Ami * 192ee82402SGolan Ben Ami * BSD LICENSE 202ee82402SGolan Ben Ami * 2161576240SJohannes Berg * Copyright(c) 2018, 2020 Intel Corporation 222ee82402SGolan Ben Ami * All rights reserved. 232ee82402SGolan Ben Ami * 242ee82402SGolan Ben Ami * Redistribution and use in source and binary forms, with or without 252ee82402SGolan Ben Ami * modification, are permitted provided that the following conditions 262ee82402SGolan Ben Ami * are met: 272ee82402SGolan Ben Ami * 282ee82402SGolan Ben Ami * * Redistributions of source code must retain the above copyright 292ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer. 302ee82402SGolan Ben Ami * * Redistributions in binary form must reproduce the above copyright 312ee82402SGolan Ben Ami * notice, this list of conditions and the following disclaimer in 322ee82402SGolan Ben Ami * the documentation and/or other materials provided with the 332ee82402SGolan Ben Ami * distribution. 342ee82402SGolan Ben Ami * * Neither the name Intel Corporation nor the names of its 352ee82402SGolan Ben Ami * contributors may be used to endorse or promote products derived 362ee82402SGolan Ben Ami * from this software without specific prior written permission. 372ee82402SGolan Ben Ami * 382ee82402SGolan Ben Ami * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 392ee82402SGolan Ben Ami * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 402ee82402SGolan Ben Ami * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 412ee82402SGolan Ben Ami * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 422ee82402SGolan Ben Ami * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 432ee82402SGolan Ben Ami * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 442ee82402SGolan Ben Ami * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 452ee82402SGolan Ben Ami * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 462ee82402SGolan Ben Ami * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 472ee82402SGolan Ben Ami * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 482ee82402SGolan Ben Ami * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 492ee82402SGolan Ben Ami * 502ee82402SGolan Ben Ami *****************************************************************************/ 512ee82402SGolan Ben Ami #ifndef __iwl_context_info_file_gen3_h__ 522ee82402SGolan Ben Ami #define __iwl_context_info_file_gen3_h__ 532ee82402SGolan Ben Ami 542ee82402SGolan Ben Ami #include "iwl-context-info.h" 552ee82402SGolan Ben Ami 562ee82402SGolan Ben Ami #define CSR_CTXT_INFO_BOOT_CTRL 0x0 572ee82402SGolan Ben Ami #define CSR_CTXT_INFO_ADDR 0x118 582ee82402SGolan Ben Ami #define CSR_IML_DATA_ADDR 0x120 592ee82402SGolan Ben Ami #define CSR_IML_SIZE_ADDR 0x128 609b58419eSGolan Ben Ami #define CSR_IML_RESP_ADDR 0x12c 612ee82402SGolan Ben Ami 622ee82402SGolan Ben Ami /* Set bit for enabling automatic function boot */ 632ee82402SGolan Ben Ami #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 642ee82402SGolan Ben Ami /* Set bit for initiating function boot */ 652ee82402SGolan Ben Ami #define CSR_AUTO_FUNC_INIT BIT(7) 662ee82402SGolan Ben Ami 672ee82402SGolan Ben Ami /** 682ee82402SGolan Ben Ami * enum iwl_prph_scratch_mtr_format - tfd size configuration 692ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 702ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 712ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 722ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 732ee82402SGolan Ben Ami */ 742ee82402SGolan Ben Ami enum iwl_prph_scratch_mtr_format { 752ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_16B = 0x0, 762ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_32B = 0x40000, 772ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_64B = 0x80000, 782ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 792ee82402SGolan Ben Ami }; 802ee82402SGolan Ben Ami 812ee82402SGolan Ben Ami /** 822ee82402SGolan Ben Ami * enum iwl_prph_scratch_flags - PRPH scratch control flags 832ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 842ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 852ee82402SGolan Ben Ami * in hwm config. 862ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 872ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 882ee82402SGolan Ben Ami * multicomm. 892ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 902ee82402SGolan Ben Ami * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 912ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 922ee82402SGolan Ben Ami * completion descriptor, 1 for responses (legacy) 932ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 942ee82402SGolan Ben Ami * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 952ee82402SGolan Ben Ami * 3: 256 bit. 9661576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 9761576240SJohannes Berg * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 9861576240SJohannes Berg * appropriately; use the below values for this. 9961576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 10061576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 101*3fa965c2SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 1022ee82402SGolan Ben Ami */ 1032ee82402SGolan Ben Ami enum iwl_prph_scratch_flags { 1042ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 1052ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 1062ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 1072ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 1082ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 1092ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 1102ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 1112ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 11261576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 11361576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 11461576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 115*3fa965c2SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 1162ee82402SGolan Ben Ami }; 1172ee82402SGolan Ben Ami 1182ee82402SGolan Ben Ami /* 1192ee82402SGolan Ben Ami * struct iwl_prph_scratch_version - version structure 1202ee82402SGolan Ben Ami * @mac_id: SKU and revision id 1212ee82402SGolan Ben Ami * @version: prph scratch information version id 1222ee82402SGolan Ben Ami * @size: the size of the context information in DWs 1232ee82402SGolan Ben Ami * @reserved: reserved 1242ee82402SGolan Ben Ami */ 1252ee82402SGolan Ben Ami struct iwl_prph_scratch_version { 1262ee82402SGolan Ben Ami __le16 mac_id; 1272ee82402SGolan Ben Ami __le16 version; 1282ee82402SGolan Ben Ami __le16 size; 1292ee82402SGolan Ben Ami __le16 reserved; 1302ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_VERSION_S */ 1312ee82402SGolan Ben Ami 1322ee82402SGolan Ben Ami /* 1332ee82402SGolan Ben Ami * struct iwl_prph_scratch_control - control structure 1342ee82402SGolan Ben Ami * @control_flags: context information flags see &enum iwl_prph_scratch_flags 1352ee82402SGolan Ben Ami * @reserved: reserved 1362ee82402SGolan Ben Ami */ 1372ee82402SGolan Ben Ami struct iwl_prph_scratch_control { 1382ee82402SGolan Ben Ami __le32 control_flags; 1392ee82402SGolan Ben Ami __le32 reserved; 1402ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 1412ee82402SGolan Ben Ami 1422ee82402SGolan Ben Ami /* 1437ef3e224SLuca Coelho * struct iwl_prph_scratch_pnvm_cfg - ror config 1447ef3e224SLuca Coelho * @pnvm_base_addr: PNVM start address 1457ef3e224SLuca Coelho * @pnvm_size: PNVM size in DWs 1462ee82402SGolan Ben Ami * @reserved: reserved 1472ee82402SGolan Ben Ami */ 1487ef3e224SLuca Coelho struct iwl_prph_scratch_pnvm_cfg { 1497ef3e224SLuca Coelho __le64 pnvm_base_addr; 1507ef3e224SLuca Coelho __le32 pnvm_size; 1512ee82402SGolan Ben Ami __le32 reserved; 1527ef3e224SLuca Coelho } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 1532ee82402SGolan Ben Ami 1542ee82402SGolan Ben Ami /* 1552ee82402SGolan Ben Ami * struct iwl_prph_scratch_hwm_cfg - hwm config 1562ee82402SGolan Ben Ami * @hwm_base_addr: hwm start address 1572ee82402SGolan Ben Ami * @hwm_size: hwm size in DWs 1582ee82402SGolan Ben Ami * @reserved: reserved 1592ee82402SGolan Ben Ami */ 1602ee82402SGolan Ben Ami struct iwl_prph_scratch_hwm_cfg { 1612ee82402SGolan Ben Ami __le64 hwm_base_addr; 1622ee82402SGolan Ben Ami __le32 hwm_size; 1632ee82402SGolan Ben Ami __le32 reserved; 1642ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 1652ee82402SGolan Ben Ami 1662ee82402SGolan Ben Ami /* 1672ee82402SGolan Ben Ami * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 1682ee82402SGolan Ben Ami * @free_rbd_addr: default queue free RB CB base address 1692ee82402SGolan Ben Ami * @reserved: reserved 1702ee82402SGolan Ben Ami */ 1712ee82402SGolan Ben Ami struct iwl_prph_scratch_rbd_cfg { 1722ee82402SGolan Ben Ami __le64 free_rbd_addr; 1732ee82402SGolan Ben Ami __le32 reserved; 1742ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 1752ee82402SGolan Ben Ami 1762ee82402SGolan Ben Ami /* 1772ee82402SGolan Ben Ami * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 1782ee82402SGolan Ben Ami * @version: version information of context info and HW 1792ee82402SGolan Ben Ami * @control: control flags of FH configurations 1807ef3e224SLuca Coelho * @pnvm_cfg: ror configuration 1812ee82402SGolan Ben Ami * @hwm_cfg: hwm configuration 1822ee82402SGolan Ben Ami * @rbd_cfg: default RX queue configuration 1832ee82402SGolan Ben Ami */ 1842ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg { 1852ee82402SGolan Ben Ami struct iwl_prph_scratch_version version; 1862ee82402SGolan Ben Ami struct iwl_prph_scratch_control control; 1877ef3e224SLuca Coelho struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 1882ee82402SGolan Ben Ami struct iwl_prph_scratch_hwm_cfg hwm_cfg; 1892ee82402SGolan Ben Ami struct iwl_prph_scratch_rbd_cfg rbd_cfg; 1902ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 1912ee82402SGolan Ben Ami 1922ee82402SGolan Ben Ami /* 1932ee82402SGolan Ben Ami * struct iwl_prph_scratch - peripheral scratch mapping 1942ee82402SGolan Ben Ami * @ctrl_cfg: control and configuration of prph scratch 1952ee82402SGolan Ben Ami * @dram: firmware images addresses in DRAM 1962ee82402SGolan Ben Ami * @reserved: reserved 1972ee82402SGolan Ben Ami */ 1982ee82402SGolan Ben Ami struct iwl_prph_scratch { 1992ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 2002ee82402SGolan Ben Ami __le32 reserved[16]; 2012ee82402SGolan Ben Ami struct iwl_context_info_dram dram; 2022ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_S */ 2032ee82402SGolan Ben Ami 2042ee82402SGolan Ben Ami /* 2052ee82402SGolan Ben Ami * struct iwl_prph_info - peripheral information 2062ee82402SGolan Ben Ami * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 2072ee82402SGolan Ben Ami * @ipc_status_mirror: reflects the value in the IPC Status CSR register 2082ee82402SGolan Ben Ami * @sleep_notif: indicates the peripheral sleep status 2092ee82402SGolan Ben Ami * @reserved: reserved 2102ee82402SGolan Ben Ami */ 2112ee82402SGolan Ben Ami struct iwl_prph_info { 2122ee82402SGolan Ben Ami __le32 boot_stage_mirror; 2132ee82402SGolan Ben Ami __le32 ipc_status_mirror; 2142ee82402SGolan Ben Ami __le32 sleep_notif; 2152ee82402SGolan Ben Ami __le32 reserved; 2162ee82402SGolan Ben Ami } __packed; /* PERIPH_INFO_S */ 2172ee82402SGolan Ben Ami 2182ee82402SGolan Ben Ami /* 2192ee82402SGolan Ben Ami * struct iwl_context_info_gen3 - device INIT configuration 2202ee82402SGolan Ben Ami * @version: version of the context information 2212ee82402SGolan Ben Ami * @size: size of context information in DWs 2222ee82402SGolan Ben Ami * @config: context in which the peripheral would execute - a subset of 2232ee82402SGolan Ben Ami * capability csr register published by the peripheral 2242ee82402SGolan Ben Ami * @prph_info_base_addr: the peripheral information structure start address 2252ee82402SGolan Ben Ami * @cr_head_idx_arr_base_addr: the completion ring head index array 2262ee82402SGolan Ben Ami * start address 2272ee82402SGolan Ben Ami * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 2282ee82402SGolan Ben Ami * start address 2292ee82402SGolan Ben Ami * @cr_tail_idx_arr_base_addr: the completion ring tail index array 2302ee82402SGolan Ben Ami * start address 2312ee82402SGolan Ben Ami * @tr_head_idx_arr_base_addr: the transfer ring head index array 2322ee82402SGolan Ben Ami * start address 2332ee82402SGolan Ben Ami * @cr_idx_arr_size: number of entries in the completion ring index array 2342ee82402SGolan Ben Ami * @tr_idx_arr_size: number of entries in the transfer ring index array 2352ee82402SGolan Ben Ami * @mtr_base_addr: the message transfer ring start address 2362ee82402SGolan Ben Ami * @mcr_base_addr: the message completion ring start address 2372ee82402SGolan Ben Ami * @mtr_size: number of entries which the message transfer ring can hold 2382ee82402SGolan Ben Ami * @mcr_size: number of entries which the message completion ring can hold 2392ee82402SGolan Ben Ami * @mtr_doorbell_vec: the doorbell vector associated with the message 2402ee82402SGolan Ben Ami * transfer ring 2412ee82402SGolan Ben Ami * @mcr_doorbell_vec: the doorbell vector associated with the message 2422ee82402SGolan Ben Ami * completion ring 2432ee82402SGolan Ben Ami * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 2442ee82402SGolan Ben Ami * completing a transfer descriptor in the message transfer ring 2452ee82402SGolan Ben Ami * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 2462ee82402SGolan Ben Ami * completing a completion descriptor in the message completion ring 2472ee82402SGolan Ben Ami * @mtr_opt_header_size: the size of the optional header in the transfer 2482ee82402SGolan Ben Ami * descriptor associated with the message transfer ring in DWs 2492ee82402SGolan Ben Ami * @mtr_opt_footer_size: the size of the optional footer in the transfer 2502ee82402SGolan Ben Ami * descriptor associated with the message transfer ring in DWs 2512ee82402SGolan Ben Ami * @mcr_opt_header_size: the size of the optional header in the completion 2522ee82402SGolan Ben Ami * descriptor associated with the message completion ring in DWs 2532ee82402SGolan Ben Ami * @mcr_opt_footer_size: the size of the optional footer in the completion 2542ee82402SGolan Ben Ami * descriptor associated with the message completion ring in DWs 2552ee82402SGolan Ben Ami * @msg_rings_ctrl_flags: message rings control flags 2562ee82402SGolan Ben Ami * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 2572ee82402SGolan Ben Ami * after updating the Peripheral Information structure 2582ee82402SGolan Ben Ami * @prph_scratch_base_addr: the peripheral scratch structure start address 2592ee82402SGolan Ben Ami * @prph_scratch_size: the size of the peripheral scratch structure in DWs 2602ee82402SGolan Ben Ami * @reserved: reserved 2612ee82402SGolan Ben Ami */ 2622ee82402SGolan Ben Ami struct iwl_context_info_gen3 { 2632ee82402SGolan Ben Ami __le16 version; 2642ee82402SGolan Ben Ami __le16 size; 2652ee82402SGolan Ben Ami __le32 config; 2662ee82402SGolan Ben Ami __le64 prph_info_base_addr; 2672ee82402SGolan Ben Ami __le64 cr_head_idx_arr_base_addr; 2682ee82402SGolan Ben Ami __le64 tr_tail_idx_arr_base_addr; 2692ee82402SGolan Ben Ami __le64 cr_tail_idx_arr_base_addr; 2702ee82402SGolan Ben Ami __le64 tr_head_idx_arr_base_addr; 2712ee82402SGolan Ben Ami __le16 cr_idx_arr_size; 2722ee82402SGolan Ben Ami __le16 tr_idx_arr_size; 2732ee82402SGolan Ben Ami __le64 mtr_base_addr; 2742ee82402SGolan Ben Ami __le64 mcr_base_addr; 2752ee82402SGolan Ben Ami __le16 mtr_size; 2762ee82402SGolan Ben Ami __le16 mcr_size; 2772ee82402SGolan Ben Ami __le16 mtr_doorbell_vec; 2782ee82402SGolan Ben Ami __le16 mcr_doorbell_vec; 2792ee82402SGolan Ben Ami __le16 mtr_msi_vec; 2802ee82402SGolan Ben Ami __le16 mcr_msi_vec; 2812ee82402SGolan Ben Ami u8 mtr_opt_header_size; 2822ee82402SGolan Ben Ami u8 mtr_opt_footer_size; 2832ee82402SGolan Ben Ami u8 mcr_opt_header_size; 2842ee82402SGolan Ben Ami u8 mcr_opt_footer_size; 2852ee82402SGolan Ben Ami __le16 msg_rings_ctrl_flags; 2862ee82402SGolan Ben Ami __le16 prph_info_msi_vec; 2872ee82402SGolan Ben Ami __le64 prph_scratch_base_addr; 2882ee82402SGolan Ben Ami __le32 prph_scratch_size; 2892ee82402SGolan Ben Ami __le32 reserved; 2902ee82402SGolan Ben Ami } __packed; /* IPC_CONTEXT_INFO_S */ 2912ee82402SGolan Ben Ami 2922ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 2932ee82402SGolan Ben Ami const struct fw_img *fw); 2942ee82402SGolan Ben Ami void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans); 2952ee82402SGolan Ben Ami 2966654cd4eSLuca Coelho int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 2976654cd4eSLuca Coelho const void *data, u32 len); 2986654cd4eSLuca Coelho 2992ee82402SGolan Ben Ami #endif /* __iwl_context_info_file_gen3_h__ */ 300