18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 28e99ea8dSJohannes Berg /* 31c4db761SMukesh Sisodiya * Copyright (C) 2018, 2020-2022 Intel Corporation 48e99ea8dSJohannes Berg */ 52ee82402SGolan Ben Ami #ifndef __iwl_context_info_file_gen3_h__ 62ee82402SGolan Ben Ami #define __iwl_context_info_file_gen3_h__ 72ee82402SGolan Ben Ami 82ee82402SGolan Ben Ami #include "iwl-context-info.h" 92ee82402SGolan Ben Ami 102ee82402SGolan Ben Ami #define CSR_CTXT_INFO_BOOT_CTRL 0x0 112ee82402SGolan Ben Ami #define CSR_CTXT_INFO_ADDR 0x118 122ee82402SGolan Ben Ami #define CSR_IML_DATA_ADDR 0x120 132ee82402SGolan Ben Ami #define CSR_IML_SIZE_ADDR 0x128 149b58419eSGolan Ben Ami #define CSR_IML_RESP_ADDR 0x12c 152ee82402SGolan Ben Ami 165f408503SAlon Giladi #define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2 175f408503SAlon Giladi 182ee82402SGolan Ben Ami /* Set bit for enabling automatic function boot */ 192ee82402SGolan Ben Ami #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 202ee82402SGolan Ben Ami /* Set bit for initiating function boot */ 212ee82402SGolan Ben Ami #define CSR_AUTO_FUNC_INIT BIT(7) 222ee82402SGolan Ben Ami 232ee82402SGolan Ben Ami /** 242ee82402SGolan Ben Ami * enum iwl_prph_scratch_mtr_format - tfd size configuration 252ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 262ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 272ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 282ee82402SGolan Ben Ami * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 292ee82402SGolan Ben Ami */ 302ee82402SGolan Ben Ami enum iwl_prph_scratch_mtr_format { 312ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_16B = 0x0, 322ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_32B = 0x40000, 332ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_64B = 0x80000, 342ee82402SGolan Ben Ami IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 352ee82402SGolan Ben Ami }; 362ee82402SGolan Ben Ami 372ee82402SGolan Ben Ami /** 382ee82402SGolan Ben Ami * enum iwl_prph_scratch_flags - PRPH scratch control flags 391c4db761SMukesh Sisodiya * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 402ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 412ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 422ee82402SGolan Ben Ami * in hwm config. 432ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 442ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 452ee82402SGolan Ben Ami * multicomm. 462ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 472ee82402SGolan Ben Ami * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 482ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 492ee82402SGolan Ben Ami * completion descriptor, 1 for responses (legacy) 502ee82402SGolan Ben Ami * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 512ee82402SGolan Ben Ami * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 522ee82402SGolan Ben Ami * 3: 256 bit. 5361576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 5461576240SJohannes Berg * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 5561576240SJohannes Berg * appropriately; use the below values for this. 5661576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 5761576240SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 583fa965c2SJohannes Berg * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 592ee82402SGolan Ben Ami */ 602ee82402SGolan Ben Ami enum iwl_prph_scratch_flags { 611c4db761SMukesh Sisodiya IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1), 622ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 632ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 642ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 652ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 662ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 672ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 682ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 692ee82402SGolan Ben Ami IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 7061576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 7161576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 7261576240SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 733fa965c2SJohannes Berg IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 742ee82402SGolan Ben Ami }; 752ee82402SGolan Ben Ami 762ee82402SGolan Ben Ami /* 772ee82402SGolan Ben Ami * struct iwl_prph_scratch_version - version structure 782ee82402SGolan Ben Ami * @mac_id: SKU and revision id 792ee82402SGolan Ben Ami * @version: prph scratch information version id 802ee82402SGolan Ben Ami * @size: the size of the context information in DWs 812ee82402SGolan Ben Ami * @reserved: reserved 822ee82402SGolan Ben Ami */ 832ee82402SGolan Ben Ami struct iwl_prph_scratch_version { 842ee82402SGolan Ben Ami __le16 mac_id; 852ee82402SGolan Ben Ami __le16 version; 862ee82402SGolan Ben Ami __le16 size; 872ee82402SGolan Ben Ami __le16 reserved; 882ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_VERSION_S */ 892ee82402SGolan Ben Ami 902ee82402SGolan Ben Ami /* 912ee82402SGolan Ben Ami * struct iwl_prph_scratch_control - control structure 922ee82402SGolan Ben Ami * @control_flags: context information flags see &enum iwl_prph_scratch_flags 932ee82402SGolan Ben Ami * @reserved: reserved 942ee82402SGolan Ben Ami */ 952ee82402SGolan Ben Ami struct iwl_prph_scratch_control { 962ee82402SGolan Ben Ami __le32 control_flags; 972ee82402SGolan Ben Ami __le32 reserved; 982ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 992ee82402SGolan Ben Ami 1002ee82402SGolan Ben Ami /* 101*7c9c8477SAlon Giladi * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch 1027ef3e224SLuca Coelho * @pnvm_base_addr: PNVM start address 103*7c9c8477SAlon Giladi * @pnvm_size: the size of the PNVM image in bytes 1042ee82402SGolan Ben Ami * @reserved: reserved 1052ee82402SGolan Ben Ami */ 1067ef3e224SLuca Coelho struct iwl_prph_scratch_pnvm_cfg { 1077ef3e224SLuca Coelho __le64 pnvm_base_addr; 1087ef3e224SLuca Coelho __le32 pnvm_size; 1092ee82402SGolan Ben Ami __le32 reserved; 1107ef3e224SLuca Coelho } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 1112ee82402SGolan Ben Ami 11263b9e7b9SAlon Giladi /** 11363b9e7b9SAlon Giladi * struct iwl_prph_scrath_mem_desc_addr_array 11463b9e7b9SAlon Giladi * @mem_descs: array of dram addresses. 11563b9e7b9SAlon Giladi * Each address is the beggining of a pnvm payload. 11663b9e7b9SAlon Giladi */ 11763b9e7b9SAlon Giladi struct iwl_prph_scrath_mem_desc_addr_array { 11863b9e7b9SAlon Giladi __le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 11963b9e7b9SAlon Giladi } __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */ 1202ee82402SGolan Ben Ami /* 1212ee82402SGolan Ben Ami * struct iwl_prph_scratch_hwm_cfg - hwm config 1222ee82402SGolan Ben Ami * @hwm_base_addr: hwm start address 1232ee82402SGolan Ben Ami * @hwm_size: hwm size in DWs 124f21baf24SMukesh Sisodiya * @debug_token_config: debug preset 1252ee82402SGolan Ben Ami */ 1262ee82402SGolan Ben Ami struct iwl_prph_scratch_hwm_cfg { 1272ee82402SGolan Ben Ami __le64 hwm_base_addr; 1282ee82402SGolan Ben Ami __le32 hwm_size; 129f21baf24SMukesh Sisodiya __le32 debug_token_config; 1302ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 1312ee82402SGolan Ben Ami 1322ee82402SGolan Ben Ami /* 1332ee82402SGolan Ben Ami * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 1342ee82402SGolan Ben Ami * @free_rbd_addr: default queue free RB CB base address 1352ee82402SGolan Ben Ami * @reserved: reserved 1362ee82402SGolan Ben Ami */ 1372ee82402SGolan Ben Ami struct iwl_prph_scratch_rbd_cfg { 1382ee82402SGolan Ben Ami __le64 free_rbd_addr; 1392ee82402SGolan Ben Ami __le32 reserved; 1402ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 1412ee82402SGolan Ben Ami 1422ee82402SGolan Ben Ami /* 1439dad325fSLuca Coelho * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table 1449dad325fSLuca Coelho * @base_addr: reduce power table address 145*7c9c8477SAlon Giladi * @size: the size of the entire power table image 1469dad325fSLuca Coelho */ 1479dad325fSLuca Coelho struct iwl_prph_scratch_uefi_cfg { 1489dad325fSLuca Coelho __le64 base_addr; 1499dad325fSLuca Coelho __le32 size; 1509dad325fSLuca Coelho __le32 reserved; 1519dad325fSLuca Coelho } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 1529dad325fSLuca Coelho 1539dad325fSLuca Coelho /* 15409b4c35dSAyala Barazani * struct iwl_prph_scratch_step_cfg - prph scratch step configuration 15509b4c35dSAyala Barazani * @mbx_addr_0: [0:7] revision, 15609b4c35dSAyala Barazani * [8:15] cnvi_to_cnvr length, 15709b4c35dSAyala Barazani * [16:23] cnvr_to_cnvi channel length, 15809b4c35dSAyala Barazani * [24:31] radio1 reserved 15909b4c35dSAyala Barazani * @mbx_addr_1: [0:7] radio2 reserved 16009b4c35dSAyala Barazani */ 16109b4c35dSAyala Barazani 16209b4c35dSAyala Barazani struct iwl_prph_scratch_step_cfg { 16309b4c35dSAyala Barazani __le32 mbx_addr_0; 16409b4c35dSAyala Barazani __le32 mbx_addr_1; 16509b4c35dSAyala Barazani } __packed; 16609b4c35dSAyala Barazani 16709b4c35dSAyala Barazani /* 1682ee82402SGolan Ben Ami * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 1692ee82402SGolan Ben Ami * @version: version information of context info and HW 1702ee82402SGolan Ben Ami * @control: control flags of FH configurations 1717ef3e224SLuca Coelho * @pnvm_cfg: ror configuration 1722ee82402SGolan Ben Ami * @hwm_cfg: hwm configuration 1732ee82402SGolan Ben Ami * @rbd_cfg: default RX queue configuration 17409b4c35dSAyala Barazani * @step_cfg: step configuration 1752ee82402SGolan Ben Ami */ 1762ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg { 1772ee82402SGolan Ben Ami struct iwl_prph_scratch_version version; 1782ee82402SGolan Ben Ami struct iwl_prph_scratch_control control; 1797ef3e224SLuca Coelho struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 1802ee82402SGolan Ben Ami struct iwl_prph_scratch_hwm_cfg hwm_cfg; 1812ee82402SGolan Ben Ami struct iwl_prph_scratch_rbd_cfg rbd_cfg; 1829dad325fSLuca Coelho struct iwl_prph_scratch_uefi_cfg reduce_power_cfg; 18309b4c35dSAyala Barazani struct iwl_prph_scratch_step_cfg step_cfg; 1842ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 1852ee82402SGolan Ben Ami 1862ee82402SGolan Ben Ami /* 1872ee82402SGolan Ben Ami * struct iwl_prph_scratch - peripheral scratch mapping 1882ee82402SGolan Ben Ami * @ctrl_cfg: control and configuration of prph scratch 1892ee82402SGolan Ben Ami * @dram: firmware images addresses in DRAM 1902ee82402SGolan Ben Ami * @reserved: reserved 1912ee82402SGolan Ben Ami */ 1922ee82402SGolan Ben Ami struct iwl_prph_scratch { 1932ee82402SGolan Ben Ami struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 19409b4c35dSAyala Barazani __le32 reserved[10]; 1952ee82402SGolan Ben Ami struct iwl_context_info_dram dram; 1962ee82402SGolan Ben Ami } __packed; /* PERIPH_SCRATCH_S */ 1972ee82402SGolan Ben Ami 1982ee82402SGolan Ben Ami /* 1992ee82402SGolan Ben Ami * struct iwl_prph_info - peripheral information 2002ee82402SGolan Ben Ami * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 2012ee82402SGolan Ben Ami * @ipc_status_mirror: reflects the value in the IPC Status CSR register 2022ee82402SGolan Ben Ami * @sleep_notif: indicates the peripheral sleep status 2032ee82402SGolan Ben Ami * @reserved: reserved 2042ee82402SGolan Ben Ami */ 2052ee82402SGolan Ben Ami struct iwl_prph_info { 2062ee82402SGolan Ben Ami __le32 boot_stage_mirror; 2072ee82402SGolan Ben Ami __le32 ipc_status_mirror; 2082ee82402SGolan Ben Ami __le32 sleep_notif; 2092ee82402SGolan Ben Ami __le32 reserved; 2102ee82402SGolan Ben Ami } __packed; /* PERIPH_INFO_S */ 2112ee82402SGolan Ben Ami 2122ee82402SGolan Ben Ami /* 2132ee82402SGolan Ben Ami * struct iwl_context_info_gen3 - device INIT configuration 2142ee82402SGolan Ben Ami * @version: version of the context information 2152ee82402SGolan Ben Ami * @size: size of context information in DWs 2162ee82402SGolan Ben Ami * @config: context in which the peripheral would execute - a subset of 2172ee82402SGolan Ben Ami * capability csr register published by the peripheral 2182ee82402SGolan Ben Ami * @prph_info_base_addr: the peripheral information structure start address 2192ee82402SGolan Ben Ami * @cr_head_idx_arr_base_addr: the completion ring head index array 2202ee82402SGolan Ben Ami * start address 2212ee82402SGolan Ben Ami * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 2222ee82402SGolan Ben Ami * start address 2232ee82402SGolan Ben Ami * @cr_tail_idx_arr_base_addr: the completion ring tail index array 2242ee82402SGolan Ben Ami * start address 2252ee82402SGolan Ben Ami * @tr_head_idx_arr_base_addr: the transfer ring head index array 2262ee82402SGolan Ben Ami * start address 2272ee82402SGolan Ben Ami * @cr_idx_arr_size: number of entries in the completion ring index array 2282ee82402SGolan Ben Ami * @tr_idx_arr_size: number of entries in the transfer ring index array 2292ee82402SGolan Ben Ami * @mtr_base_addr: the message transfer ring start address 2302ee82402SGolan Ben Ami * @mcr_base_addr: the message completion ring start address 2312ee82402SGolan Ben Ami * @mtr_size: number of entries which the message transfer ring can hold 2322ee82402SGolan Ben Ami * @mcr_size: number of entries which the message completion ring can hold 2332ee82402SGolan Ben Ami * @mtr_doorbell_vec: the doorbell vector associated with the message 2342ee82402SGolan Ben Ami * transfer ring 2352ee82402SGolan Ben Ami * @mcr_doorbell_vec: the doorbell vector associated with the message 2362ee82402SGolan Ben Ami * completion ring 2372ee82402SGolan Ben Ami * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 2382ee82402SGolan Ben Ami * completing a transfer descriptor in the message transfer ring 2392ee82402SGolan Ben Ami * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 2402ee82402SGolan Ben Ami * completing a completion descriptor in the message completion ring 2412ee82402SGolan Ben Ami * @mtr_opt_header_size: the size of the optional header in the transfer 2422ee82402SGolan Ben Ami * descriptor associated with the message transfer ring in DWs 2432ee82402SGolan Ben Ami * @mtr_opt_footer_size: the size of the optional footer in the transfer 2442ee82402SGolan Ben Ami * descriptor associated with the message transfer ring in DWs 2452ee82402SGolan Ben Ami * @mcr_opt_header_size: the size of the optional header in the completion 2462ee82402SGolan Ben Ami * descriptor associated with the message completion ring in DWs 2472ee82402SGolan Ben Ami * @mcr_opt_footer_size: the size of the optional footer in the completion 2482ee82402SGolan Ben Ami * descriptor associated with the message completion ring in DWs 2492ee82402SGolan Ben Ami * @msg_rings_ctrl_flags: message rings control flags 2502ee82402SGolan Ben Ami * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 2512ee82402SGolan Ben Ami * after updating the Peripheral Information structure 2522ee82402SGolan Ben Ami * @prph_scratch_base_addr: the peripheral scratch structure start address 2532ee82402SGolan Ben Ami * @prph_scratch_size: the size of the peripheral scratch structure in DWs 2542ee82402SGolan Ben Ami * @reserved: reserved 2552ee82402SGolan Ben Ami */ 2562ee82402SGolan Ben Ami struct iwl_context_info_gen3 { 2572ee82402SGolan Ben Ami __le16 version; 2582ee82402SGolan Ben Ami __le16 size; 2592ee82402SGolan Ben Ami __le32 config; 2602ee82402SGolan Ben Ami __le64 prph_info_base_addr; 2612ee82402SGolan Ben Ami __le64 cr_head_idx_arr_base_addr; 2622ee82402SGolan Ben Ami __le64 tr_tail_idx_arr_base_addr; 2632ee82402SGolan Ben Ami __le64 cr_tail_idx_arr_base_addr; 2642ee82402SGolan Ben Ami __le64 tr_head_idx_arr_base_addr; 2652ee82402SGolan Ben Ami __le16 cr_idx_arr_size; 2662ee82402SGolan Ben Ami __le16 tr_idx_arr_size; 2672ee82402SGolan Ben Ami __le64 mtr_base_addr; 2682ee82402SGolan Ben Ami __le64 mcr_base_addr; 2692ee82402SGolan Ben Ami __le16 mtr_size; 2702ee82402SGolan Ben Ami __le16 mcr_size; 2712ee82402SGolan Ben Ami __le16 mtr_doorbell_vec; 2722ee82402SGolan Ben Ami __le16 mcr_doorbell_vec; 2732ee82402SGolan Ben Ami __le16 mtr_msi_vec; 2742ee82402SGolan Ben Ami __le16 mcr_msi_vec; 2752ee82402SGolan Ben Ami u8 mtr_opt_header_size; 2762ee82402SGolan Ben Ami u8 mtr_opt_footer_size; 2772ee82402SGolan Ben Ami u8 mcr_opt_header_size; 2782ee82402SGolan Ben Ami u8 mcr_opt_footer_size; 2792ee82402SGolan Ben Ami __le16 msg_rings_ctrl_flags; 2802ee82402SGolan Ben Ami __le16 prph_info_msi_vec; 2812ee82402SGolan Ben Ami __le64 prph_scratch_base_addr; 2822ee82402SGolan Ben Ami __le32 prph_scratch_size; 2832ee82402SGolan Ben Ami __le32 reserved; 2842ee82402SGolan Ben Ami } __packed; /* IPC_CONTEXT_INFO_S */ 2852ee82402SGolan Ben Ami 2862ee82402SGolan Ben Ami int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 2872ee82402SGolan Ben Ami const struct fw_img *fw); 28894768975SJohannes Berg void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive); 2892ee82402SGolan Ben Ami 290194d1f84SAlon Giladi int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans, 29133182810SAlon Giladi const struct iwl_pnvm_image *pnvm_payloads, 29233182810SAlon Giladi const struct iwl_ucode_capabilities *capa); 29333182810SAlon Giladi void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 29433182810SAlon Giladi const struct iwl_ucode_capabilities *capa); 295*7c9c8477SAlon Giladi int 296*7c9c8477SAlon Giladi iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans, 297*7c9c8477SAlon Giladi const struct iwl_pnvm_image *payloads, 298*7c9c8477SAlon Giladi const struct iwl_ucode_capabilities *capa); 299*7c9c8477SAlon Giladi void 300*7c9c8477SAlon Giladi iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 301*7c9c8477SAlon Giladi const struct iwl_ucode_capabilities *capa); 30209b4c35dSAyala Barazani int iwl_trans_pcie_ctx_info_gen3_set_step(struct iwl_trans *trans, 30309b4c35dSAyala Barazani u32 mbx_addr_0_step, u32 mbx_addr_1_step); 3042ee82402SGolan Ben Ami #endif /* __iwl_context_info_file_gen3_h__ */ 305